| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | /* |
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| 3 | * Copyright © 2023 Intel Corporation |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __INTEL_PSR_REGS_H__ |
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| 7 | #define __INTEL_PSR_REGS_H__ |
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| 8 | |
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| 9 | #include "intel_display_reg_defs.h" |
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| 10 | #include "intel_dp_aux_regs.h" |
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| 11 | |
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| 12 | #define TRANS_EXITLINE(trans) _MMIO_TRANS2((trans), _TRANS_EXITLINE_A) |
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| 13 | #define EXITLINE_ENABLE REG_BIT(31) |
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| 14 | #define EXITLINE_MASK REG_GENMASK(12, 0) |
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| 15 | #define EXITLINE_SHIFT 0 |
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| 16 | |
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| 17 | /* |
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| 18 | * HSW+ eDP PSR registers |
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| 19 | * |
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| 20 | * HSW PSR registers are relative to DDIA(_DDI_BUF_CTL_A + 0x800) with just one |
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| 21 | * instance of it |
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| 22 | */ |
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| 23 | #define HSW_SRD_CTL _MMIO(0x64800) |
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| 24 | #define _SRD_CTL_A 0x60800 |
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| 25 | #define _SRD_CTL_EDP 0x6f800 |
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| 26 | #define EDP_PSR_CTL(tran) _MMIO_TRANS2(tran, _SRD_CTL_A) |
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| 27 | #define EDP_PSR_ENABLE REG_BIT(31) |
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| 28 | #define BDW_PSR_SINGLE_FRAME REG_BIT(30) |
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| 29 | #define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK REG_BIT(29) /* SW can't modify */ |
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| 30 | #define EDP_PSR_LINK_STANDBY REG_BIT(27) |
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| 31 | #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK REG_GENMASK(26, 25) |
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| 32 | #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES REG_FIELD_PREP(EDP_PSR_MIN_LINK_ENTRY_TIME_MASK, 0) |
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| 33 | #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES REG_FIELD_PREP(EDP_PSR_MIN_LINK_ENTRY_TIME_MASK, 1) |
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| 34 | #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES REG_FIELD_PREP(EDP_PSR_MIN_LINK_ENTRY_TIME_MASK, 2) |
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| 35 | #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES REG_FIELD_PREP(EDP_PSR_MIN_LINK_ENTRY_TIME_MASK, 3) |
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| 36 | #define EDP_PSR_MAX_SLEEP_TIME_MASK REG_GENMASK(24, 20) |
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| 37 | #define EDP_PSR_MAX_SLEEP_TIME(x) REG_FIELD_PREP(EDP_PSR_MAX_SLEEP_TIME_MASK, (x)) |
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| 38 | #define LNL_EDP_PSR_ENTRY_SETUP_FRAMES_MASK REG_GENMASK(17, 16) |
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| 39 | #define LNL_EDP_PSR_ENTRY_SETUP_FRAMES(x) REG_FIELD_PREP(LNL_EDP_PSR_ENTRY_SETUP_FRAMES_MASK, (x)) |
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| 40 | #define EDP_PSR_SKIP_AUX_EXIT REG_BIT(12) |
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| 41 | #define EDP_PSR_TP_MASK REG_BIT(11) |
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| 42 | #define EDP_PSR_TP_TP1_TP2 REG_FIELD_PREP(EDP_PSR_TP_MASK, 0) |
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| 43 | #define EDP_PSR_TP_TP1_TP3 REG_FIELD_PREP(EDP_PSR_TP_MASK, 1) |
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| 44 | #define EDP_PSR_CRC_ENABLE REG_BIT(10) /* BDW+ */ |
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| 45 | #define EDP_PSR_TP2_TP3_TIME_MASK REG_GENMASK(9, 8) |
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| 46 | #define EDP_PSR_TP2_TP3_TIME_500us REG_FIELD_PREP(EDP_PSR_TP2_TP3_TIME_MASK, 0) |
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| 47 | #define EDP_PSR_TP2_TP3_TIME_100us REG_FIELD_PREP(EDP_PSR_TP2_TP3_TIME_MASK, 1) |
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| 48 | #define EDP_PSR_TP2_TP3_TIME_2500us REG_FIELD_PREP(EDP_PSR_TP2_TP3_TIME_MASK, 2) |
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| 49 | #define EDP_PSR_TP2_TP3_TIME_0us REG_FIELD_PREP(EDP_PSR_TP2_TP3_TIME_MASK, 3) |
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| 50 | #define EDP_PSR_TP4_TIME_MASK REG_GENMASK(7, 6) |
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| 51 | #define EDP_PSR_TP4_TIME_0us REG_FIELD_PREP(EDP_PSR_TP4_TIME_MASK, 3) /* ICL+ */ |
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| 52 | #define EDP_PSR_TP1_TIME_MASK REG_GENMASK(5, 4) |
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| 53 | #define EDP_PSR_TP1_TIME_500us REG_FIELD_PREP(EDP_PSR_TP1_TIME_MASK, 0) |
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| 54 | #define EDP_PSR_TP1_TIME_100us REG_FIELD_PREP(EDP_PSR_TP1_TIME_MASK, 1) |
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| 55 | #define EDP_PSR_TP1_TIME_2500us REG_FIELD_PREP(EDP_PSR_TP1_TIME_MASK, 2) |
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| 56 | #define EDP_PSR_TP1_TIME_0us REG_FIELD_PREP(EDP_PSR_TP1_TIME_MASK, 3) |
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| 57 | #define EDP_PSR_IDLE_FRAMES_MASK REG_GENMASK(3, 0) |
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| 58 | #define EDP_PSR_IDLE_FRAMES(x) REG_FIELD_PREP(EDP_PSR_IDLE_FRAMES_MASK, (x)) |
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| 59 | |
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| 60 | /* |
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| 61 | * Until TGL, IMR/IIR are fixed at 0x648xx. On TGL+ those registers are relative |
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| 62 | * to transcoder and bits defined for each one as if using no shift (i.e. as if |
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| 63 | * it was for TRANSCODER_EDP) |
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| 64 | */ |
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| 65 | #define EDP_PSR_IMR _MMIO(0x64834) |
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| 66 | #define EDP_PSR_IIR _MMIO(0x64838) |
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| 67 | #define _PSR_IMR_A 0x60814 |
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| 68 | #define _PSR_IIR_A 0x60818 |
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| 69 | #define TRANS_PSR_IMR(tran) _MMIO_TRANS2(tran, _PSR_IMR_A) |
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| 70 | #define TRANS_PSR_IIR(tran) _MMIO_TRANS2(tran, _PSR_IIR_A) |
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| 71 | #define _EDP_PSR_TRANS_SHIFT(trans) ((trans) == TRANSCODER_EDP ? \ |
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| 72 | 0 : ((trans) - TRANSCODER_A + 1) * 8) |
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| 73 | #define TGL_PSR_MASK REG_GENMASK(2, 0) |
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| 74 | #define TGL_PSR_ERROR REG_BIT(2) |
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| 75 | #define TGL_PSR_POST_EXIT REG_BIT(1) |
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| 76 | #define TGL_PSR_PRE_ENTRY REG_BIT(0) |
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| 77 | #define EDP_PSR_MASK(trans) (TGL_PSR_MASK << \ |
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| 78 | _EDP_PSR_TRANS_SHIFT(trans)) |
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| 79 | #define EDP_PSR_ERROR(trans) (TGL_PSR_ERROR << \ |
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| 80 | _EDP_PSR_TRANS_SHIFT(trans)) |
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| 81 | #define EDP_PSR_POST_EXIT(trans) (TGL_PSR_POST_EXIT << \ |
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| 82 | _EDP_PSR_TRANS_SHIFT(trans)) |
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| 83 | #define EDP_PSR_PRE_ENTRY(trans) (TGL_PSR_PRE_ENTRY << \ |
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| 84 | _EDP_PSR_TRANS_SHIFT(trans)) |
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| 85 | |
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| 86 | #define HSW_SRD_AUX_CTL _MMIO(0x64810) |
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| 87 | #define _SRD_AUX_CTL_A 0x60810 |
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| 88 | #define _SRD_AUX_CTL_EDP 0x6f810 |
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| 89 | #define EDP_PSR_AUX_CTL(tran) _MMIO_TRANS2(tran, _SRD_AUX_CTL_A) |
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| 90 | #define EDP_PSR_AUX_CTL_TIME_OUT_MASK DP_AUX_CH_CTL_TIME_OUT_MASK |
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| 91 | #define EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK DP_AUX_CH_CTL_MESSAGE_SIZE_MASK |
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| 92 | #define EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK DP_AUX_CH_CTL_PRECHARGE_2US_MASK |
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| 93 | #define EDP_PSR_AUX_CTL_ERROR_INTERRUPT REG_BIT(11) |
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| 94 | #define EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK |
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| 95 | |
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| 96 | #define HSW_SRD_AUX_DATA(i) _MMIO(0x64814 + (i) * 4) /* 5 registers */ |
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| 97 | #define _SRD_AUX_DATA_A 0x60814 |
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| 98 | #define _SRD_AUX_DATA_EDP 0x6f814 |
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| 99 | #define EDP_PSR_AUX_DATA(tran, i) _MMIO_TRANS2(tran, _SRD_AUX_DATA_A + (i) * 4) /* 5 registers */ |
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| 100 | |
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| 101 | #define HSW_SRD_STATUS _MMIO(0x64840) |
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| 102 | #define _SRD_STATUS_A 0x60840 |
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| 103 | #define _SRD_STATUS_EDP 0x6f840 |
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| 104 | #define EDP_PSR_STATUS(tran) _MMIO_TRANS2(tran, _SRD_STATUS_A) |
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| 105 | #define EDP_PSR_STATUS_STATE_MASK REG_GENMASK(31, 29) |
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| 106 | #define EDP_PSR_STATUS_STATE_IDLE REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 0) |
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| 107 | #define EDP_PSR_STATUS_STATE_SRDONACK REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 1) |
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| 108 | #define EDP_PSR_STATUS_STATE_SRDENT REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 2) |
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| 109 | #define EDP_PSR_STATUS_STATE_BUFOFF REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 3) |
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| 110 | #define EDP_PSR_STATUS_STATE_BUFON REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 4) |
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| 111 | #define EDP_PSR_STATUS_STATE_AUXACK REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 5) |
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| 112 | #define EDP_PSR_STATUS_STATE_SRDOFFACK REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 6) |
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| 113 | #define EDP_PSR_STATUS_LINK_MASK REG_GENMASK(27, 26) |
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| 114 | #define EDP_PSR_STATUS_LINK_FULL_OFF REG_FIELD_PREP(EDP_PSR_STATUS_LINK_MASK, 0) |
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| 115 | #define EDP_PSR_STATUS_LINK_FULL_ON REG_FIELD_PREP(EDP_PSR_STATUS_LINK_MASK, 1) |
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| 116 | #define EDP_PSR_STATUS_LINK_STANDBY REG_FIELD_PREP(EDP_PSR_STATUS_LINK_MASK, 2) |
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| 117 | #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK REG_GENMASK(24, 20) |
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| 118 | #define EDP_PSR_STATUS_COUNT_MASK REG_GENMASK(19, 16) |
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| 119 | #define EDP_PSR_STATUS_AUX_ERROR REG_BIT(15) |
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| 120 | #define EDP_PSR_STATUS_AUX_SENDING REG_BIT(12) |
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| 121 | #define EDP_PSR_STATUS_SENDING_IDLE REG_BIT(9) |
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| 122 | #define EDP_PSR_STATUS_SENDING_TP2_TP3 REG_BIT(8) |
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| 123 | #define EDP_PSR_STATUS_SENDING_TP1 REG_BIT(4) |
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| 124 | #define EDP_PSR_STATUS_IDLE_MASK REG_GENMASK(3, 0) |
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| 125 | |
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| 126 | #define HSW_SRD_PERF_CNT _MMIO(0x64844) |
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| 127 | #define _SRD_PERF_CNT_A 0x60844 |
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| 128 | #define _SRD_PERF_CNT_EDP 0x6f844 |
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| 129 | #define EDP_PSR_PERF_CNT(tran) _MMIO_TRANS2(tran, _SRD_PERF_CNT_A) |
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| 130 | #define EDP_PSR_PERF_CNT_MASK REG_GENMASK(23, 0) |
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| 131 | |
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| 132 | /* PSR_MASK on SKL+ */ |
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| 133 | #define HSW_SRD_DEBUG _MMIO(0x64860) |
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| 134 | #define _SRD_DEBUG_A 0x60860 |
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| 135 | #define _SRD_DEBUG_EDP 0x6f860 |
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| 136 | #define EDP_PSR_DEBUG(tran) _MMIO_TRANS2(tran, _SRD_DEBUG_A) |
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| 137 | #define EDP_PSR_DEBUG_MASK_MAX_SLEEP REG_BIT(28) |
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| 138 | #define EDP_PSR_DEBUG_MASK_LPSP REG_BIT(27) |
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| 139 | #define EDP_PSR_DEBUG_MASK_MEMUP REG_BIT(26) |
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| 140 | #define EDP_PSR_DEBUG_MASK_HPD REG_BIT(25) |
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| 141 | #define EDP_PSR_DEBUG_MASK_FBC_MODIFY REG_BIT(24) |
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| 142 | #define EDP_PSR_DEBUG_MASK_PRIMARY_FLIP REG_BIT(23) /* hsw */ |
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| 143 | #define EDP_PSR_DEBUG_MASK_HDCP_ENABLE REG_BIT(22) /* hsw/bdw */ |
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| 144 | #define EDP_PSR_DEBUG_MASK_SPRITE_ENABLE REG_BIT(21) /* hsw */ |
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| 145 | #define EDP_PSR_DEBUG_MASK_CURSOR_MOVE REG_BIT(20) /* hsw */ |
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| 146 | #define EDP_PSR_DEBUG_MASK_VBLANK_VSYNC_INT REG_BIT(19) /* hsw */ |
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| 147 | #define EDP_PSR_DEBUG_MASK_DPST_PHASE_IN REG_BIT(18) /* hsw */ |
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| 148 | #define EDP_PSR_DEBUG_MASK_KVMR_SESSION_EN REG_BIT(17) |
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| 149 | #define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE REG_BIT(16) /* hsw-skl */ |
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| 150 | #define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN REG_BIT(15) /* skl+ */ |
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| 151 | #define EDP_PSR_DEBUG_RFB_UPDATE_SENT REG_BIT(2) /* bdw */ |
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| 152 | #define EDP_PSR_DEBUG_ENTRY_COMPLETION REG_BIT(1) /* hsw/bdw */ |
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| 153 | |
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| 154 | #define _PSR2_CTL_A 0x60900 |
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| 155 | #define _PSR2_CTL_EDP 0x6f900 |
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| 156 | #define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A) |
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| 157 | #define EDP_PSR2_ENABLE REG_BIT(31) |
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| 158 | #define EDP_SU_TRACK_ENABLE REG_BIT(30) /* up to adl-p */ |
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| 159 | #define TGL_EDP_PSR2_BLOCK_COUNT_MASK REG_BIT(28) |
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| 160 | #define TGL_EDP_PSR2_BLOCK_COUNT_NUM_2 REG_FIELD_PREP(TGL_EDP_PSR2_BLOCK_COUNT_MASK, 0) |
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| 161 | #define TGL_EDP_PSR2_BLOCK_COUNT_NUM_3 REG_FIELD_PREP(TGL_EDP_PSR2_BLOCK_COUNT_MASK, 1) |
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| 162 | #define LNL_EDP_PSR2_SU_REGION_ET_ENABLE REG_BIT(27) |
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| 163 | #define EDP_Y_COORDINATE_ENABLE REG_BIT(25) /* display 10, 11 and 12 */ |
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| 164 | #define EDP_PSR2_SU_SDP_SCANLINE REG_BIT(25) /* display 13+ */ |
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| 165 | #define EDP_MAX_SU_DISABLE_TIME_MASK REG_GENMASK(24, 20) |
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| 166 | #define EDP_MAX_SU_DISABLE_TIME(t) REG_FIELD_PREP(EDP_MAX_SU_DISABLE_TIME, (t)) |
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| 167 | #define EDP_PSR2_IO_BUFFER_WAKE_MASK REG_GENMASK(14, 13) |
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| 168 | #define EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES 8 |
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| 169 | #define EDP_PSR2_IO_BUFFER_WAKE(lines) REG_FIELD_PREP(EDP_PSR2_IO_BUFFER_WAKE_MASK, \ |
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| 170 | EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines)) |
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| 171 | #define TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK REG_GENMASK(15, 13) |
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| 172 | #define TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5 |
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| 173 | #define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) REG_FIELD_PREP(TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK, \ |
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| 174 | (lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) |
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| 175 | #define EDP_PSR2_FAST_WAKE_MASK REG_GENMASK(12, 11) |
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| 176 | #define EDP_PSR2_FAST_WAKE_MAX_LINES 8 |
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| 177 | #define EDP_PSR2_FAST_WAKE(lines) REG_FIELD_PREP(EDP_PSR2_FAST_WAKE_MASK, \ |
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| 178 | EDP_PSR2_FAST_WAKE_MAX_LINES - (lines)) |
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| 179 | #define TGL_EDP_PSR2_FAST_WAKE_MASK REG_GENMASK(12, 10) |
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| 180 | #define TGL_EDP_PSR2_FAST_WAKE_MIN_LINES 5 |
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| 181 | #define TGL_EDP_PSR2_FAST_WAKE(lines) REG_FIELD_PREP(TGL_EDP_PSR2_FAST_WAKE_MASK, \ |
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| 182 | (lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) |
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| 183 | #define EDP_PSR2_TP2_TIME_MASK REG_GENMASK(9, 8) |
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| 184 | #define EDP_PSR2_TP2_TIME_500us REG_FIELD_PREP(EDP_PSR2_TP2_TIME_MASK, 0) |
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| 185 | #define EDP_PSR2_TP2_TIME_100us REG_FIELD_PREP(EDP_PSR2_TP2_TIME_MASK, 1) |
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| 186 | #define EDP_PSR2_TP2_TIME_2500us REG_FIELD_PREP(EDP_PSR2_TP2_TIME_MASK, 2) |
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| 187 | #define EDP_PSR2_TP2_TIME_50us REG_FIELD_PREP(EDP_PSR2_TP2_TIME_MASK, 3) |
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| 188 | #define EDP_PSR2_FRAME_BEFORE_SU_MASK REG_GENMASK(7, 4) |
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| 189 | #define EDP_PSR2_FRAME_BEFORE_SU(a) REG_FIELD_PREP(EDP_PSR2_FRAME_BEFORE_SU_MASK, (a)) |
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| 190 | #define EDP_PSR2_IDLE_FRAMES_MASK REG_GENMASK(3, 0) |
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| 191 | #define EDP_PSR2_IDLE_FRAMES(x) REG_FIELD_PREP(EDP_PSR2_IDLE_FRAMES_MASK, (x)) |
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| 192 | |
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| 193 | #define _PSR_EVENT_TRANS_A 0x60848 |
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| 194 | #define _PSR_EVENT_TRANS_B 0x61848 |
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| 195 | #define _PSR_EVENT_TRANS_C 0x62848 |
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| 196 | #define _PSR_EVENT_TRANS_D 0x63848 |
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| 197 | #define _PSR_EVENT_TRANS_EDP 0x6f848 |
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| 198 | #define PSR_EVENT(tran) _MMIO_TRANS2(tran, _PSR_EVENT_TRANS_A) |
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| 199 | #define PSR_EVENT_PSR2_WD_TIMER_EXPIRE REG_BIT(17) |
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| 200 | #define PSR_EVENT_PSR2_DISABLED REG_BIT(16) |
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| 201 | #define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN REG_BIT(15) |
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| 202 | #define PSR_EVENT_SU_CRC_FIFO_UNDERRUN REG_BIT(14) |
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| 203 | #define PSR_EVENT_GRAPHICS_RESET REG_BIT(12) |
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| 204 | #define PSR_EVENT_PCH_INTERRUPT REG_BIT(11) |
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| 205 | #define PSR_EVENT_MEMORY_UP REG_BIT(10) |
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| 206 | #define PSR_EVENT_FRONT_BUFFER_MODIFY REG_BIT(9) |
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| 207 | #define PSR_EVENT_WD_TIMER_EXPIRE REG_BIT(8) |
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| 208 | #define PSR_EVENT_PIPE_REGISTERS_UPDATE REG_BIT(6) |
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| 209 | #define PSR_EVENT_REGISTER_UPDATE REG_BIT(5) /* Reserved in ICL+ */ |
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| 210 | #define PSR_EVENT_HDCP_ENABLE REG_BIT(4) |
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| 211 | #define PSR_EVENT_KVMR_SESSION_ENABLE REG_BIT(3) |
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| 212 | #define PSR_EVENT_VBI_ENABLE REG_BIT(2) |
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| 213 | #define PSR_EVENT_LPSP_MODE_EXIT REG_BIT(1) |
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| 214 | #define PSR_EVENT_PSR_DISABLE REG_BIT(0) |
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| 215 | |
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| 216 | #define _PSR2_STATUS_A 0x60940 |
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| 217 | #define _PSR2_STATUS_EDP 0x6f940 |
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| 218 | #define EDP_PSR2_STATUS(tran) _MMIO_TRANS2(tran, _PSR2_STATUS_A) |
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| 219 | #define EDP_PSR2_STATUS_STATE_MASK REG_GENMASK(31, 28) |
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| 220 | #define EDP_PSR2_STATUS_STATE_DEEP_SLEEP REG_FIELD_PREP(EDP_PSR2_STATUS_STATE_MASK, 0x8) |
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| 221 | |
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| 222 | #define _PSR2_SU_STATUS_A 0x60914 |
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| 223 | #define _PSR2_SU_STATUS_EDP 0x6f914 |
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| 224 | #define _PSR2_SU_STATUS(tran, index) _MMIO_TRANS2(tran, _PSR2_SU_STATUS_A + (index) * 4) |
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| 225 | #define PSR2_SU_STATUS(tran, frame) (_PSR2_SU_STATUS(tran, (frame) / 3)) |
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| 226 | #define PSR2_SU_STATUS_SHIFT(frame) (((frame) % 3) * 10) |
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| 227 | #define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame)) |
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| 228 | #define PSR2_SU_STATUS_FRAMES 8 |
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| 229 | |
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| 230 | #define _PSR2_MAN_TRK_CTL_A 0x60910 |
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| 231 | #define _PSR2_MAN_TRK_CTL_EDP 0x6f910 |
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| 232 | #define PSR2_MAN_TRK_CTL(tran) _MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A) |
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| 233 | #define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31) |
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| 234 | #define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30, 21) |
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| 235 | #define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val) |
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| 236 | #define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(20, 11) |
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| 237 | #define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val) |
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| 238 | #define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3) |
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| 239 | #define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2) |
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| 240 | #define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1) |
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| 241 | #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(28, 16) |
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| 242 | #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val) |
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| 243 | #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(12, 0) |
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| 244 | #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val) |
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| 245 | #define ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(31) |
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| 246 | #define ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(14) |
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| 247 | #define ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(13) |
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| 248 | |
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| 249 | /* PSR2 Early transport */ |
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| 250 | #define _PIPE_SRCSZ_ERLY_TPT_A 0x70074 |
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| 251 | |
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| 252 | #define PIPE_SRCSZ_ERLY_TPT(trans) _MMIO_TRANS2(trans, _PIPE_SRCSZ_ERLY_TPT_A) |
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| 253 | |
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| 254 | #define _SEL_FETCH_PLANE_BASE_1_A 0x70890 |
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| 255 | #define _SEL_FETCH_PLANE_BASE_2_A 0x708B0 |
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| 256 | #define _SEL_FETCH_PLANE_BASE_3_A 0x708D0 |
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| 257 | #define _SEL_FETCH_PLANE_BASE_4_A 0x708F0 |
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| 258 | #define _SEL_FETCH_PLANE_BASE_5_A 0x70920 |
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| 259 | #define _SEL_FETCH_PLANE_BASE_6_A 0x70940 |
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| 260 | #define _SEL_FETCH_PLANE_BASE_7_A 0x70960 |
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| 261 | #define _SEL_FETCH_PLANE_BASE_CUR_A 0x70880 |
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| 262 | #define _SEL_FETCH_PLANE_BASE_1_B 0x71890 |
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| 263 | |
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| 264 | #define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \ |
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| 265 | _SEL_FETCH_PLANE_BASE_1_A, \ |
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| 266 | _SEL_FETCH_PLANE_BASE_2_A, \ |
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| 267 | _SEL_FETCH_PLANE_BASE_3_A, \ |
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| 268 | _SEL_FETCH_PLANE_BASE_4_A, \ |
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| 269 | _SEL_FETCH_PLANE_BASE_5_A, \ |
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| 270 | _SEL_FETCH_PLANE_BASE_6_A, \ |
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| 271 | _SEL_FETCH_PLANE_BASE_7_A, \ |
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| 272 | _SEL_FETCH_PLANE_BASE_CUR_A) |
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| 273 | #define _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe, _SEL_FETCH_PLANE_BASE_1_A, _SEL_FETCH_PLANE_BASE_1_B) |
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| 274 | #define _SEL_FETCH_PLANE_BASE(pipe, plane) (_SEL_FETCH_PLANE_BASE_1(pipe) - \ |
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| 275 | _SEL_FETCH_PLANE_BASE_1_A + \ |
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| 276 | _SEL_FETCH_PLANE_BASE_A(plane)) |
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| 277 | |
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| 278 | #define _SEL_FETCH_PLANE_CTL_1_A 0x70890 |
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| 279 | #define PLANE_SEL_FETCH_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ |
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| 280 | _SEL_FETCH_PLANE_CTL_1_A - \ |
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| 281 | _SEL_FETCH_PLANE_BASE_1_A) |
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| 282 | #define PLANE_SEL_FETCH_CTL_ENABLE REG_BIT(31) |
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| 283 | |
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| 284 | #define _SEL_FETCH_PLANE_POS_1_A 0x70894 |
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| 285 | #define PLANE_SEL_FETCH_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ |
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| 286 | _SEL_FETCH_PLANE_POS_1_A - \ |
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| 287 | _SEL_FETCH_PLANE_BASE_1_A) |
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| 288 | |
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| 289 | #define _SEL_FETCH_PLANE_SIZE_1_A 0x70898 |
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| 290 | #define PLANE_SEL_FETCH_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ |
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| 291 | _SEL_FETCH_PLANE_SIZE_1_A - \ |
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| 292 | _SEL_FETCH_PLANE_BASE_1_A) |
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| 293 | |
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| 294 | #define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089C |
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| 295 | #define PLANE_SEL_FETCH_OFFSET(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ |
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| 296 | _SEL_FETCH_PLANE_OFFSET_1_A - \ |
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| 297 | _SEL_FETCH_PLANE_BASE_1_A) |
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| 298 | |
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| 299 | #define _ALPM_CTL_A 0x60950 |
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| 300 | #define ALPM_CTL(tran) _MMIO_TRANS2(tran, _ALPM_CTL_A) |
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| 301 | #define ALPM_CTL_ALPM_ENABLE REG_BIT(31) |
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| 302 | #define ALPM_CTL_ALPM_AUX_LESS_ENABLE REG_BIT(30) |
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| 303 | #define ALPM_CTL_LOBF_ENABLE REG_BIT(29) |
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| 304 | #define ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE REG_BIT(28) |
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| 305 | #define ALPM_CTL_KEEP_FEC_ENABLE_FOR_AUX_WAKE_SLEEP REG_BIT(27) |
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| 306 | #define ALPM_CTL_RESTORE_OCCURED REG_BIT(26) |
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| 307 | #define ALPM_CTL_RESTORE_TO_SLEEP REG_BIT(25) |
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| 308 | #define ALPM_CTL_RESTORE_TO_DEEP_SLEEP REG_BIT(24) |
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| 309 | #define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_MASK REG_GENMASK(23, 21) |
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| 310 | #define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS REG_FIELD_PREP(ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_MASK, 0) |
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| 311 | #define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_128_SYMBOLS REG_FIELD_PREP(ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_MASK, 1) |
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| 312 | #define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_256_SYMBOLS REG_FIELD_PREP(ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_MASK, 2) |
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| 313 | #define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_512_SYMBOLS REG_FIELD_PREP(ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_MASK, 3) |
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| 314 | #define ALPM_CTL_AUX_WAKE_SLEEP_HOLD_ENABLE REG_BIT(20) |
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| 315 | #define ALPM_CTL_ALPM_ENTRY_CHECK_MASK REG_GENMASK(19, 16) |
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| 316 | #define ALPM_CTL_ALPM_ENTRY_CHECK(val) REG_FIELD_PREP(ALPM_CTL_ALPM_ENTRY_CHECK_MASK, val) |
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| 317 | #define ALPM_CTL_EXTENDED_FAST_WAKE_TIME_MASK REG_GENMASK(13, 8) |
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| 318 | #define ALPM_CTL_EXTENDED_FAST_WAKE_MIN_LINES 5 |
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| 319 | #define ALPM_CTL_EXTENDED_FAST_WAKE_TIME(lines) REG_FIELD_PREP(ALPM_CTL_EXTENDED_FAST_WAKE_TIME_MASK, (lines) - ALPM_CTL_EXTENDED_FAST_WAKE_MIN_LINES) |
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| 320 | #define ALPM_CTL_AUX_LESS_WAKE_TIME_MASK REG_GENMASK(5, 0) |
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| 321 | #define ALPM_CTL_AUX_LESS_WAKE_TIME(val) REG_FIELD_PREP(ALPM_CTL_AUX_LESS_WAKE_TIME_MASK, val) |
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| 322 | |
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| 323 | #define _ALPM_CTL2_A 0x60954 |
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| 324 | #define ALPM_CTL2(tran) _MMIO_TRANS2(tran, _ALPM_CTL2_A) |
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| 325 | #define ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK REG_GENMASK(28, 24) |
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| 326 | #define ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY(val) REG_FIELD_PREP(ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK, val) |
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| 327 | #define ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION_MASK REG_GENMASK(19, 16) |
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| 328 | #define ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION(val) REG_FIELD_PREP(ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION_MASK, val) |
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| 329 | #define ALPM_CTL2_NUMBER_OF_LTTPR_MASK REG_GENMASK(15, 12) |
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| 330 | #define ALPM_CTL2_NUMBER_OF_LTTPR(val) REG_FIELD_PREP(ALPM_CTL2_NUMBER_OF_LTTPR_MASK, val) |
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| 331 | #define ALPM_CTL2_LTTPR_AUX_LESS_SLEEP_HOLD_TIME_MASK REG_GENMASK(10, 8) |
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| 332 | #define ALPM_CTL2_LTTPR_AUX_LESS_SLEEP_HOLD_TIME(val) REG_FIELD_PREP(ALPM_CTL2_LTTPR_AUX_LESS_SLEEP_HOLD_TIME_MASK, val) |
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| 333 | #define ALPM_CTL2_FEC_DECODE_EN_POSITION_AFTER_WAKE_SR REG_BIT(4) |
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| 334 | #define ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES_MASK REG_GENMASK(2, 0) |
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| 335 | #define ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES(val) REG_FIELD_PREP(ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES_MASK, val) |
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| 336 | |
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| 337 | #define _PORT_ALPM_CTL_A 0x16fa2c |
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| 338 | #define PORT_ALPM_CTL(tran) _MMIO_TRANS2(tran, _PORT_ALPM_CTL_A) |
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| 339 | #define PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE REG_BIT(31) |
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| 340 | #define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK REG_GENMASK(23, 20) |
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| 341 | #define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(val) REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK, val) |
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| 342 | #define PORT_ALPM_CTL_MAX_PHY_SWING_HOLD_MASK REG_GENMASK(19, 16) |
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| 343 | #define PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(val) REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_HOLD_MASK, val) |
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| 344 | #define PORT_ALPM_CTL_SILENCE_PERIOD_MASK REG_GENMASK(7, 0) |
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| 345 | #define PORT_ALPM_CTL_SILENCE_PERIOD(val) REG_FIELD_PREP(PORT_ALPM_CTL_SILENCE_PERIOD_MASK, val) |
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| 346 | |
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| 347 | #define _PORT_ALPM_LFPS_CTL_A 0x16fa30 |
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| 348 | #define PORT_ALPM_LFPS_CTL(tran) _MMIO_TRANS2(tran, _PORT_ALPM_LFPS_CTL_A) |
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| 349 | #define PORT_ALPM_LFPS_CTL_LFPS_START_POLARITY REG_BIT(31) |
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| 350 | #define PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK REG_GENMASK(27, 24) |
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| 351 | #define ALPM_CTL_EXTENDED_FAST_WAKE_MIN_LINES 5 |
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| 352 | #define ALPM_CTL_EXTENDED_FAST_WAKE_TIME(lines) REG_FIELD_PREP(ALPM_CTL_EXTENDED_FAST_WAKE_TIME_MASK, (lines) - ALPM_CTL_EXTENDED_FAST_WAKE_MIN_LINES) |
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| 353 | #define ALPM_CTL_AUX_LESS_WAKE_TIME_MASK REG_GENMASK(5, 0) |
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| 354 | #define ALPM_CTL_AUX_LESS_WAKE_TIME(val) REG_FIELD_PREP(ALPM_CTL_AUX_LESS_WAKE_TIME_MASK, val) |
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| 355 | |
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| 356 | #endif /* __INTEL_PSR_REGS_H__ */ |
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| 357 | |
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