| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | /* |
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| 3 | * Copyright © 2022 Intel Corporation |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __INTEL_SNPS_PHY_REGS__ |
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| 7 | #define __INTEL_SNPS_PHY_REGS__ |
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| 8 | |
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| 9 | #include "intel_display_reg_defs.h" |
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| 10 | |
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| 11 | #define _SNPS_PHY_A_BASE 0x168000 |
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| 12 | #define _SNPS_PHY_B_BASE 0x169000 |
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| 13 | #define _SNPS_PHY(phy) _PHY(phy, \ |
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| 14 | _SNPS_PHY_A_BASE, \ |
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| 15 | _SNPS_PHY_B_BASE) |
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| 16 | #define _SNPS2(phy, reg) (_SNPS_PHY(phy) - \ |
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| 17 | _SNPS_PHY_A_BASE + (reg)) |
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| 18 | #define _MMIO_SNPS(phy, reg) _MMIO(_SNPS2(phy, reg)) |
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| 19 | #define _MMIO_SNPS_LN(ln, phy, reg) _MMIO(_SNPS2(phy, \ |
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| 20 | (reg) + (ln) * 0x10)) |
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| 21 | |
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| 22 | #define SNPS_PHY_MPLLB_CP(phy) _MMIO_SNPS(phy, 0x168000) |
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| 23 | #define SNPS_PHY_MPLLB_CP_INT REG_GENMASK(31, 25) |
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| 24 | #define SNPS_PHY_MPLLB_CP_INT_GS REG_GENMASK(23, 17) |
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| 25 | #define SNPS_PHY_MPLLB_CP_PROP REG_GENMASK(15, 9) |
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| 26 | #define SNPS_PHY_MPLLB_CP_PROP_GS REG_GENMASK(7, 1) |
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| 27 | |
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| 28 | #define SNPS_PHY_MPLLB_DIV(phy) _MMIO_SNPS(phy, 0x168004) |
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| 29 | #define SNPS_PHY_MPLLB_FORCE_EN REG_BIT(31) |
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| 30 | #define SNPS_PHY_MPLLB_DIV_CLK_EN REG_BIT(30) |
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| 31 | #define SNPS_PHY_MPLLB_DIV5_CLK_EN REG_BIT(29) |
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| 32 | #define SNPS_PHY_MPLLB_V2I REG_GENMASK(27, 26) |
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| 33 | #define SNPS_PHY_MPLLB_FREQ_VCO REG_GENMASK(25, 24) |
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| 34 | #define SNPS_PHY_MPLLB_DIV_MULTIPLIER REG_GENMASK(23, 16) |
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| 35 | #define SNPS_PHY_MPLLB_PMIX_EN REG_BIT(10) |
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| 36 | #define SNPS_PHY_MPLLB_DP2_MODE REG_BIT(9) |
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| 37 | #define SNPS_PHY_MPLLB_WORD_DIV2_EN REG_BIT(8) |
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| 38 | #define SNPS_PHY_MPLLB_TX_CLK_DIV REG_GENMASK(7, 5) |
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| 39 | #define SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL REG_BIT(0) |
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| 40 | |
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| 41 | #define SNPS_PHY_MPLLB_FRACN1(phy) _MMIO_SNPS(phy, 0x168008) |
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| 42 | #define SNPS_PHY_MPLLB_FRACN_EN REG_BIT(31) |
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| 43 | #define SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN REG_BIT(30) |
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| 44 | #define SNPS_PHY_MPLLB_FRACN_DEN REG_GENMASK(15, 0) |
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| 45 | |
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| 46 | #define SNPS_PHY_MPLLB_FRACN2(phy) _MMIO_SNPS(phy, 0x16800C) |
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| 47 | #define SNPS_PHY_MPLLB_FRACN_REM REG_GENMASK(31, 16) |
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| 48 | #define SNPS_PHY_MPLLB_FRACN_QUOT REG_GENMASK(15, 0) |
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| 49 | |
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| 50 | #define SNPS_PHY_MPLLB_SSCEN(phy) _MMIO_SNPS(phy, 0x168014) |
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| 51 | #define SNPS_PHY_MPLLB_SSC_EN REG_BIT(31) |
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| 52 | #define SNPS_PHY_MPLLB_SSC_UP_SPREAD REG_BIT(30) |
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| 53 | #define SNPS_PHY_MPLLB_SSC_PEAK REG_GENMASK(29, 10) |
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| 54 | |
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| 55 | #define SNPS_PHY_MPLLB_SSCSTEP(phy) _MMIO_SNPS(phy, 0x168018) |
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| 56 | #define SNPS_PHY_MPLLB_SSC_STEPSIZE REG_GENMASK(31, 11) |
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| 57 | |
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| 58 | #define SNPS_PHY_MPLLB_DIV2(phy) _MMIO_SNPS(phy, 0x16801C) |
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| 59 | #define SNPS_PHY_MPLLB_HDMI_PIXEL_CLK_DIV REG_GENMASK(19, 18) |
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| 60 | #define SNPS_PHY_MPLLB_HDMI_DIV REG_GENMASK(17, 15) |
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| 61 | #define SNPS_PHY_MPLLB_REF_CLK_DIV REG_GENMASK(14, 12) |
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| 62 | #define SNPS_PHY_MPLLB_MULTIPLIER REG_GENMASK(11, 0) |
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| 63 | |
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| 64 | #define SNPS_PHY_REF_CONTROL(phy) _MMIO_SNPS(phy, 0x168188) |
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| 65 | #define SNPS_PHY_REF_CONTROL_REF_RANGE REG_GENMASK(31, 27) |
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| 66 | |
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| 67 | #define SNPS_PHY_TX_REQ(phy) _MMIO_SNPS(phy, 0x168200) |
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| 68 | #define SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR REG_GENMASK(31, 30) |
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| 69 | |
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| 70 | #define SNPS_PHY_TX_EQ(ln, phy) _MMIO_SNPS_LN(ln, phy, 0x168300) |
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| 71 | #define SNPS_PHY_TX_EQ_MAIN REG_GENMASK(23, 18) |
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| 72 | #define SNPS_PHY_TX_EQ_POST REG_GENMASK(15, 10) |
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| 73 | #define SNPS_PHY_TX_EQ_PRE REG_GENMASK(7, 2) |
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| 74 | |
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| 75 | #endif /* __INTEL_SNPS_PHY_REGS__ */ |
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| 76 | |
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