1 | // SPDX-License-Identifier: MIT |
2 | /* |
3 | * Copyright © 2019 Intel Corporation |
4 | */ |
5 | |
6 | #include <linux/util_macros.h> |
7 | |
8 | #include "i915_reg.h" |
9 | #include "intel_ddi.h" |
10 | #include "intel_ddi_buf_trans.h" |
11 | #include "intel_de.h" |
12 | #include "intel_display_types.h" |
13 | #include "intel_snps_phy.h" |
14 | #include "intel_snps_phy_regs.h" |
15 | |
16 | /** |
17 | * DOC: Synopsis PHY support |
18 | * |
19 | * Synopsis PHYs are primarily programmed by looking up magic register values |
20 | * in tables rather than calculating the necessary values at runtime. |
21 | * |
22 | * Of special note is that the SNPS PHYs include a dedicated port PLL, known as |
23 | * an "MPLLB." The MPLLB replaces the shared DPLL functionality used on other |
24 | * platforms and must be programming directly during the modeset sequence |
25 | * since it is not handled by the shared DPLL framework as on other platforms. |
26 | */ |
27 | |
28 | void intel_snps_phy_wait_for_calibration(struct drm_i915_private *i915) |
29 | { |
30 | enum phy phy; |
31 | |
32 | for_each_phy_masked(phy, ~0) { |
33 | if (!intel_phy_is_snps(dev_priv: i915, phy)) |
34 | continue; |
35 | |
36 | /* |
37 | * If calibration does not complete successfully, we'll remember |
38 | * which phy was affected and skip setup of the corresponding |
39 | * output later. |
40 | */ |
41 | if (intel_de_wait_for_clear(i915, DG2_PHY_MISC(phy), |
42 | DG2_PHY_DP_TX_ACK_MASK, timeout: 25)) |
43 | i915->display.snps.phy_failed_calibration |= BIT(phy); |
44 | } |
45 | } |
46 | |
47 | void intel_snps_phy_update_psr_power_state(struct drm_i915_private *i915, |
48 | enum phy phy, bool enable) |
49 | { |
50 | u32 val; |
51 | |
52 | if (!intel_phy_is_snps(dev_priv: i915, phy)) |
53 | return; |
54 | |
55 | val = REG_FIELD_PREP(SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR, |
56 | enable ? 2 : 3); |
57 | intel_de_rmw(i915, SNPS_PHY_TX_REQ(phy), |
58 | SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR, set: val); |
59 | } |
60 | |
61 | void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder, |
62 | const struct intel_crtc_state *crtc_state) |
63 | { |
64 | struct drm_i915_private *dev_priv = to_i915(dev: encoder->base.dev); |
65 | const struct intel_ddi_buf_trans *trans; |
66 | enum phy phy = intel_port_to_phy(i915: dev_priv, port: encoder->port); |
67 | int n_entries, ln; |
68 | |
69 | trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); |
70 | if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) |
71 | return; |
72 | |
73 | for (ln = 0; ln < 4; ln++) { |
74 | int level = intel_ddi_level(encoder, crtc_state, lane: ln); |
75 | u32 val = 0; |
76 | |
77 | val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, trans->entries[level].snps.vswing); |
78 | val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_PRE, trans->entries[level].snps.pre_cursor); |
79 | val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, trans->entries[level].snps.post_cursor); |
80 | |
81 | intel_de_write(i915: dev_priv, SNPS_PHY_TX_EQ(ln, phy), val); |
82 | } |
83 | } |
84 | |
85 | /* |
86 | * Basic DP link rates with 100 MHz reference clock. |
87 | */ |
88 | |
89 | static const struct intel_mpllb_state dg2_dp_rbr_100 = { |
90 | .clock = 162000, |
91 | .ref_control = |
92 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
93 | .mpllb_cp = |
94 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | |
95 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) | |
96 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | |
97 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), |
98 | .mpllb_div = |
99 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
100 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | |
101 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
102 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
103 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2), |
104 | .mpllb_div2 = |
105 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | |
106 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 226), |
107 | .mpllb_fracn1 = |
108 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
109 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
110 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), |
111 | .mpllb_fracn2 = |
112 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) | |
113 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 3), |
114 | }; |
115 | |
116 | static const struct intel_mpllb_state dg2_dp_hbr1_100 = { |
117 | .clock = 270000, |
118 | .ref_control = |
119 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
120 | .mpllb_cp = |
121 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | |
122 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) | |
123 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | |
124 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), |
125 | .mpllb_div = |
126 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
127 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | |
128 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
129 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), |
130 | .mpllb_div2 = |
131 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | |
132 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 184), |
133 | .mpllb_fracn1 = |
134 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
135 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), |
136 | }; |
137 | |
138 | static const struct intel_mpllb_state dg2_dp_hbr2_100 = { |
139 | .clock = 540000, |
140 | .ref_control = |
141 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
142 | .mpllb_cp = |
143 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | |
144 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) | |
145 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | |
146 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), |
147 | .mpllb_div = |
148 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
149 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
150 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), |
151 | .mpllb_div2 = |
152 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | |
153 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 184), |
154 | .mpllb_fracn1 = |
155 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
156 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), |
157 | }; |
158 | |
159 | static const struct intel_mpllb_state dg2_dp_hbr3_100 = { |
160 | .clock = 810000, |
161 | .ref_control = |
162 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
163 | .mpllb_cp = |
164 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | |
165 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) | |
166 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | |
167 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), |
168 | .mpllb_div = |
169 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
170 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), |
171 | .mpllb_div2 = |
172 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | |
173 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 292), |
174 | .mpllb_fracn1 = |
175 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
176 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), |
177 | }; |
178 | |
179 | static const struct intel_mpllb_state dg2_dp_uhbr10_100 = { |
180 | .clock = 1000000, |
181 | .ref_control = |
182 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
183 | .mpllb_cp = |
184 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | |
185 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 21) | |
186 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | |
187 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), |
188 | .mpllb_div = |
189 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
190 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) | |
191 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) | |
192 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
193 | REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) | |
194 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) | |
195 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL, 1) | |
196 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), |
197 | .mpllb_div2 = |
198 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | |
199 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 368), |
200 | .mpllb_fracn1 = |
201 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
202 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), |
203 | |
204 | /* |
205 | * SSC will be enabled, DP UHBR has a minimum SSC requirement. |
206 | */ |
207 | .mpllb_sscen = |
208 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | |
209 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 58982), |
210 | .mpllb_sscstep = |
211 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 76101), |
212 | }; |
213 | |
214 | static const struct intel_mpllb_state dg2_dp_uhbr13_100 = { |
215 | .clock = 1350000, |
216 | .ref_control = |
217 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
218 | .mpllb_cp = |
219 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) | |
220 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 45) | |
221 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | |
222 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), |
223 | .mpllb_div = |
224 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
225 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) | |
226 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) | |
227 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
228 | REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) | |
229 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) | |
230 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 3), |
231 | .mpllb_div2 = |
232 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | |
233 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 508), |
234 | .mpllb_fracn1 = |
235 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
236 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), |
237 | |
238 | /* |
239 | * SSC will be enabled, DP UHBR has a minimum SSC requirement. |
240 | */ |
241 | .mpllb_sscen = |
242 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | |
243 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 79626), |
244 | .mpllb_sscstep = |
245 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 102737), |
246 | }; |
247 | |
248 | static const struct intel_mpllb_state * const dg2_dp_100_tables[] = { |
249 | &dg2_dp_rbr_100, |
250 | &dg2_dp_hbr1_100, |
251 | &dg2_dp_hbr2_100, |
252 | &dg2_dp_hbr3_100, |
253 | &dg2_dp_uhbr10_100, |
254 | &dg2_dp_uhbr13_100, |
255 | NULL, |
256 | }; |
257 | |
258 | /* |
259 | * eDP link rates with 100 MHz reference clock. |
260 | */ |
261 | |
262 | static const struct intel_mpllb_state dg2_edp_r216 = { |
263 | .clock = 216000, |
264 | .ref_control = |
265 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
266 | .mpllb_cp = |
267 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | |
268 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) | |
269 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | |
270 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), |
271 | .mpllb_div = |
272 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
273 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | |
274 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
275 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), |
276 | .mpllb_div2 = |
277 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | |
278 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 312), |
279 | .mpllb_fracn1 = |
280 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
281 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
282 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), |
283 | .mpllb_fracn2 = |
284 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) | |
285 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 4), |
286 | .mpllb_sscen = |
287 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | |
288 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 50961), |
289 | .mpllb_sscstep = |
290 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 65752), |
291 | }; |
292 | |
293 | static const struct intel_mpllb_state dg2_edp_r243 = { |
294 | .clock = 243000, |
295 | .ref_control = |
296 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
297 | .mpllb_cp = |
298 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | |
299 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) | |
300 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | |
301 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), |
302 | .mpllb_div = |
303 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
304 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | |
305 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
306 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), |
307 | .mpllb_div2 = |
308 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | |
309 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 356), |
310 | .mpllb_fracn1 = |
311 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
312 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
313 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), |
314 | .mpllb_fracn2 = |
315 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | |
316 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2), |
317 | .mpllb_sscen = |
318 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | |
319 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 57331), |
320 | .mpllb_sscstep = |
321 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 73971), |
322 | }; |
323 | |
324 | static const struct intel_mpllb_state dg2_edp_r324 = { |
325 | .clock = 324000, |
326 | .ref_control = |
327 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
328 | .mpllb_cp = |
329 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | |
330 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) | |
331 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | |
332 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), |
333 | .mpllb_div = |
334 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
335 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | |
336 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
337 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
338 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2), |
339 | .mpllb_div2 = |
340 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | |
341 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 226), |
342 | .mpllb_fracn1 = |
343 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
344 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
345 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), |
346 | .mpllb_fracn2 = |
347 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) | |
348 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 3), |
349 | .mpllb_sscen = |
350 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | |
351 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 38221), |
352 | .mpllb_sscstep = |
353 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 49314), |
354 | }; |
355 | |
356 | static const struct intel_mpllb_state dg2_edp_r432 = { |
357 | .clock = 432000, |
358 | .ref_control = |
359 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
360 | .mpllb_cp = |
361 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | |
362 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) | |
363 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | |
364 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), |
365 | .mpllb_div = |
366 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
367 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | |
368 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
369 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), |
370 | .mpllb_div2 = |
371 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | |
372 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 312), |
373 | .mpllb_fracn1 = |
374 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
375 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
376 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), |
377 | .mpllb_fracn2 = |
378 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) | |
379 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 4), |
380 | .mpllb_sscen = |
381 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | |
382 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 50961), |
383 | .mpllb_sscstep = |
384 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 65752), |
385 | }; |
386 | |
387 | static const struct intel_mpllb_state * const dg2_edp_tables[] = { |
388 | &dg2_dp_rbr_100, |
389 | &dg2_edp_r216, |
390 | &dg2_edp_r243, |
391 | &dg2_dp_hbr1_100, |
392 | &dg2_edp_r324, |
393 | &dg2_edp_r432, |
394 | &dg2_dp_hbr2_100, |
395 | &dg2_dp_hbr3_100, |
396 | NULL, |
397 | }; |
398 | |
399 | /* |
400 | * HDMI link rates with 100 MHz reference clock. |
401 | */ |
402 | |
403 | static const struct intel_mpllb_state dg2_hdmi_25_175 = { |
404 | .clock = 25175, |
405 | .ref_control = |
406 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
407 | .mpllb_cp = |
408 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) | |
409 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | |
410 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
411 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
412 | .mpllb_div = |
413 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
414 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) | |
415 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
416 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), |
417 | .mpllb_div2 = |
418 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
419 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 128) | |
420 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
421 | .mpllb_fracn1 = |
422 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
423 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
424 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 143), |
425 | .mpllb_fracn2 = |
426 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36663) | |
427 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 71), |
428 | .mpllb_sscen = |
429 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
430 | }; |
431 | |
432 | static const struct intel_mpllb_state dg2_hdmi_27_0 = { |
433 | .clock = 27000, |
434 | .ref_control = |
435 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
436 | .mpllb_cp = |
437 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) | |
438 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | |
439 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
440 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
441 | .mpllb_div = |
442 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
443 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) | |
444 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
445 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), |
446 | .mpllb_div2 = |
447 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
448 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 140) | |
449 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
450 | .mpllb_fracn1 = |
451 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
452 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
453 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), |
454 | .mpllb_fracn2 = |
455 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | |
456 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2), |
457 | .mpllb_sscen = |
458 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
459 | }; |
460 | |
461 | static const struct intel_mpllb_state dg2_hdmi_74_25 = { |
462 | .clock = 74250, |
463 | .ref_control = |
464 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
465 | .mpllb_cp = |
466 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | |
467 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | |
468 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
469 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
470 | .mpllb_div = |
471 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
472 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | |
473 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
474 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
475 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), |
476 | .mpllb_div2 = |
477 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
478 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | |
479 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
480 | .mpllb_fracn1 = |
481 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
482 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
483 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), |
484 | .mpllb_fracn2 = |
485 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | |
486 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2), |
487 | .mpllb_sscen = |
488 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
489 | }; |
490 | |
491 | static const struct intel_mpllb_state dg2_hdmi_148_5 = { |
492 | .clock = 148500, |
493 | .ref_control = |
494 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
495 | .mpllb_cp = |
496 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | |
497 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | |
498 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
499 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
500 | .mpllb_div = |
501 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
502 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | |
503 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
504 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
505 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), |
506 | .mpllb_div2 = |
507 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
508 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | |
509 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
510 | .mpllb_fracn1 = |
511 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
512 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
513 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), |
514 | .mpllb_fracn2 = |
515 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | |
516 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2), |
517 | .mpllb_sscen = |
518 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
519 | }; |
520 | |
521 | /* values in the below table are calculted using the algo */ |
522 | static const struct intel_mpllb_state dg2_hdmi_25200 = { |
523 | .clock = 25200, |
524 | .ref_control = |
525 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
526 | .mpllb_cp = |
527 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) | |
528 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | |
529 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
530 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
531 | .mpllb_div = |
532 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
533 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) | |
534 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
535 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
536 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), |
537 | .mpllb_div2 = |
538 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
539 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 128) | |
540 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
541 | .mpllb_fracn1 = |
542 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
543 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
544 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), |
545 | .mpllb_fracn2 = |
546 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 41943) | |
547 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2621), |
548 | .mpllb_sscen = |
549 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
550 | }; |
551 | |
552 | static const struct intel_mpllb_state dg2_hdmi_27027 = { |
553 | .clock = 27027, |
554 | .ref_control = |
555 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
556 | .mpllb_cp = |
557 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | |
558 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | |
559 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
560 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
561 | .mpllb_div = |
562 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
563 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) | |
564 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
565 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
566 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), |
567 | .mpllb_div2 = |
568 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
569 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 140) | |
570 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
571 | .mpllb_fracn1 = |
572 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
573 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
574 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), |
575 | .mpllb_fracn2 = |
576 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 31876) | |
577 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 46555), |
578 | .mpllb_sscen = |
579 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
580 | }; |
581 | |
582 | static const struct intel_mpllb_state dg2_hdmi_28320 = { |
583 | .clock = 28320, |
584 | .ref_control = |
585 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
586 | .mpllb_cp = |
587 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | |
588 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | |
589 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
590 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
591 | .mpllb_div = |
592 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
593 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) | |
594 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
595 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
596 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), |
597 | .mpllb_div2 = |
598 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
599 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 148) | |
600 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
601 | .mpllb_fracn1 = |
602 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
603 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
604 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), |
605 | .mpllb_fracn2 = |
606 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 40894) | |
607 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 30408), |
608 | .mpllb_sscen = |
609 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
610 | }; |
611 | |
612 | static const struct intel_mpllb_state dg2_hdmi_30240 = { |
613 | .clock = 30240, |
614 | .ref_control = |
615 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
616 | .mpllb_cp = |
617 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | |
618 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | |
619 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
620 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
621 | .mpllb_div = |
622 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
623 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) | |
624 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
625 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
626 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), |
627 | .mpllb_div2 = |
628 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
629 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 160) | |
630 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
631 | .mpllb_fracn1 = |
632 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
633 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
634 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), |
635 | .mpllb_fracn2 = |
636 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 50331) | |
637 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 42466), |
638 | .mpllb_sscen = |
639 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
640 | }; |
641 | |
642 | static const struct intel_mpllb_state dg2_hdmi_31500 = { |
643 | .clock = 31500, |
644 | .ref_control = |
645 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
646 | .mpllb_cp = |
647 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) | |
648 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | |
649 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
650 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
651 | .mpllb_div = |
652 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
653 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) | |
654 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
655 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
656 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), |
657 | .mpllb_div2 = |
658 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
659 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 68) | |
660 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
661 | .mpllb_fracn1 = |
662 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
663 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
664 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), |
665 | .mpllb_fracn2 = |
666 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | |
667 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214), |
668 | .mpllb_sscen = |
669 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
670 | }; |
671 | |
672 | static const struct intel_mpllb_state dg2_hdmi_36000 = { |
673 | .clock = 36000, |
674 | .ref_control = |
675 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
676 | .mpllb_cp = |
677 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | |
678 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | |
679 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
680 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
681 | .mpllb_div = |
682 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
683 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) | |
684 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
685 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
686 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), |
687 | .mpllb_div2 = |
688 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
689 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 82) | |
690 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
691 | .mpllb_fracn1 = |
692 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
693 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
694 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), |
695 | .mpllb_fracn2 = |
696 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) | |
697 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 39320), |
698 | .mpllb_sscen = |
699 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
700 | }; |
701 | |
702 | static const struct intel_mpllb_state dg2_hdmi_40000 = { |
703 | .clock = 40000, |
704 | .ref_control = |
705 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
706 | .mpllb_cp = |
707 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | |
708 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | |
709 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
710 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
711 | .mpllb_div = |
712 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
713 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) | |
714 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) | |
715 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
716 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2), |
717 | .mpllb_div2 = |
718 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
719 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 96) | |
720 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
721 | .mpllb_fracn1 = |
722 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
723 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) | |
724 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), |
725 | .mpllb_fracn2 = |
726 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) | |
727 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0), |
728 | .mpllb_sscen = |
729 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
730 | }; |
731 | |
732 | static const struct intel_mpllb_state dg2_hdmi_49500 = { |
733 | .clock = 49500, |
734 | .ref_control = |
735 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
736 | .mpllb_cp = |
737 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | |
738 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | |
739 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
740 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
741 | .mpllb_div = |
742 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
743 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) | |
744 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
745 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
746 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 1), |
747 | .mpllb_div2 = |
748 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
749 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 126) | |
750 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
751 | .mpllb_fracn1 = |
752 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
753 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
754 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), |
755 | .mpllb_fracn2 = |
756 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 13107) | |
757 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107), |
758 | .mpllb_sscen = |
759 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
760 | }; |
761 | |
762 | static const struct intel_mpllb_state dg2_hdmi_50000 = { |
763 | .clock = 50000, |
764 | .ref_control = |
765 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
766 | .mpllb_cp = |
767 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | |
768 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | |
769 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
770 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
771 | .mpllb_div = |
772 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
773 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) | |
774 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) | |
775 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
776 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 1), |
777 | .mpllb_div2 = |
778 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
779 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 128) | |
780 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
781 | .mpllb_fracn1 = |
782 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
783 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) | |
784 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), |
785 | .mpllb_fracn2 = |
786 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) | |
787 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0), |
788 | .mpllb_sscen = |
789 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
790 | }; |
791 | |
792 | static const struct intel_mpllb_state dg2_hdmi_57284 = { |
793 | .clock = 57284, |
794 | .ref_control = |
795 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
796 | .mpllb_cp = |
797 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | |
798 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | |
799 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
800 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
801 | .mpllb_div = |
802 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
803 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) | |
804 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
805 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
806 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), |
807 | .mpllb_div2 = |
808 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
809 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 150) | |
810 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
811 | .mpllb_fracn1 = |
812 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
813 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
814 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), |
815 | .mpllb_fracn2 = |
816 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 42886) | |
817 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 49701), |
818 | .mpllb_sscen = |
819 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
820 | }; |
821 | |
822 | static const struct intel_mpllb_state dg2_hdmi_58000 = { |
823 | .clock = 58000, |
824 | .ref_control = |
825 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
826 | .mpllb_cp = |
827 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | |
828 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | |
829 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
830 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
831 | .mpllb_div = |
832 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
833 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) | |
834 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
835 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
836 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), |
837 | .mpllb_div2 = |
838 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
839 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 152) | |
840 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
841 | .mpllb_fracn1 = |
842 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
843 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
844 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), |
845 | .mpllb_fracn2 = |
846 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) | |
847 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427), |
848 | .mpllb_sscen = |
849 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
850 | }; |
851 | |
852 | static const struct intel_mpllb_state dg2_hdmi_65000 = { |
853 | .clock = 65000, |
854 | .ref_control = |
855 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
856 | .mpllb_cp = |
857 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) | |
858 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | |
859 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
860 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
861 | .mpllb_div = |
862 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
863 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | |
864 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) | |
865 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
866 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), |
867 | .mpllb_div2 = |
868 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
869 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 72) | |
870 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
871 | .mpllb_fracn1 = |
872 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
873 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) | |
874 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), |
875 | .mpllb_fracn2 = |
876 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) | |
877 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0), |
878 | .mpllb_sscen = |
879 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
880 | }; |
881 | |
882 | static const struct intel_mpllb_state dg2_hdmi_71000 = { |
883 | .clock = 71000, |
884 | .ref_control = |
885 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
886 | .mpllb_cp = |
887 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | |
888 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | |
889 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
890 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
891 | .mpllb_div = |
892 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
893 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | |
894 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
895 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
896 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), |
897 | .mpllb_div2 = |
898 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
899 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 80) | |
900 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
901 | .mpllb_fracn1 = |
902 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
903 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
904 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), |
905 | .mpllb_fracn2 = |
906 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) | |
907 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427), |
908 | .mpllb_sscen = |
909 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
910 | }; |
911 | |
912 | static const struct intel_mpllb_state dg2_hdmi_74176 = { |
913 | .clock = 74176, |
914 | .ref_control = |
915 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
916 | .mpllb_cp = |
917 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | |
918 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | |
919 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
920 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
921 | .mpllb_div = |
922 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
923 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | |
924 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
925 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
926 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), |
927 | .mpllb_div2 = |
928 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
929 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | |
930 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
931 | .mpllb_fracn1 = |
932 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
933 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
934 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), |
935 | .mpllb_fracn2 = |
936 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 22334) | |
937 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 43829), |
938 | .mpllb_sscen = |
939 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
940 | }; |
941 | |
942 | static const struct intel_mpllb_state dg2_hdmi_75000 = { |
943 | .clock = 75000, |
944 | .ref_control = |
945 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
946 | .mpllb_cp = |
947 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | |
948 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | |
949 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
950 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
951 | .mpllb_div = |
952 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
953 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | |
954 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) | |
955 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
956 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), |
957 | .mpllb_div2 = |
958 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
959 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 88) | |
960 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
961 | .mpllb_fracn1 = |
962 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
963 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) | |
964 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), |
965 | .mpllb_fracn2 = |
966 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) | |
967 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0), |
968 | .mpllb_sscen = |
969 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
970 | }; |
971 | |
972 | static const struct intel_mpllb_state dg2_hdmi_78750 = { |
973 | .clock = 78750, |
974 | .ref_control = |
975 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
976 | .mpllb_cp = |
977 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | |
978 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | |
979 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
980 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
981 | .mpllb_div = |
982 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
983 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | |
984 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) | |
985 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
986 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2), |
987 | .mpllb_div2 = |
988 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
989 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 94) | |
990 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
991 | .mpllb_fracn1 = |
992 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
993 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) | |
994 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), |
995 | .mpllb_fracn2 = |
996 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) | |
997 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0), |
998 | .mpllb_sscen = |
999 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
1000 | }; |
1001 | |
1002 | static const struct intel_mpllb_state dg2_hdmi_85500 = { |
1003 | .clock = 85500, |
1004 | .ref_control = |
1005 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
1006 | .mpllb_cp = |
1007 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | |
1008 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | |
1009 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
1010 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
1011 | .mpllb_div = |
1012 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
1013 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | |
1014 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
1015 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
1016 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2), |
1017 | .mpllb_div2 = |
1018 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
1019 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 104) | |
1020 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
1021 | .mpllb_fracn1 = |
1022 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
1023 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
1024 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), |
1025 | .mpllb_fracn2 = |
1026 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | |
1027 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214), |
1028 | .mpllb_sscen = |
1029 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
1030 | }; |
1031 | |
1032 | static const struct intel_mpllb_state dg2_hdmi_88750 = { |
1033 | .clock = 88750, |
1034 | .ref_control = |
1035 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
1036 | .mpllb_cp = |
1037 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) | |
1038 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | |
1039 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
1040 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
1041 | .mpllb_div = |
1042 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
1043 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | |
1044 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) | |
1045 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
1046 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 1), |
1047 | .mpllb_div2 = |
1048 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
1049 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 110) | |
1050 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
1051 | .mpllb_fracn1 = |
1052 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
1053 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) | |
1054 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), |
1055 | .mpllb_fracn2 = |
1056 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) | |
1057 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0), |
1058 | .mpllb_sscen = |
1059 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
1060 | }; |
1061 | |
1062 | static const struct intel_mpllb_state dg2_hdmi_106500 = { |
1063 | .clock = 106500, |
1064 | .ref_control = |
1065 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
1066 | .mpllb_cp = |
1067 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | |
1068 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | |
1069 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
1070 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
1071 | .mpllb_div = |
1072 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
1073 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | |
1074 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
1075 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
1076 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), |
1077 | .mpllb_div2 = |
1078 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
1079 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 138) | |
1080 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
1081 | .mpllb_fracn1 = |
1082 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
1083 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
1084 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), |
1085 | .mpllb_fracn2 = |
1086 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 13107) | |
1087 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107), |
1088 | .mpllb_sscen = |
1089 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
1090 | }; |
1091 | |
1092 | static const struct intel_mpllb_state dg2_hdmi_108000 = { |
1093 | .clock = 108000, |
1094 | .ref_control = |
1095 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
1096 | .mpllb_cp = |
1097 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | |
1098 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | |
1099 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
1100 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
1101 | .mpllb_div = |
1102 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
1103 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | |
1104 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
1105 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
1106 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), |
1107 | .mpllb_div2 = |
1108 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
1109 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 140) | |
1110 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
1111 | .mpllb_fracn1 = |
1112 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
1113 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
1114 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), |
1115 | .mpllb_fracn2 = |
1116 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | |
1117 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214), |
1118 | .mpllb_sscen = |
1119 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
1120 | }; |
1121 | |
1122 | static const struct intel_mpllb_state dg2_hdmi_115500 = { |
1123 | .clock = 115500, |
1124 | .ref_control = |
1125 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
1126 | .mpllb_cp = |
1127 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | |
1128 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | |
1129 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
1130 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
1131 | .mpllb_div = |
1132 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
1133 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | |
1134 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
1135 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
1136 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), |
1137 | .mpllb_div2 = |
1138 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
1139 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 152) | |
1140 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
1141 | .mpllb_fracn1 = |
1142 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
1143 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
1144 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), |
1145 | .mpllb_fracn2 = |
1146 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | |
1147 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214), |
1148 | .mpllb_sscen = |
1149 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
1150 | }; |
1151 | |
1152 | static const struct intel_mpllb_state dg2_hdmi_119000 = { |
1153 | .clock = 119000, |
1154 | .ref_control = |
1155 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
1156 | .mpllb_cp = |
1157 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | |
1158 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | |
1159 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
1160 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
1161 | .mpllb_div = |
1162 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
1163 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | |
1164 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
1165 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
1166 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), |
1167 | .mpllb_div2 = |
1168 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
1169 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 158) | |
1170 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
1171 | .mpllb_fracn1 = |
1172 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
1173 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
1174 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), |
1175 | .mpllb_fracn2 = |
1176 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 13107) | |
1177 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107), |
1178 | .mpllb_sscen = |
1179 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
1180 | }; |
1181 | |
1182 | static const struct intel_mpllb_state dg2_hdmi_135000 = { |
1183 | .clock = 135000, |
1184 | .ref_control = |
1185 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
1186 | .mpllb_cp = |
1187 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) | |
1188 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | |
1189 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
1190 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
1191 | .mpllb_div = |
1192 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
1193 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | |
1194 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) | |
1195 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
1196 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), |
1197 | .mpllb_div2 = |
1198 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
1199 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 76) | |
1200 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
1201 | .mpllb_fracn1 = |
1202 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
1203 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) | |
1204 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), |
1205 | .mpllb_fracn2 = |
1206 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) | |
1207 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0), |
1208 | .mpllb_sscen = |
1209 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
1210 | }; |
1211 | |
1212 | static const struct intel_mpllb_state dg2_hdmi_138500 = { |
1213 | .clock = 138500, |
1214 | .ref_control = |
1215 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
1216 | .mpllb_cp = |
1217 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | |
1218 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | |
1219 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
1220 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
1221 | .mpllb_div = |
1222 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
1223 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | |
1224 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
1225 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
1226 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), |
1227 | .mpllb_div2 = |
1228 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
1229 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 78) | |
1230 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
1231 | .mpllb_fracn1 = |
1232 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
1233 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
1234 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), |
1235 | .mpllb_fracn2 = |
1236 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | |
1237 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214), |
1238 | .mpllb_sscen = |
1239 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
1240 | }; |
1241 | |
1242 | static const struct intel_mpllb_state dg2_hdmi_147160 = { |
1243 | .clock = 147160, |
1244 | .ref_control = |
1245 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
1246 | .mpllb_cp = |
1247 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | |
1248 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | |
1249 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
1250 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
1251 | .mpllb_div = |
1252 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
1253 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | |
1254 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
1255 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
1256 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), |
1257 | .mpllb_div2 = |
1258 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
1259 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 84) | |
1260 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
1261 | .mpllb_fracn1 = |
1262 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
1263 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
1264 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), |
1265 | .mpllb_fracn2 = |
1266 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 56623) | |
1267 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 6815), |
1268 | .mpllb_sscen = |
1269 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
1270 | }; |
1271 | |
1272 | static const struct intel_mpllb_state dg2_hdmi_148352 = { |
1273 | .clock = 148352, |
1274 | .ref_control = |
1275 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
1276 | .mpllb_cp = |
1277 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | |
1278 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | |
1279 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
1280 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
1281 | .mpllb_div = |
1282 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
1283 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | |
1284 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
1285 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
1286 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), |
1287 | .mpllb_div2 = |
1288 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
1289 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | |
1290 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
1291 | .mpllb_fracn1 = |
1292 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
1293 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
1294 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), |
1295 | .mpllb_fracn2 = |
1296 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 22334) | |
1297 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 43829), |
1298 | .mpllb_sscen = |
1299 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
1300 | }; |
1301 | |
1302 | static const struct intel_mpllb_state dg2_hdmi_154000 = { |
1303 | .clock = 154000, |
1304 | .ref_control = |
1305 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
1306 | .mpllb_cp = |
1307 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | |
1308 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 13) | |
1309 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
1310 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
1311 | .mpllb_div = |
1312 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
1313 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | |
1314 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
1315 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
1316 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2), |
1317 | .mpllb_div2 = |
1318 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
1319 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 90) | |
1320 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
1321 | .mpllb_fracn1 = |
1322 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
1323 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
1324 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), |
1325 | .mpllb_fracn2 = |
1326 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) | |
1327 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 39320), |
1328 | .mpllb_sscen = |
1329 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
1330 | }; |
1331 | |
1332 | static const struct intel_mpllb_state dg2_hdmi_162000 = { |
1333 | .clock = 162000, |
1334 | .ref_control = |
1335 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
1336 | .mpllb_cp = |
1337 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | |
1338 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | |
1339 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
1340 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
1341 | .mpllb_div = |
1342 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
1343 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | |
1344 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
1345 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
1346 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2), |
1347 | .mpllb_div2 = |
1348 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
1349 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 96) | |
1350 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
1351 | .mpllb_fracn1 = |
1352 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
1353 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
1354 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), |
1355 | .mpllb_fracn2 = |
1356 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) | |
1357 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427), |
1358 | .mpllb_sscen = |
1359 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
1360 | }; |
1361 | |
1362 | static const struct intel_mpllb_state dg2_hdmi_209800 = { |
1363 | .clock = 209800, |
1364 | .ref_control = |
1365 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
1366 | .mpllb_cp = |
1367 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) | |
1368 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | |
1369 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
1370 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
1371 | .mpllb_div = |
1372 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
1373 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | |
1374 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
1375 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
1376 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), |
1377 | .mpllb_div2 = |
1378 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
1379 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 134) | |
1380 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
1381 | .mpllb_fracn1 = |
1382 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
1383 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
1384 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), |
1385 | .mpllb_fracn2 = |
1386 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 60293) | |
1387 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 7864), |
1388 | .mpllb_sscen = |
1389 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
1390 | }; |
1391 | |
1392 | static const struct intel_mpllb_state dg2_hdmi_262750 = { |
1393 | .clock = 262750, |
1394 | .ref_control = |
1395 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
1396 | .mpllb_cp = |
1397 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) | |
1398 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | |
1399 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
1400 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
1401 | .mpllb_div = |
1402 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
1403 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | |
1404 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
1405 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
1406 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), |
1407 | .mpllb_div2 = |
1408 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
1409 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 72) | |
1410 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
1411 | .mpllb_fracn1 = |
1412 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
1413 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
1414 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), |
1415 | .mpllb_fracn2 = |
1416 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36044) | |
1417 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427), |
1418 | .mpllb_sscen = |
1419 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
1420 | }; |
1421 | |
1422 | static const struct intel_mpllb_state dg2_hdmi_267300 = { |
1423 | .clock = 267300, |
1424 | .ref_control = |
1425 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
1426 | .mpllb_cp = |
1427 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) | |
1428 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | |
1429 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
1430 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
1431 | .mpllb_div = |
1432 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
1433 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | |
1434 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
1435 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
1436 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), |
1437 | .mpllb_div2 = |
1438 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
1439 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 74) | |
1440 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
1441 | .mpllb_fracn1 = |
1442 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
1443 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
1444 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), |
1445 | .mpllb_fracn2 = |
1446 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 30146) | |
1447 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 36699), |
1448 | .mpllb_sscen = |
1449 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
1450 | }; |
1451 | |
1452 | static const struct intel_mpllb_state dg2_hdmi_268500 = { |
1453 | .clock = 268500, |
1454 | .ref_control = |
1455 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
1456 | .mpllb_cp = |
1457 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) | |
1458 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | |
1459 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
1460 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
1461 | .mpllb_div = |
1462 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
1463 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | |
1464 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
1465 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
1466 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), |
1467 | .mpllb_div2 = |
1468 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
1469 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 74) | |
1470 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
1471 | .mpllb_fracn1 = |
1472 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
1473 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
1474 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), |
1475 | .mpllb_fracn2 = |
1476 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 45875) | |
1477 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107), |
1478 | .mpllb_sscen = |
1479 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
1480 | }; |
1481 | |
1482 | static const struct intel_mpllb_state dg2_hdmi_296703 = { |
1483 | .clock = 296703, |
1484 | .ref_control = |
1485 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
1486 | .mpllb_cp = |
1487 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | |
1488 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | |
1489 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
1490 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
1491 | .mpllb_div = |
1492 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
1493 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | |
1494 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
1495 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
1496 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), |
1497 | .mpllb_div2 = |
1498 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
1499 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | |
1500 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
1501 | .mpllb_fracn1 = |
1502 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
1503 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
1504 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), |
1505 | .mpllb_fracn2 = |
1506 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 22321) | |
1507 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 36804), |
1508 | .mpllb_sscen = |
1509 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
1510 | }; |
1511 | |
1512 | static const struct intel_mpllb_state dg2_hdmi_241500 = { |
1513 | .clock = 241500, |
1514 | .ref_control = |
1515 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
1516 | .mpllb_cp = |
1517 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | |
1518 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | |
1519 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
1520 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
1521 | .mpllb_div = |
1522 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
1523 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | |
1524 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
1525 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
1526 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), |
1527 | .mpllb_div2 = |
1528 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
1529 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 160) | |
1530 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
1531 | .mpllb_fracn1 = |
1532 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
1533 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
1534 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), |
1535 | .mpllb_fracn2 = |
1536 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) | |
1537 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 39320), |
1538 | .mpllb_sscen = |
1539 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
1540 | }; |
1541 | |
1542 | static const struct intel_mpllb_state dg2_hdmi_319890 = { |
1543 | .clock = 319890, |
1544 | .ref_control = |
1545 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
1546 | .mpllb_cp = |
1547 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | |
1548 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | |
1549 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
1550 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
1551 | .mpllb_div = |
1552 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
1553 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | |
1554 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
1555 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
1556 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2), |
1557 | .mpllb_div2 = |
1558 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
1559 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 94) | |
1560 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
1561 | .mpllb_fracn1 = |
1562 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
1563 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
1564 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), |
1565 | .mpllb_fracn2 = |
1566 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 64094) | |
1567 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13631), |
1568 | .mpllb_sscen = |
1569 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
1570 | }; |
1571 | |
1572 | static const struct intel_mpllb_state dg2_hdmi_497750 = { |
1573 | .clock = 497750, |
1574 | .ref_control = |
1575 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
1576 | .mpllb_cp = |
1577 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | |
1578 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | |
1579 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
1580 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
1581 | .mpllb_div = |
1582 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
1583 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | |
1584 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
1585 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
1586 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), |
1587 | .mpllb_div2 = |
1588 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
1589 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 166) | |
1590 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
1591 | .mpllb_fracn1 = |
1592 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
1593 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
1594 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), |
1595 | .mpllb_fracn2 = |
1596 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36044) | |
1597 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427), |
1598 | .mpllb_sscen = |
1599 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
1600 | }; |
1601 | |
1602 | static const struct intel_mpllb_state dg2_hdmi_592000 = { |
1603 | .clock = 592000, |
1604 | .ref_control = |
1605 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
1606 | .mpllb_cp = |
1607 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | |
1608 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | |
1609 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
1610 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
1611 | .mpllb_div = |
1612 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
1613 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 0) | |
1614 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
1615 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
1616 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), |
1617 | .mpllb_div2 = |
1618 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
1619 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | |
1620 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
1621 | .mpllb_fracn1 = |
1622 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
1623 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
1624 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), |
1625 | .mpllb_fracn2 = |
1626 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 13107) | |
1627 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107), |
1628 | .mpllb_sscen = |
1629 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
1630 | }; |
1631 | |
1632 | static const struct intel_mpllb_state dg2_hdmi_593407 = { |
1633 | .clock = 593407, |
1634 | .ref_control = |
1635 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
1636 | .mpllb_cp = |
1637 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | |
1638 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | |
1639 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
1640 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
1641 | .mpllb_div = |
1642 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
1643 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 0) | |
1644 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
1645 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
1646 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), |
1647 | .mpllb_div2 = |
1648 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
1649 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | |
1650 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
1651 | .mpllb_fracn1 = |
1652 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
1653 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
1654 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), |
1655 | .mpllb_fracn2 = |
1656 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 22328) | |
1657 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 7549), |
1658 | .mpllb_sscen = |
1659 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
1660 | }; |
1661 | |
1662 | static const struct intel_mpllb_state dg2_hdmi_297 = { |
1663 | .clock = 297000, |
1664 | .ref_control = |
1665 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
1666 | .mpllb_cp = |
1667 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | |
1668 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | |
1669 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
1670 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
1671 | .mpllb_div = |
1672 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
1673 | REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | |
1674 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
1675 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
1676 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), |
1677 | .mpllb_div2 = |
1678 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
1679 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | |
1680 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
1681 | .mpllb_fracn1 = |
1682 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
1683 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
1684 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), |
1685 | .mpllb_fracn2 = |
1686 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | |
1687 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214), |
1688 | .mpllb_sscen = |
1689 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
1690 | }; |
1691 | |
1692 | static const struct intel_mpllb_state dg2_hdmi_594 = { |
1693 | .clock = 594000, |
1694 | .ref_control = |
1695 | REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), |
1696 | .mpllb_cp = |
1697 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | |
1698 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | |
1699 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | |
1700 | REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), |
1701 | .mpllb_div = |
1702 | REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | |
1703 | REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | |
1704 | REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | |
1705 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), |
1706 | .mpllb_div2 = |
1707 | REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | |
1708 | REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | |
1709 | REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), |
1710 | .mpllb_fracn1 = |
1711 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | |
1712 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | |
1713 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), |
1714 | .mpllb_fracn2 = |
1715 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | |
1716 | REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2), |
1717 | .mpllb_sscen = |
1718 | REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), |
1719 | }; |
1720 | |
1721 | static const struct intel_mpllb_state * const dg2_hdmi_tables[] = { |
1722 | &dg2_hdmi_25_175, |
1723 | &dg2_hdmi_27_0, |
1724 | &dg2_hdmi_74_25, |
1725 | &dg2_hdmi_148_5, |
1726 | &dg2_hdmi_297, |
1727 | &dg2_hdmi_594, |
1728 | &dg2_hdmi_25200, |
1729 | &dg2_hdmi_27027, |
1730 | &dg2_hdmi_28320, |
1731 | &dg2_hdmi_30240, |
1732 | &dg2_hdmi_31500, |
1733 | &dg2_hdmi_36000, |
1734 | &dg2_hdmi_40000, |
1735 | &dg2_hdmi_49500, |
1736 | &dg2_hdmi_50000, |
1737 | &dg2_hdmi_57284, |
1738 | &dg2_hdmi_58000, |
1739 | &dg2_hdmi_65000, |
1740 | &dg2_hdmi_71000, |
1741 | &dg2_hdmi_74176, |
1742 | &dg2_hdmi_75000, |
1743 | &dg2_hdmi_78750, |
1744 | &dg2_hdmi_85500, |
1745 | &dg2_hdmi_88750, |
1746 | &dg2_hdmi_106500, |
1747 | &dg2_hdmi_108000, |
1748 | &dg2_hdmi_115500, |
1749 | &dg2_hdmi_119000, |
1750 | &dg2_hdmi_135000, |
1751 | &dg2_hdmi_138500, |
1752 | &dg2_hdmi_147160, |
1753 | &dg2_hdmi_148352, |
1754 | &dg2_hdmi_154000, |
1755 | &dg2_hdmi_162000, |
1756 | &dg2_hdmi_209800, |
1757 | &dg2_hdmi_241500, |
1758 | &dg2_hdmi_262750, |
1759 | &dg2_hdmi_267300, |
1760 | &dg2_hdmi_268500, |
1761 | &dg2_hdmi_296703, |
1762 | &dg2_hdmi_319890, |
1763 | &dg2_hdmi_497750, |
1764 | &dg2_hdmi_592000, |
1765 | &dg2_hdmi_593407, |
1766 | NULL, |
1767 | }; |
1768 | |
1769 | static const struct intel_mpllb_state * const * |
1770 | intel_mpllb_tables_get(struct intel_crtc_state *crtc_state, |
1771 | struct intel_encoder *encoder) |
1772 | { |
1773 | if (intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_EDP)) { |
1774 | return dg2_edp_tables; |
1775 | } else if (intel_crtc_has_dp_encoder(crtc_state)) { |
1776 | return dg2_dp_100_tables; |
1777 | } else if (intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_HDMI)) { |
1778 | return dg2_hdmi_tables; |
1779 | } |
1780 | |
1781 | MISSING_CASE(encoder->type); |
1782 | return NULL; |
1783 | } |
1784 | |
1785 | int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state, |
1786 | struct intel_encoder *encoder) |
1787 | { |
1788 | struct drm_i915_private *i915 = to_i915(dev: encoder->base.dev); |
1789 | const struct intel_mpllb_state * const *tables; |
1790 | int i; |
1791 | |
1792 | if (intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_HDMI)) { |
1793 | if (intel_snps_phy_check_hdmi_link_rate(clock: crtc_state->port_clock) |
1794 | != MODE_OK) { |
1795 | /* |
1796 | * FIXME: Can only support fixed HDMI frequencies |
1797 | * until we have a proper algorithm under a valid |
1798 | * license. |
1799 | */ |
1800 | drm_dbg_kms(&i915->drm, "Can't support HDMI link rate %d\n" , |
1801 | crtc_state->port_clock); |
1802 | return -EINVAL; |
1803 | } |
1804 | } |
1805 | |
1806 | tables = intel_mpllb_tables_get(crtc_state, encoder); |
1807 | if (!tables) |
1808 | return -EINVAL; |
1809 | |
1810 | for (i = 0; tables[i]; i++) { |
1811 | if (crtc_state->port_clock == tables[i]->clock) { |
1812 | crtc_state->mpllb_state = *tables[i]; |
1813 | return 0; |
1814 | } |
1815 | } |
1816 | |
1817 | return -EINVAL; |
1818 | } |
1819 | |
1820 | void intel_mpllb_enable(struct intel_encoder *encoder, |
1821 | const struct intel_crtc_state *crtc_state) |
1822 | { |
1823 | struct drm_i915_private *dev_priv = to_i915(dev: encoder->base.dev); |
1824 | const struct intel_mpllb_state *pll_state = &crtc_state->mpllb_state; |
1825 | enum phy phy = intel_port_to_phy(i915: dev_priv, port: encoder->port); |
1826 | i915_reg_t enable_reg = (phy <= PHY_D ? |
1827 | DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0)); |
1828 | |
1829 | /* |
1830 | * 3. Software programs the following PLL registers for the desired |
1831 | * frequency. |
1832 | */ |
1833 | intel_de_write(i915: dev_priv, SNPS_PHY_MPLLB_CP(phy), val: pll_state->mpllb_cp); |
1834 | intel_de_write(i915: dev_priv, SNPS_PHY_MPLLB_DIV(phy), val: pll_state->mpllb_div); |
1835 | intel_de_write(i915: dev_priv, SNPS_PHY_MPLLB_DIV2(phy), val: pll_state->mpllb_div2); |
1836 | intel_de_write(i915: dev_priv, SNPS_PHY_MPLLB_SSCEN(phy), val: pll_state->mpllb_sscen); |
1837 | intel_de_write(i915: dev_priv, SNPS_PHY_MPLLB_SSCSTEP(phy), val: pll_state->mpllb_sscstep); |
1838 | intel_de_write(i915: dev_priv, SNPS_PHY_MPLLB_FRACN1(phy), val: pll_state->mpllb_fracn1); |
1839 | intel_de_write(i915: dev_priv, SNPS_PHY_MPLLB_FRACN2(phy), val: pll_state->mpllb_fracn2); |
1840 | |
1841 | /* |
1842 | * 4. If the frequency will result in a change to the voltage |
1843 | * requirement, follow the Display Voltage Frequency Switching - |
1844 | * Sequence Before Frequency Change. |
1845 | * |
1846 | * We handle this step in bxt_set_cdclk(). |
1847 | */ |
1848 | |
1849 | /* 5. Software sets DPLL_ENABLE [PLL Enable] to "1". */ |
1850 | intel_de_rmw(i915: dev_priv, reg: enable_reg, clear: 0, PLL_ENABLE); |
1851 | |
1852 | /* |
1853 | * 9. Software sets SNPS_PHY_MPLLB_DIV dp_mpllb_force_en to "1". This |
1854 | * will keep the PLL running during the DDI lane programming and any |
1855 | * typeC DP cable disconnect. Do not set the force before enabling the |
1856 | * PLL because that will start the PLL before it has sampled the |
1857 | * divider values. |
1858 | */ |
1859 | intel_de_write(i915: dev_priv, SNPS_PHY_MPLLB_DIV(phy), |
1860 | val: pll_state->mpllb_div | SNPS_PHY_MPLLB_FORCE_EN); |
1861 | |
1862 | /* |
1863 | * 10. Software polls on register DPLL_ENABLE [PLL Lock] to confirm PLL |
1864 | * is locked at new settings. This register bit is sampling PHY |
1865 | * dp_mpllb_state interface signal. |
1866 | */ |
1867 | if (intel_de_wait_for_set(i915: dev_priv, reg: enable_reg, PLL_LOCK, timeout: 5)) |
1868 | drm_dbg_kms(&dev_priv->drm, "Port %c PLL not locked\n" , phy_name(phy)); |
1869 | |
1870 | /* |
1871 | * 11. If the frequency will result in a change to the voltage |
1872 | * requirement, follow the Display Voltage Frequency Switching - |
1873 | * Sequence After Frequency Change. |
1874 | * |
1875 | * We handle this step in bxt_set_cdclk(). |
1876 | */ |
1877 | } |
1878 | |
1879 | void intel_mpllb_disable(struct intel_encoder *encoder) |
1880 | { |
1881 | struct drm_i915_private *i915 = to_i915(dev: encoder->base.dev); |
1882 | enum phy phy = intel_port_to_phy(i915, port: encoder->port); |
1883 | i915_reg_t enable_reg = (phy <= PHY_D ? |
1884 | DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0)); |
1885 | |
1886 | /* |
1887 | * 1. If the frequency will result in a change to the voltage |
1888 | * requirement, follow the Display Voltage Frequency Switching - |
1889 | * Sequence Before Frequency Change. |
1890 | * |
1891 | * We handle this step in bxt_set_cdclk(). |
1892 | */ |
1893 | |
1894 | /* 2. Software programs DPLL_ENABLE [PLL Enable] to "0" */ |
1895 | intel_de_rmw(i915, reg: enable_reg, PLL_ENABLE, set: 0); |
1896 | |
1897 | /* |
1898 | * 4. Software programs SNPS_PHY_MPLLB_DIV dp_mpllb_force_en to "0". |
1899 | * This will allow the PLL to stop running. |
1900 | */ |
1901 | intel_de_rmw(i915, SNPS_PHY_MPLLB_DIV(phy), SNPS_PHY_MPLLB_FORCE_EN, set: 0); |
1902 | |
1903 | /* |
1904 | * 5. Software polls DPLL_ENABLE [PLL Lock] for PHY acknowledgment |
1905 | * (dp_txX_ack) that the new transmitter setting request is completed. |
1906 | */ |
1907 | if (intel_de_wait_for_clear(i915, reg: enable_reg, PLL_LOCK, timeout: 5)) |
1908 | drm_err(&i915->drm, "Port %c PLL not locked\n" , phy_name(phy)); |
1909 | |
1910 | /* |
1911 | * 6. If the frequency will result in a change to the voltage |
1912 | * requirement, follow the Display Voltage Frequency Switching - |
1913 | * Sequence After Frequency Change. |
1914 | * |
1915 | * We handle this step in bxt_set_cdclk(). |
1916 | */ |
1917 | } |
1918 | |
1919 | int intel_mpllb_calc_port_clock(struct intel_encoder *encoder, |
1920 | const struct intel_mpllb_state *pll_state) |
1921 | { |
1922 | unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1; |
1923 | unsigned int multiplier, tx_clk_div, refclk; |
1924 | bool frac_en; |
1925 | |
1926 | if (0) |
1927 | refclk = 38400; |
1928 | else |
1929 | refclk = 100000; |
1930 | |
1931 | refclk >>= REG_FIELD_GET(SNPS_PHY_MPLLB_REF_CLK_DIV, pll_state->mpllb_div2) - 1; |
1932 | |
1933 | frac_en = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_EN, pll_state->mpllb_fracn1); |
1934 | |
1935 | if (frac_en) { |
1936 | frac_quot = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_QUOT, pll_state->mpllb_fracn2); |
1937 | frac_rem = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_REM, pll_state->mpllb_fracn2); |
1938 | frac_den = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_DEN, pll_state->mpllb_fracn1); |
1939 | } |
1940 | |
1941 | multiplier = REG_FIELD_GET(SNPS_PHY_MPLLB_MULTIPLIER, pll_state->mpllb_div2) / 2 + 16; |
1942 | |
1943 | tx_clk_div = REG_FIELD_GET(SNPS_PHY_MPLLB_TX_CLK_DIV, pll_state->mpllb_div); |
1944 | |
1945 | return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) + |
1946 | DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den), |
1947 | 10 << (tx_clk_div + 16)); |
1948 | } |
1949 | |
1950 | void intel_mpllb_readout_hw_state(struct intel_encoder *encoder, |
1951 | struct intel_mpllb_state *pll_state) |
1952 | { |
1953 | struct drm_i915_private *dev_priv = to_i915(dev: encoder->base.dev); |
1954 | enum phy phy = intel_port_to_phy(i915: dev_priv, port: encoder->port); |
1955 | |
1956 | pll_state->mpllb_cp = intel_de_read(i915: dev_priv, SNPS_PHY_MPLLB_CP(phy)); |
1957 | pll_state->mpllb_div = intel_de_read(i915: dev_priv, SNPS_PHY_MPLLB_DIV(phy)); |
1958 | pll_state->mpllb_div2 = intel_de_read(i915: dev_priv, SNPS_PHY_MPLLB_DIV2(phy)); |
1959 | pll_state->mpllb_sscen = intel_de_read(i915: dev_priv, SNPS_PHY_MPLLB_SSCEN(phy)); |
1960 | pll_state->mpllb_sscstep = intel_de_read(i915: dev_priv, SNPS_PHY_MPLLB_SSCSTEP(phy)); |
1961 | pll_state->mpllb_fracn1 = intel_de_read(i915: dev_priv, SNPS_PHY_MPLLB_FRACN1(phy)); |
1962 | pll_state->mpllb_fracn2 = intel_de_read(i915: dev_priv, SNPS_PHY_MPLLB_FRACN2(phy)); |
1963 | |
1964 | /* |
1965 | * REF_CONTROL is under firmware control and never programmed by the |
1966 | * driver; we read it only for sanity checking purposes. The bspec |
1967 | * only tells us the expected value for one field in this register, |
1968 | * so we'll only read out those specific bits here. |
1969 | */ |
1970 | pll_state->ref_control = intel_de_read(i915: dev_priv, SNPS_PHY_REF_CONTROL(phy)) & |
1971 | SNPS_PHY_REF_CONTROL_REF_RANGE; |
1972 | |
1973 | /* |
1974 | * MPLLB_DIV is programmed twice, once with the software-computed |
1975 | * state, then again with the MPLLB_FORCE_EN bit added. Drop that |
1976 | * extra bit during readout so that we return the actual expected |
1977 | * software state. |
1978 | */ |
1979 | pll_state->mpllb_div &= ~SNPS_PHY_MPLLB_FORCE_EN; |
1980 | } |
1981 | |
1982 | int intel_snps_phy_check_hdmi_link_rate(int clock) |
1983 | { |
1984 | const struct intel_mpllb_state * const *tables = dg2_hdmi_tables; |
1985 | int i; |
1986 | |
1987 | for (i = 0; tables[i]; i++) { |
1988 | if (clock == tables[i]->clock) |
1989 | return MODE_OK; |
1990 | } |
1991 | |
1992 | return MODE_CLOCK_RANGE; |
1993 | } |
1994 | |
1995 | void intel_mpllb_state_verify(struct intel_atomic_state *state, |
1996 | struct intel_crtc *crtc) |
1997 | { |
1998 | struct drm_i915_private *i915 = to_i915(dev: state->base.dev); |
1999 | const struct intel_crtc_state *new_crtc_state = |
2000 | intel_atomic_get_new_crtc_state(state, crtc); |
2001 | struct intel_mpllb_state mpllb_hw_state = {}; |
2002 | const struct intel_mpllb_state *mpllb_sw_state = &new_crtc_state->mpllb_state; |
2003 | struct intel_encoder *encoder; |
2004 | |
2005 | if (!IS_DG2(i915)) |
2006 | return; |
2007 | |
2008 | if (!new_crtc_state->hw.active) |
2009 | return; |
2010 | |
2011 | /* intel_get_crtc_new_encoder() only works for modeset/fastset commits */ |
2012 | if (!intel_crtc_needs_modeset(crtc_state: new_crtc_state) && |
2013 | !intel_crtc_needs_fastset(crtc_state: new_crtc_state)) |
2014 | return; |
2015 | |
2016 | encoder = intel_get_crtc_new_encoder(state, crtc_state: new_crtc_state); |
2017 | intel_mpllb_readout_hw_state(encoder, pll_state: &mpllb_hw_state); |
2018 | |
2019 | #define MPLLB_CHECK(__name) \ |
2020 | I915_STATE_WARN(i915, mpllb_sw_state->__name != mpllb_hw_state.__name, \ |
2021 | "[CRTC:%d:%s] mismatch in MPLLB: %s (expected 0x%08x, found 0x%08x)", \ |
2022 | crtc->base.base.id, crtc->base.name, \ |
2023 | __stringify(__name), \ |
2024 | mpllb_sw_state->__name, mpllb_hw_state.__name) |
2025 | |
2026 | MPLLB_CHECK(mpllb_cp); |
2027 | MPLLB_CHECK(mpllb_div); |
2028 | MPLLB_CHECK(mpllb_div2); |
2029 | MPLLB_CHECK(mpllb_fracn1); |
2030 | MPLLB_CHECK(mpllb_fracn2); |
2031 | MPLLB_CHECK(mpllb_sscen); |
2032 | MPLLB_CHECK(mpllb_sscstep); |
2033 | |
2034 | /* |
2035 | * ref_control is handled by the hardware/firemware and never |
2036 | * programmed by the software, but the proper values are supplied |
2037 | * in the bspec for verification purposes. |
2038 | */ |
2039 | MPLLB_CHECK(ref_control); |
2040 | |
2041 | #undef MPLLB_CHECK |
2042 | } |
2043 | |