1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2022-2023 Intel Corporation
4 */
5
6#include "i915_drv.h"
7#include "i915_reg.h"
8#include "intel_crtc.h"
9#include "intel_de.h"
10#include "intel_display_types.h"
11#include "intel_vblank.h"
12#include "intel_vrr.h"
13
14/*
15 * This timing diagram depicts the video signal in and
16 * around the vertical blanking period.
17 *
18 * Assumptions about the fictitious mode used in this example:
19 * vblank_start >= 3
20 * vsync_start = vblank_start + 1
21 * vsync_end = vblank_start + 2
22 * vtotal = vblank_start + 3
23 *
24 * start of vblank:
25 * latch double buffered registers
26 * increment frame counter (ctg+)
27 * generate start of vblank interrupt (gen4+)
28 * |
29 * | frame start:
30 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
31 * | may be shifted forward 1-3 extra lines via TRANSCONF
32 * | |
33 * | | start of vsync:
34 * | | generate vsync interrupt
35 * | | |
36 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
37 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
38 * ----va---> <-----------------vb--------------------> <--------va-------------
39 * | | <----vs-----> |
40 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
41 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
42 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
43 * | | |
44 * last visible pixel first visible pixel
45 * | increment frame counter (gen3/4)
46 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
47 *
48 * x = horizontal active
49 * _ = horizontal blanking
50 * hs = horizontal sync
51 * va = vertical active
52 * vb = vertical blanking
53 * vs = vertical sync
54 * vbs = vblank_start (number)
55 *
56 * Summary:
57 * - most events happen at the start of horizontal sync
58 * - frame start happens at the start of horizontal blank, 1-4 lines
59 * (depending on TRANSCONF settings) after the start of vblank
60 * - gen3/4 pixel and frame counter are synchronized with the start
61 * of horizontal active on the first line of vertical active
62 */
63
64/*
65 * Called from drm generic code, passed a 'crtc', which we use as a pipe index.
66 */
67u32 i915_get_vblank_counter(struct drm_crtc *crtc)
68{
69 struct drm_i915_private *dev_priv = to_i915(dev: crtc->dev);
70 struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)];
71 const struct drm_display_mode *mode = &vblank->hwmode;
72 enum pipe pipe = to_intel_crtc(crtc)->pipe;
73 u32 pixel, vbl_start, hsync_start, htotal;
74 u64 frame;
75
76 /*
77 * On i965gm TV output the frame counter only works up to
78 * the point when we enable the TV encoder. After that the
79 * frame counter ceases to work and reads zero. We need a
80 * vblank wait before enabling the TV encoder and so we
81 * have to enable vblank interrupts while the frame counter
82 * is still in a working state. However the core vblank code
83 * does not like us returning non-zero frame counter values
84 * when we've told it that we don't have a working frame
85 * counter. Thus we must stop non-zero values leaking out.
86 */
87 if (!vblank->max_vblank_count)
88 return 0;
89
90 htotal = mode->crtc_htotal;
91 hsync_start = mode->crtc_hsync_start;
92 vbl_start = mode->crtc_vblank_start;
93 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
94 vbl_start = DIV_ROUND_UP(vbl_start, 2);
95
96 /* Convert to pixel count */
97 vbl_start *= htotal;
98
99 /* Start of vblank event occurs at start of hsync */
100 vbl_start -= htotal - hsync_start;
101
102 /*
103 * High & low register fields aren't synchronized, so make sure
104 * we get a low value that's stable across two reads of the high
105 * register.
106 */
107 frame = intel_de_read64_2x32(i915: dev_priv, PIPEFRAMEPIXEL(pipe), PIPEFRAME(pipe));
108
109 pixel = frame & PIPE_PIXEL_MASK;
110 frame = (frame >> PIPE_FRAME_LOW_SHIFT) & 0xffffff;
111
112 /*
113 * The frame counter increments at beginning of active.
114 * Cook up a vblank counter by also checking the pixel
115 * counter against vblank start.
116 */
117 return (frame + (pixel >= vbl_start)) & 0xffffff;
118}
119
120u32 g4x_get_vblank_counter(struct drm_crtc *crtc)
121{
122 struct drm_i915_private *dev_priv = to_i915(dev: crtc->dev);
123 struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)];
124 enum pipe pipe = to_intel_crtc(crtc)->pipe;
125
126 if (!vblank->max_vblank_count)
127 return 0;
128
129 return intel_de_read(i915: dev_priv, PIPE_FRMCOUNT_G4X(pipe));
130}
131
132static u32 intel_crtc_scanlines_since_frame_timestamp(struct intel_crtc *crtc)
133{
134 struct drm_i915_private *dev_priv = to_i915(dev: crtc->base.dev);
135 struct drm_vblank_crtc *vblank =
136 &crtc->base.dev->vblank[drm_crtc_index(crtc: &crtc->base)];
137 const struct drm_display_mode *mode = &vblank->hwmode;
138 u32 htotal = mode->crtc_htotal;
139 u32 clock = mode->crtc_clock;
140 u32 scan_prev_time, scan_curr_time, scan_post_time;
141
142 /*
143 * To avoid the race condition where we might cross into the
144 * next vblank just between the PIPE_FRMTMSTMP and TIMESTAMP_CTR
145 * reads. We make sure we read PIPE_FRMTMSTMP and TIMESTAMP_CTR
146 * during the same frame.
147 */
148 do {
149 /*
150 * This field provides read back of the display
151 * pipe frame time stamp. The time stamp value
152 * is sampled at every start of vertical blank.
153 */
154 scan_prev_time = intel_de_read_fw(i915: dev_priv,
155 PIPE_FRMTMSTMP(crtc->pipe));
156
157 /*
158 * The TIMESTAMP_CTR register has the current
159 * time stamp value.
160 */
161 scan_curr_time = intel_de_read_fw(i915: dev_priv, IVB_TIMESTAMP_CTR);
162
163 scan_post_time = intel_de_read_fw(i915: dev_priv,
164 PIPE_FRMTMSTMP(crtc->pipe));
165 } while (scan_post_time != scan_prev_time);
166
167 return div_u64(dividend: mul_u32_u32(a: scan_curr_time - scan_prev_time,
168 b: clock), divisor: 1000 * htotal);
169}
170
171/*
172 * On certain encoders on certain platforms, pipe
173 * scanline register will not work to get the scanline,
174 * since the timings are driven from the PORT or issues
175 * with scanline register updates.
176 * This function will use Framestamp and current
177 * timestamp registers to calculate the scanline.
178 */
179static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
180{
181 struct drm_vblank_crtc *vblank =
182 &crtc->base.dev->vblank[drm_crtc_index(crtc: &crtc->base)];
183 const struct drm_display_mode *mode = &vblank->hwmode;
184 u32 vblank_start = mode->crtc_vblank_start;
185 u32 vtotal = mode->crtc_vtotal;
186 u32 scanline;
187
188 scanline = intel_crtc_scanlines_since_frame_timestamp(crtc);
189 scanline = min(scanline, vtotal - 1);
190 scanline = (scanline + vblank_start) % vtotal;
191
192 return scanline;
193}
194
195/*
196 * intel_de_read_fw(), only for fast reads of display block, no need for
197 * forcewake etc.
198 */
199static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
200{
201 struct drm_device *dev = crtc->base.dev;
202 struct drm_i915_private *dev_priv = to_i915(dev);
203 const struct drm_display_mode *mode;
204 struct drm_vblank_crtc *vblank;
205 enum pipe pipe = crtc->pipe;
206 int position, vtotal;
207
208 if (!crtc->active)
209 return 0;
210
211 vblank = &crtc->base.dev->vblank[drm_crtc_index(crtc: &crtc->base)];
212 mode = &vblank->hwmode;
213
214 if (crtc->mode_flags & I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP)
215 return __intel_get_crtc_scanline_from_timestamp(crtc);
216
217 vtotal = mode->crtc_vtotal;
218 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
219 vtotal /= 2;
220
221 position = intel_de_read_fw(i915: dev_priv, PIPEDSL(pipe)) & PIPEDSL_LINE_MASK;
222
223 /*
224 * On HSW, the DSL reg (0x70000) appears to return 0 if we
225 * read it just before the start of vblank. So try it again
226 * so we don't accidentally end up spanning a vblank frame
227 * increment, causing the pipe_update_end() code to squak at us.
228 *
229 * The nature of this problem means we can't simply check the ISR
230 * bit and return the vblank start value; nor can we use the scanline
231 * debug register in the transcoder as it appears to have the same
232 * problem. We may need to extend this to include other platforms,
233 * but so far testing only shows the problem on HSW.
234 */
235 if (HAS_DDI(dev_priv) && !position) {
236 int i, temp;
237
238 for (i = 0; i < 100; i++) {
239 udelay(1);
240 temp = intel_de_read_fw(i915: dev_priv, PIPEDSL(pipe)) & PIPEDSL_LINE_MASK;
241 if (temp != position) {
242 position = temp;
243 break;
244 }
245 }
246 }
247
248 /*
249 * See update_scanline_offset() for the details on the
250 * scanline_offset adjustment.
251 */
252 return (position + crtc->scanline_offset) % vtotal;
253}
254
255int intel_crtc_scanline_to_hw(struct intel_crtc *crtc, int scanline)
256{
257 const struct drm_vblank_crtc *vblank =
258 &crtc->base.dev->vblank[drm_crtc_index(crtc: &crtc->base)];
259 const struct drm_display_mode *mode = &vblank->hwmode;
260 int vtotal;
261
262 vtotal = mode->crtc_vtotal;
263 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
264 vtotal /= 2;
265
266 return (scanline + vtotal - crtc->scanline_offset) % vtotal;
267}
268
269/*
270 * The uncore version of the spin lock functions is used to decide
271 * whether we need to lock the uncore lock or not. This is only
272 * needed in i915, not in Xe.
273 *
274 * This lock in i915 is needed because some old platforms (at least
275 * IVB and possibly HSW as well), which are not supported in Xe, need
276 * all register accesses to the same cacheline to be serialized,
277 * otherwise they may hang.
278 */
279static void intel_vblank_section_enter(struct drm_i915_private *i915)
280 __acquires(i915->uncore.lock)
281{
282#ifdef I915
283 spin_lock(lock: &i915->uncore.lock);
284#endif
285}
286
287static void intel_vblank_section_exit(struct drm_i915_private *i915)
288 __releases(i915->uncore.lock)
289{
290#ifdef I915
291 spin_unlock(lock: &i915->uncore.lock);
292#endif
293}
294
295static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
296 bool in_vblank_irq,
297 int *vpos, int *hpos,
298 ktime_t *stime, ktime_t *etime,
299 const struct drm_display_mode *mode)
300{
301 struct drm_device *dev = _crtc->dev;
302 struct drm_i915_private *dev_priv = to_i915(dev);
303 struct intel_crtc *crtc = to_intel_crtc(_crtc);
304 enum pipe pipe = crtc->pipe;
305 int position;
306 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
307 unsigned long irqflags;
308 bool use_scanline_counter = DISPLAY_VER(dev_priv) >= 5 ||
309 IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) == 2 ||
310 crtc->mode_flags & I915_MODE_FLAG_USE_SCANLINE_COUNTER;
311
312 if (drm_WARN_ON(&dev_priv->drm, !mode->crtc_clock)) {
313 drm_dbg(&dev_priv->drm,
314 "trying to get scanoutpos for disabled pipe %c\n",
315 pipe_name(pipe));
316 return false;
317 }
318
319 htotal = mode->crtc_htotal;
320 hsync_start = mode->crtc_hsync_start;
321 vtotal = mode->crtc_vtotal;
322 vbl_start = mode->crtc_vblank_start;
323 vbl_end = mode->crtc_vblank_end;
324
325 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
326 vbl_start = DIV_ROUND_UP(vbl_start, 2);
327 vbl_end /= 2;
328 vtotal /= 2;
329 }
330
331 /*
332 * Enter vblank critical section, as we will do multiple
333 * timing critical raw register reads, potentially with
334 * preemption disabled, so the following code must not block.
335 */
336 local_irq_save(irqflags);
337 intel_vblank_section_enter(i915: dev_priv);
338
339 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
340
341 /* Get optional system timestamp before query. */
342 if (stime)
343 *stime = ktime_get();
344
345 if (crtc->mode_flags & I915_MODE_FLAG_VRR) {
346 int scanlines = intel_crtc_scanlines_since_frame_timestamp(crtc);
347
348 position = __intel_get_crtc_scanline(crtc);
349
350 /*
351 * Already exiting vblank? If so, shift our position
352 * so it looks like we're already apporaching the full
353 * vblank end. This should make the generated timestamp
354 * more or less match when the active portion will start.
355 */
356 if (position >= vbl_start && scanlines < position)
357 position = min(crtc->vmax_vblank_start + scanlines, vtotal - 1);
358 } else if (use_scanline_counter) {
359 /* No obvious pixelcount register. Only query vertical
360 * scanout position from Display scan line register.
361 */
362 position = __intel_get_crtc_scanline(crtc);
363 } else {
364 /*
365 * Have access to pixelcount since start of frame.
366 * We can split this into vertical and horizontal
367 * scanout position.
368 */
369 position = (intel_de_read_fw(i915: dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
370
371 /* convert to pixel counts */
372 vbl_start *= htotal;
373 vbl_end *= htotal;
374 vtotal *= htotal;
375
376 /*
377 * In interlaced modes, the pixel counter counts all pixels,
378 * so one field will have htotal more pixels. In order to avoid
379 * the reported position from jumping backwards when the pixel
380 * counter is beyond the length of the shorter field, just
381 * clamp the position the length of the shorter field. This
382 * matches how the scanline counter based position works since
383 * the scanline counter doesn't count the two half lines.
384 */
385 position = min(position, vtotal - 1);
386
387 /*
388 * Start of vblank interrupt is triggered at start of hsync,
389 * just prior to the first active line of vblank. However we
390 * consider lines to start at the leading edge of horizontal
391 * active. So, should we get here before we've crossed into
392 * the horizontal active of the first line in vblank, we would
393 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
394 * always add htotal-hsync_start to the current pixel position.
395 */
396 position = (position + htotal - hsync_start) % vtotal;
397 }
398
399 /* Get optional system timestamp after query. */
400 if (etime)
401 *etime = ktime_get();
402
403 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
404
405 intel_vblank_section_exit(i915: dev_priv);
406 local_irq_restore(irqflags);
407
408 /*
409 * While in vblank, position will be negative
410 * counting up towards 0 at vbl_end. And outside
411 * vblank, position will be positive counting
412 * up since vbl_end.
413 */
414 if (position >= vbl_start)
415 position -= vbl_end;
416 else
417 position += vtotal - vbl_end;
418
419 if (use_scanline_counter) {
420 *vpos = position;
421 *hpos = 0;
422 } else {
423 *vpos = position / htotal;
424 *hpos = position - (*vpos * htotal);
425 }
426
427 return true;
428}
429
430bool intel_crtc_get_vblank_timestamp(struct drm_crtc *crtc, int *max_error,
431 ktime_t *vblank_time, bool in_vblank_irq)
432{
433 return drm_crtc_vblank_helper_get_vblank_timestamp_internal(
434 crtc, max_error, vblank_time, in_vblank_irq,
435 get_scanout_position: i915_get_crtc_scanoutpos);
436}
437
438int intel_get_crtc_scanline(struct intel_crtc *crtc)
439{
440 struct drm_i915_private *dev_priv = to_i915(dev: crtc->base.dev);
441 unsigned long irqflags;
442 int position;
443
444 local_irq_save(irqflags);
445 intel_vblank_section_enter(i915: dev_priv);
446
447 position = __intel_get_crtc_scanline(crtc);
448
449 intel_vblank_section_exit(i915: dev_priv);
450 local_irq_restore(irqflags);
451
452 return position;
453}
454
455static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
456 enum pipe pipe)
457{
458 i915_reg_t reg = PIPEDSL(pipe);
459 u32 line1, line2;
460
461 line1 = intel_de_read(i915: dev_priv, reg) & PIPEDSL_LINE_MASK;
462 msleep(msecs: 5);
463 line2 = intel_de_read(i915: dev_priv, reg) & PIPEDSL_LINE_MASK;
464
465 return line1 != line2;
466}
467
468static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
469{
470 struct drm_i915_private *dev_priv = to_i915(dev: crtc->base.dev);
471 enum pipe pipe = crtc->pipe;
472
473 /* Wait for the display line to settle/start moving */
474 if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
475 drm_err(&dev_priv->drm,
476 "pipe %c scanline %s wait timed out\n",
477 pipe_name(pipe), str_on_off(state));
478}
479
480void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
481{
482 wait_for_pipe_scanline_moving(crtc, state: false);
483}
484
485void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
486{
487 wait_for_pipe_scanline_moving(crtc, state: true);
488}
489
490static int intel_crtc_scanline_offset(const struct intel_crtc_state *crtc_state)
491{
492 struct drm_i915_private *i915 = to_i915(dev: crtc_state->uapi.crtc->dev);
493 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
494
495 /*
496 * The scanline counter increments at the leading edge of hsync.
497 *
498 * On most platforms it starts counting from vtotal-1 on the
499 * first active line. That means the scanline counter value is
500 * always one less than what we would expect. Ie. just after
501 * start of vblank, which also occurs at start of hsync (on the
502 * last active line), the scanline counter will read vblank_start-1.
503 *
504 * On gen2 the scanline counter starts counting from 1 instead
505 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
506 * to keep the value positive), instead of adding one.
507 *
508 * On HSW+ the behaviour of the scanline counter depends on the output
509 * type. For DP ports it behaves like most other platforms, but on HDMI
510 * there's an extra 1 line difference. So we need to add two instead of
511 * one to the value.
512 *
513 * On VLV/CHV DSI the scanline counter would appear to increment
514 * approx. 1/3 of a scanline before start of vblank. Unfortunately
515 * that means we can't tell whether we're in vblank or not while
516 * we're on that particular line. We must still set scanline_offset
517 * to 1 so that the vblank timestamps come out correct when we query
518 * the scanline counter from within the vblank interrupt handler.
519 * However if queried just before the start of vblank we'll get an
520 * answer that's slightly in the future.
521 */
522 if (DISPLAY_VER(i915) == 2) {
523 int vtotal;
524
525 vtotal = adjusted_mode->crtc_vtotal;
526 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
527 vtotal /= 2;
528
529 return vtotal - 1;
530 } else if (HAS_DDI(i915) && intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_HDMI)) {
531 return 2;
532 } else {
533 return 1;
534 }
535}
536
537void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state,
538 bool vrr_enable)
539{
540 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
541 struct drm_i915_private *i915 = to_i915(dev: crtc->base.dev);
542 u8 mode_flags = crtc_state->mode_flags;
543 struct drm_display_mode adjusted_mode;
544 int vmax_vblank_start = 0;
545 unsigned long irqflags;
546
547 drm_mode_init(dst: &adjusted_mode, src: &crtc_state->hw.adjusted_mode);
548
549 if (vrr_enable) {
550 drm_WARN_ON(&i915->drm, (mode_flags & I915_MODE_FLAG_VRR) == 0);
551
552 adjusted_mode.crtc_vtotal = crtc_state->vrr.vmax;
553 adjusted_mode.crtc_vblank_end = crtc_state->vrr.vmax;
554 adjusted_mode.crtc_vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
555 vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
556 } else {
557 mode_flags &= ~I915_MODE_FLAG_VRR;
558 }
559
560 /*
561 * Belts and suspenders locking to guarantee everyone sees 100%
562 * consistent state during fastset seamless refresh rate changes.
563 *
564 * vblank_time_lock takes care of all drm_vblank.c stuff, and
565 * uncore.lock takes care of __intel_get_crtc_scanline() which
566 * may get called elsewhere as well.
567 *
568 * TODO maybe just protect everything (including
569 * __intel_get_crtc_scanline()) with vblank_time_lock?
570 * Need to audit everything to make sure it's safe.
571 */
572 spin_lock_irqsave(&i915->drm.vblank_time_lock, irqflags);
573 intel_vblank_section_enter(i915);
574
575 drm_calc_timestamping_constants(crtc: &crtc->base, mode: &adjusted_mode);
576
577 crtc->vmax_vblank_start = vmax_vblank_start;
578
579 crtc->mode_flags = mode_flags;
580
581 crtc->scanline_offset = intel_crtc_scanline_offset(crtc_state);
582 intel_vblank_section_exit(i915);
583 spin_unlock_irqrestore(lock: &i915->drm.vblank_time_lock, flags: irqflags);
584}
585
586static int intel_mode_vblank_start(const struct drm_display_mode *mode)
587{
588 int vblank_start = mode->crtc_vblank_start;
589
590 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
591 vblank_start = DIV_ROUND_UP(vblank_start, 2);
592
593 return vblank_start;
594}
595
596void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
597 const struct intel_crtc_state *new_crtc_state,
598 struct intel_vblank_evade_ctx *evade)
599{
600 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
601 struct drm_i915_private *i915 = to_i915(dev: crtc->base.dev);
602 const struct intel_crtc_state *crtc_state;
603 const struct drm_display_mode *adjusted_mode;
604
605 evade->crtc = crtc;
606
607 evade->need_vlv_dsi_wa = (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) &&
608 intel_crtc_has_type(crtc_state: new_crtc_state, type: INTEL_OUTPUT_DSI);
609
610 /*
611 * During fastsets/etc. the transcoder is still
612 * running with the old timings at this point.
613 *
614 * TODO: maybe just use the active timings here?
615 */
616 if (intel_crtc_needs_modeset(crtc_state: new_crtc_state))
617 crtc_state = new_crtc_state;
618 else
619 crtc_state = old_crtc_state;
620
621 adjusted_mode = &crtc_state->hw.adjusted_mode;
622
623 if (crtc->mode_flags & I915_MODE_FLAG_VRR) {
624 /* timing changes should happen with VRR disabled */
625 drm_WARN_ON(crtc->base.dev, intel_crtc_needs_modeset(new_crtc_state) ||
626 new_crtc_state->update_m_n || new_crtc_state->update_lrr);
627
628 if (intel_vrr_is_push_sent(crtc_state))
629 evade->vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
630 else
631 evade->vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
632 } else {
633 evade->vblank_start = intel_mode_vblank_start(mode: adjusted_mode);
634 }
635
636 /* FIXME needs to be calibrated sensibly */
637 evade->min = evade->vblank_start - intel_usecs_to_scanlines(adjusted_mode,
638 VBLANK_EVASION_TIME_US);
639 evade->max = evade->vblank_start - 1;
640
641 /*
642 * M/N and TRANS_VTOTAL are double buffered on the transcoder's
643 * undelayed vblank, so with seamless M/N and LRR we must evade
644 * both vblanks.
645 *
646 * DSB execution waits for the transcoder's undelayed vblank,
647 * hence we must kick off the commit before that.
648 */
649 if (new_crtc_state->dsb || new_crtc_state->update_m_n || new_crtc_state->update_lrr)
650 evade->min -= adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;
651}
652
653/* must be called with vblank interrupt already enabled! */
654int intel_vblank_evade(struct intel_vblank_evade_ctx *evade)
655{
656 struct intel_crtc *crtc = evade->crtc;
657 struct drm_i915_private *i915 = to_i915(dev: crtc->base.dev);
658 long timeout = msecs_to_jiffies_timeout(m: 1);
659 wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(crtc: &crtc->base);
660 DEFINE_WAIT(wait);
661 int scanline;
662
663 if (evade->min <= 0 || evade->max <= 0)
664 return 0;
665
666 for (;;) {
667 /*
668 * prepare_to_wait() has a memory barrier, which guarantees
669 * other CPUs can see the task state update by the time we
670 * read the scanline.
671 */
672 prepare_to_wait(wq_head: wq, wq_entry: &wait, TASK_UNINTERRUPTIBLE);
673
674 scanline = intel_get_crtc_scanline(crtc);
675 if (scanline < evade->min || scanline > evade->max)
676 break;
677
678 if (!timeout) {
679 drm_err(&i915->drm,
680 "Potential atomic update failure on pipe %c\n",
681 pipe_name(crtc->pipe));
682 break;
683 }
684
685 local_irq_enable();
686
687 timeout = schedule_timeout(timeout);
688
689 local_irq_disable();
690 }
691
692 finish_wait(wq_head: wq, wq_entry: &wait);
693
694 /*
695 * On VLV/CHV DSI the scanline counter would appear to
696 * increment approx. 1/3 of a scanline before start of vblank.
697 * The registers still get latched at start of vblank however.
698 * This means we must not write any registers on the first
699 * line of vblank (since not the whole line is actually in
700 * vblank). And unfortunately we can't use the interrupt to
701 * wait here since it will fire too soon. We could use the
702 * frame start interrupt instead since it will fire after the
703 * critical scanline, but that would require more changes
704 * in the interrupt code. So for now we'll just do the nasty
705 * thing and poll for the bad scanline to pass us by.
706 *
707 * FIXME figure out if BXT+ DSI suffers from this as well
708 */
709 while (evade->need_vlv_dsi_wa && scanline == evade->vblank_start)
710 scanline = intel_get_crtc_scanline(crtc);
711
712 return scanline;
713}
714

source code of linux/drivers/gpu/drm/i915/display/intel_vblank.c