| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | /* |
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| 3 | * Copyright © 2022 Intel Corporation |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __SKL_WATERMARK_H__ |
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| 7 | #define __SKL_WATERMARK_H__ |
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| 8 | |
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| 9 | #include <linux/types.h> |
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| 10 | |
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| 11 | #include "intel_display_limits.h" |
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| 12 | #include "intel_global_state.h" |
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| 13 | #include "intel_wm_types.h" |
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| 14 | |
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| 15 | struct drm_i915_private; |
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| 16 | struct intel_atomic_state; |
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| 17 | struct intel_bw_state; |
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| 18 | struct intel_crtc; |
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| 19 | struct intel_crtc_state; |
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| 20 | struct intel_plane; |
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| 21 | |
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| 22 | u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *i915); |
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| 23 | |
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| 24 | void intel_sagv_pre_plane_update(struct intel_atomic_state *state); |
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| 25 | void intel_sagv_post_plane_update(struct intel_atomic_state *state); |
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| 26 | bool intel_can_enable_sagv(struct drm_i915_private *i915, |
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| 27 | const struct intel_bw_state *bw_state); |
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| 28 | |
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| 29 | u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *i915, |
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| 30 | const struct skl_ddb_entry *entry); |
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| 31 | |
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| 32 | void skl_write_plane_wm(struct intel_plane *plane, |
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| 33 | const struct intel_crtc_state *crtc_state); |
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| 34 | void skl_write_cursor_wm(struct intel_plane *plane, |
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| 35 | const struct intel_crtc_state *crtc_state); |
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| 36 | |
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| 37 | bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb, |
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| 38 | const struct skl_ddb_entry *entries, |
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| 39 | int num_entries, int ignore_idx); |
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| 40 | |
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| 41 | void intel_wm_state_verify(struct intel_atomic_state *state, |
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| 42 | struct intel_crtc *crtc); |
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| 43 | |
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| 44 | void skl_watermark_ipc_init(struct drm_i915_private *i915); |
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| 45 | void skl_watermark_ipc_update(struct drm_i915_private *i915); |
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| 46 | bool skl_watermark_ipc_enabled(struct drm_i915_private *i915); |
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| 47 | void skl_watermark_debugfs_register(struct drm_i915_private *i915); |
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| 48 | |
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| 49 | unsigned int skl_watermark_max_latency(struct drm_i915_private *i915, |
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| 50 | int initial_wm_level); |
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| 51 | void skl_wm_init(struct drm_i915_private *i915); |
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| 52 | |
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| 53 | struct intel_dbuf_state { |
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| 54 | struct intel_global_state base; |
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| 55 | |
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| 56 | struct skl_ddb_entry ddb[I915_MAX_PIPES]; |
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| 57 | unsigned int weight[I915_MAX_PIPES]; |
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| 58 | u8 slices[I915_MAX_PIPES]; |
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| 59 | u8 enabled_slices; |
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| 60 | u8 active_pipes; |
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| 61 | bool joined_mbus; |
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| 62 | }; |
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| 63 | |
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| 64 | struct intel_dbuf_state * |
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| 65 | intel_atomic_get_dbuf_state(struct intel_atomic_state *state); |
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| 66 | |
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| 67 | #define to_intel_dbuf_state(x) container_of((x), struct intel_dbuf_state, base) |
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| 68 | #define intel_atomic_get_old_dbuf_state(state) \ |
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| 69 | to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->display.dbuf.obj)) |
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| 70 | #define intel_atomic_get_new_dbuf_state(state) \ |
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| 71 | to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display.dbuf.obj)) |
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| 72 | |
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| 73 | int intel_dbuf_init(struct drm_i915_private *i915); |
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| 74 | void intel_dbuf_pre_plane_update(struct intel_atomic_state *state); |
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| 75 | void intel_dbuf_post_plane_update(struct intel_atomic_state *state); |
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| 76 | void intel_mbus_dbox_update(struct intel_atomic_state *state); |
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| 77 | |
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| 78 | #endif /* __SKL_WATERMARK_H__ */ |
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| 79 | |
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| 80 | |
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