1/*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Kevin Tian <kevin.tian@intel.com>
25 *
26 * Contributors:
27 * Bing Niu <bing.niu@intel.com>
28 * Xu Han <xu.han@intel.com>
29 * Ping Gao <ping.a.gao@intel.com>
30 * Xiaoguang Chen <xiaoguang.chen@intel.com>
31 * Yang Liu <yang2.liu@intel.com>
32 * Tina Zhang <tina.zhang@intel.com>
33 *
34 */
35
36#include <uapi/drm/drm_fourcc.h>
37#include "i915_drv.h"
38#include "gvt.h"
39#include "i915_pvinfo.h"
40#include "i915_reg.h"
41
42#define PRIMARY_FORMAT_NUM 16
43struct pixel_format {
44 int drm_format; /* Pixel format in DRM definition */
45 int bpp; /* Bits per pixel, 0 indicates invalid */
46 const char *desc; /* The description */
47};
48
49static const struct pixel_format bdw_pixel_formats[] = {
50 {DRM_FORMAT_C8, 8, "8-bit Indexed"},
51 {DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
52 {DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
53 {DRM_FORMAT_XBGR2101010, 32, "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"},
54
55 {DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"},
56 {DRM_FORMAT_XBGR8888, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"},
57
58 /* non-supported format has bpp default to 0 */
59 {}
60};
61
62static const struct pixel_format skl_pixel_formats[] = {
63 {DRM_FORMAT_YUYV, 16, "16-bit packed YUYV (8:8:8:8 MSB-V:Y2:U:Y1)"},
64 {DRM_FORMAT_UYVY, 16, "16-bit packed UYVY (8:8:8:8 MSB-Y2:V:Y1:U)"},
65 {DRM_FORMAT_YVYU, 16, "16-bit packed YVYU (8:8:8:8 MSB-U:Y2:V:Y1)"},
66 {DRM_FORMAT_VYUY, 16, "16-bit packed VYUY (8:8:8:8 MSB-Y2:U:Y1:V)"},
67
68 {DRM_FORMAT_C8, 8, "8-bit Indexed"},
69 {DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
70 {DRM_FORMAT_ABGR8888, 32, "32-bit RGBA (8:8:8:8 MSB-A:B:G:R)"},
71 {DRM_FORMAT_XBGR8888, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"},
72
73 {DRM_FORMAT_ARGB8888, 32, "32-bit BGRA (8:8:8:8 MSB-A:R:G:B)"},
74 {DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
75 {DRM_FORMAT_XBGR2101010, 32, "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"},
76 {DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"},
77
78 /* non-supported format has bpp default to 0 */
79 {}
80};
81
82static int bdw_format_to_drm(int format)
83{
84 int bdw_pixel_formats_index = 6;
85
86 switch (format) {
87 case DISP_FORMAT_8BPP:
88 bdw_pixel_formats_index = 0;
89 break;
90 case DISP_FORMAT_BGRX565:
91 bdw_pixel_formats_index = 1;
92 break;
93 case DISP_FORMAT_BGRX888:
94 bdw_pixel_formats_index = 2;
95 break;
96 case DISP_FORMAT_RGBX101010:
97 bdw_pixel_formats_index = 3;
98 break;
99 case DISP_FORMAT_BGRX101010:
100 bdw_pixel_formats_index = 4;
101 break;
102 case DISP_FORMAT_RGBX888:
103 bdw_pixel_formats_index = 5;
104 break;
105
106 default:
107 break;
108 }
109
110 return bdw_pixel_formats_index;
111}
112
113static int skl_format_to_drm(int format, bool rgb_order, bool alpha,
114 int yuv_order)
115{
116 int skl_pixel_formats_index = 12;
117
118 switch (format) {
119 case PLANE_CTL_FORMAT_INDEXED:
120 skl_pixel_formats_index = 4;
121 break;
122 case PLANE_CTL_FORMAT_RGB_565:
123 skl_pixel_formats_index = 5;
124 break;
125 case PLANE_CTL_FORMAT_XRGB_8888:
126 if (rgb_order)
127 skl_pixel_formats_index = alpha ? 6 : 7;
128 else
129 skl_pixel_formats_index = alpha ? 8 : 9;
130 break;
131 case PLANE_CTL_FORMAT_XRGB_2101010:
132 skl_pixel_formats_index = rgb_order ? 10 : 11;
133 break;
134 case PLANE_CTL_FORMAT_YUV422:
135 skl_pixel_formats_index = yuv_order >> 16;
136 if (skl_pixel_formats_index > 3)
137 return -EINVAL;
138 break;
139
140 default:
141 break;
142 }
143
144 return skl_pixel_formats_index;
145}
146
147static u32 intel_vgpu_get_stride(struct intel_vgpu *vgpu, int pipe,
148 u32 tiled, int stride_mask, int bpp)
149{
150 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
151
152 u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(pipe)) & stride_mask;
153 u32 stride = stride_reg;
154
155 if (GRAPHICS_VER(dev_priv) >= 9) {
156 switch (tiled) {
157 case PLANE_CTL_TILED_LINEAR:
158 stride = stride_reg * 64;
159 break;
160 case PLANE_CTL_TILED_X:
161 stride = stride_reg * 512;
162 break;
163 case PLANE_CTL_TILED_Y:
164 stride = stride_reg * 128;
165 break;
166 case PLANE_CTL_TILED_YF:
167 if (bpp == 8)
168 stride = stride_reg * 64;
169 else if (bpp == 16 || bpp == 32 || bpp == 64)
170 stride = stride_reg * 128;
171 else
172 gvt_dbg_core("skl: unsupported bpp:%d\n", bpp);
173 break;
174 default:
175 gvt_dbg_core("skl: unsupported tile format:%x\n",
176 tiled);
177 }
178 }
179
180 return stride;
181}
182
183static int get_active_pipe(struct intel_vgpu *vgpu)
184{
185 int i;
186
187 for (i = 0; i < I915_MAX_PIPES; i++)
188 if (pipe_is_enabled(vgpu, pipe: i))
189 break;
190
191 return i;
192}
193
194/**
195 * intel_vgpu_decode_primary_plane - Decode primary plane
196 * @vgpu: input vgpu
197 * @plane: primary plane to save decoded info
198 * This function is called for decoding plane
199 *
200 * Returns:
201 * 0 on success, non-zero if failed.
202 */
203int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
204 struct intel_vgpu_primary_plane_format *plane)
205{
206 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
207 u32 val, fmt;
208 int pipe;
209
210 pipe = get_active_pipe(vgpu);
211 if (pipe >= I915_MAX_PIPES)
212 return -ENODEV;
213
214 val = vgpu_vreg_t(vgpu, DSPCNTR(pipe));
215 plane->enabled = !!(val & DISP_ENABLE);
216 if (!plane->enabled)
217 return -ENODEV;
218
219 if (GRAPHICS_VER(dev_priv) >= 9) {
220 plane->tiled = val & PLANE_CTL_TILED_MASK;
221 fmt = skl_format_to_drm(
222 format: val & PLANE_CTL_FORMAT_MASK_SKL,
223 rgb_order: val & PLANE_CTL_ORDER_RGBX,
224 alpha: val & PLANE_CTL_ALPHA_MASK,
225 yuv_order: val & PLANE_CTL_YUV422_ORDER_MASK);
226
227 if (fmt >= ARRAY_SIZE(skl_pixel_formats)) {
228 gvt_vgpu_err("Out-of-bounds pixel format index\n");
229 return -EINVAL;
230 }
231
232 plane->bpp = skl_pixel_formats[fmt].bpp;
233 plane->drm_format = skl_pixel_formats[fmt].drm_format;
234 } else {
235 plane->tiled = val & DISP_TILED;
236 fmt = bdw_format_to_drm(format: val & DISP_FORMAT_MASK);
237 plane->bpp = bdw_pixel_formats[fmt].bpp;
238 plane->drm_format = bdw_pixel_formats[fmt].drm_format;
239 }
240
241 if (!plane->bpp) {
242 gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt);
243 return -EINVAL;
244 }
245
246 plane->hw_format = fmt;
247
248 plane->base = vgpu_vreg_t(vgpu, DSPSURF(pipe)) & I915_GTT_PAGE_MASK;
249 if (!vgpu_gmadr_is_valid(vgpu, plane->base))
250 return -EINVAL;
251
252 plane->base_gpa = intel_vgpu_gma_to_gpa(mm: vgpu->gtt.ggtt_mm, gma: plane->base);
253 if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {
254 gvt_vgpu_err("Translate primary plane gma 0x%x to gpa fail\n",
255 plane->base);
256 return -EINVAL;
257 }
258
259 plane->stride = intel_vgpu_get_stride(vgpu, pipe, tiled: plane->tiled,
260 stride_mask: (GRAPHICS_VER(dev_priv) >= 9) ?
261 (_PRI_PLANE_STRIDE_MASK >> 6) :
262 _PRI_PLANE_STRIDE_MASK, bpp: plane->bpp);
263
264 plane->width = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) & _PIPE_H_SRCSZ_MASK) >>
265 _PIPE_H_SRCSZ_SHIFT;
266 plane->width += 1;
267 plane->height = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) &
268 _PIPE_V_SRCSZ_MASK) >> _PIPE_V_SRCSZ_SHIFT;
269 plane->height += 1; /* raw height is one minus the real value */
270
271 val = vgpu_vreg_t(vgpu, DSPTILEOFF(pipe));
272 plane->x_offset = (val & _PRI_PLANE_X_OFF_MASK) >>
273 _PRI_PLANE_X_OFF_SHIFT;
274 plane->y_offset = (val & _PRI_PLANE_Y_OFF_MASK) >>
275 _PRI_PLANE_Y_OFF_SHIFT;
276
277 return 0;
278}
279
280#define CURSOR_FORMAT_NUM (1 << 6)
281struct cursor_mode_format {
282 int drm_format; /* Pixel format in DRM definition */
283 u8 bpp; /* Bits per pixel; 0 indicates invalid */
284 u32 width; /* In pixel */
285 u32 height; /* In lines */
286 const char *desc; /* The description */
287};
288
289static const struct cursor_mode_format cursor_pixel_formats[] = {
290 {DRM_FORMAT_ARGB8888, 32, 128, 128, "128x128 32bpp ARGB"},
291 {DRM_FORMAT_ARGB8888, 32, 256, 256, "256x256 32bpp ARGB"},
292 {DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"},
293 {DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"},
294
295 /* non-supported format has bpp default to 0 */
296 {}
297};
298
299static int cursor_mode_to_drm(int mode)
300{
301 int cursor_pixel_formats_index = 4;
302
303 switch (mode) {
304 case MCURSOR_MODE_128_ARGB_AX:
305 cursor_pixel_formats_index = 0;
306 break;
307 case MCURSOR_MODE_256_ARGB_AX:
308 cursor_pixel_formats_index = 1;
309 break;
310 case MCURSOR_MODE_64_ARGB_AX:
311 cursor_pixel_formats_index = 2;
312 break;
313 case MCURSOR_MODE_64_32B_AX:
314 cursor_pixel_formats_index = 3;
315 break;
316
317 default:
318 break;
319 }
320
321 return cursor_pixel_formats_index;
322}
323
324/**
325 * intel_vgpu_decode_cursor_plane - Decode sprite plane
326 * @vgpu: input vgpu
327 * @plane: cursor plane to save decoded info
328 * This function is called for decoding plane
329 *
330 * Returns:
331 * 0 on success, non-zero if failed.
332 */
333int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu,
334 struct intel_vgpu_cursor_plane_format *plane)
335{
336 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
337 u32 val, mode, index;
338 u32 alpha_plane, alpha_force;
339 int pipe;
340
341 pipe = get_active_pipe(vgpu);
342 if (pipe >= I915_MAX_PIPES)
343 return -ENODEV;
344
345 val = vgpu_vreg_t(vgpu, CURCNTR(pipe));
346 mode = val & MCURSOR_MODE_MASK;
347 plane->enabled = (mode != MCURSOR_MODE_DISABLE);
348 if (!plane->enabled)
349 return -ENODEV;
350
351 index = cursor_mode_to_drm(mode);
352
353 if (!cursor_pixel_formats[index].bpp) {
354 gvt_vgpu_err("Non-supported cursor mode (0x%x)\n", mode);
355 return -EINVAL;
356 }
357 plane->mode = mode;
358 plane->bpp = cursor_pixel_formats[index].bpp;
359 plane->drm_format = cursor_pixel_formats[index].drm_format;
360 plane->width = cursor_pixel_formats[index].width;
361 plane->height = cursor_pixel_formats[index].height;
362
363 alpha_plane = (val & _CURSOR_ALPHA_PLANE_MASK) >>
364 _CURSOR_ALPHA_PLANE_SHIFT;
365 alpha_force = (val & _CURSOR_ALPHA_FORCE_MASK) >>
366 _CURSOR_ALPHA_FORCE_SHIFT;
367 if (alpha_plane || alpha_force)
368 gvt_dbg_core("alpha_plane=0x%x, alpha_force=0x%x\n",
369 alpha_plane, alpha_force);
370
371 plane->base = vgpu_vreg_t(vgpu, CURBASE(pipe)) & I915_GTT_PAGE_MASK;
372 if (!vgpu_gmadr_is_valid(vgpu, plane->base))
373 return -EINVAL;
374
375 plane->base_gpa = intel_vgpu_gma_to_gpa(mm: vgpu->gtt.ggtt_mm, gma: plane->base);
376 if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {
377 gvt_vgpu_err("Translate cursor plane gma 0x%x to gpa fail\n",
378 plane->base);
379 return -EINVAL;
380 }
381
382 val = vgpu_vreg_t(vgpu, CURPOS(pipe));
383 plane->x_pos = (val & _CURSOR_POS_X_MASK) >> _CURSOR_POS_X_SHIFT;
384 plane->x_sign = (val & _CURSOR_SIGN_X_MASK) >> _CURSOR_SIGN_X_SHIFT;
385 plane->y_pos = (val & _CURSOR_POS_Y_MASK) >> _CURSOR_POS_Y_SHIFT;
386 plane->y_sign = (val & _CURSOR_SIGN_Y_MASK) >> _CURSOR_SIGN_Y_SHIFT;
387
388 plane->x_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot));
389 plane->y_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot));
390 return 0;
391}
392
393#define SPRITE_FORMAT_NUM (1 << 3)
394
395static const struct pixel_format sprite_pixel_formats[SPRITE_FORMAT_NUM] = {
396 [0x0] = {DRM_FORMAT_YUV422, 16, "YUV 16-bit 4:2:2 packed"},
397 [0x1] = {DRM_FORMAT_XRGB2101010, 32, "RGB 32-bit 2:10:10:10"},
398 [0x2] = {DRM_FORMAT_XRGB8888, 32, "RGB 32-bit 8:8:8:8"},
399 [0x4] = {DRM_FORMAT_AYUV, 32,
400 "YUV 32-bit 4:4:4 packed (8:8:8:8 MSB-X:Y:U:V)"},
401};
402
403/**
404 * intel_vgpu_decode_sprite_plane - Decode sprite plane
405 * @vgpu: input vgpu
406 * @plane: sprite plane to save decoded info
407 * This function is called for decoding plane
408 *
409 * Returns:
410 * 0 on success, non-zero if failed.
411 */
412int intel_vgpu_decode_sprite_plane(struct intel_vgpu *vgpu,
413 struct intel_vgpu_sprite_plane_format *plane)
414{
415 u32 val, fmt;
416 u32 color_order, yuv_order;
417 int drm_format;
418 int pipe;
419
420 pipe = get_active_pipe(vgpu);
421 if (pipe >= I915_MAX_PIPES)
422 return -ENODEV;
423
424 val = vgpu_vreg_t(vgpu, SPRCTL(pipe));
425 plane->enabled = !!(val & SPRITE_ENABLE);
426 if (!plane->enabled)
427 return -ENODEV;
428
429 plane->tiled = !!(val & SPRITE_TILED);
430 color_order = !!(val & SPRITE_RGB_ORDER_RGBX);
431 yuv_order = (val & SPRITE_YUV_ORDER_MASK) >>
432 _SPRITE_YUV_ORDER_SHIFT;
433
434 fmt = (val & SPRITE_FORMAT_MASK) >> _SPRITE_FMT_SHIFT;
435 if (!sprite_pixel_formats[fmt].bpp) {
436 gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt);
437 return -EINVAL;
438 }
439 plane->hw_format = fmt;
440 plane->bpp = sprite_pixel_formats[fmt].bpp;
441 drm_format = sprite_pixel_formats[fmt].drm_format;
442
443 /* Order of RGB values in an RGBxxx buffer may be ordered RGB or
444 * BGR depending on the state of the color_order field
445 */
446 if (!color_order) {
447 if (drm_format == DRM_FORMAT_XRGB2101010)
448 drm_format = DRM_FORMAT_XBGR2101010;
449 else if (drm_format == DRM_FORMAT_XRGB8888)
450 drm_format = DRM_FORMAT_XBGR8888;
451 }
452
453 if (drm_format == DRM_FORMAT_YUV422) {
454 switch (yuv_order) {
455 case 0:
456 drm_format = DRM_FORMAT_YUYV;
457 break;
458 case 1:
459 drm_format = DRM_FORMAT_UYVY;
460 break;
461 case 2:
462 drm_format = DRM_FORMAT_YVYU;
463 break;
464 case 3:
465 drm_format = DRM_FORMAT_VYUY;
466 break;
467 default:
468 /* yuv_order has only 2 bits */
469 break;
470 }
471 }
472
473 plane->drm_format = drm_format;
474
475 plane->base = vgpu_vreg_t(vgpu, SPRSURF(pipe)) & I915_GTT_PAGE_MASK;
476 if (!vgpu_gmadr_is_valid(vgpu, plane->base))
477 return -EINVAL;
478
479 plane->base_gpa = intel_vgpu_gma_to_gpa(mm: vgpu->gtt.ggtt_mm, gma: plane->base);
480 if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {
481 gvt_vgpu_err("Translate sprite plane gma 0x%x to gpa fail\n",
482 plane->base);
483 return -EINVAL;
484 }
485
486 plane->stride = vgpu_vreg_t(vgpu, SPRSTRIDE(pipe)) &
487 _SPRITE_STRIDE_MASK;
488
489 val = vgpu_vreg_t(vgpu, SPRSIZE(pipe));
490 plane->height = (val & _SPRITE_SIZE_HEIGHT_MASK) >>
491 _SPRITE_SIZE_HEIGHT_SHIFT;
492 plane->width = (val & _SPRITE_SIZE_WIDTH_MASK) >>
493 _SPRITE_SIZE_WIDTH_SHIFT;
494 plane->height += 1; /* raw height is one minus the real value */
495 plane->width += 1; /* raw width is one minus the real value */
496
497 val = vgpu_vreg_t(vgpu, SPRPOS(pipe));
498 plane->x_pos = (val & _SPRITE_POS_X_MASK) >> _SPRITE_POS_X_SHIFT;
499 plane->y_pos = (val & _SPRITE_POS_Y_MASK) >> _SPRITE_POS_Y_SHIFT;
500
501 val = vgpu_vreg_t(vgpu, SPROFFSET(pipe));
502 plane->x_offset = (val & _SPRITE_OFFSET_START_X_MASK) >>
503 _SPRITE_OFFSET_START_X_SHIFT;
504 plane->y_offset = (val & _SPRITE_OFFSET_START_Y_MASK) >>
505 _SPRITE_OFFSET_START_Y_SHIFT;
506
507 return 0;
508}
509

source code of linux/drivers/gpu/drm/i915/gvt/fb_decoder.c