| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | /* |
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| 3 | * Copyright © 2019 Intel Corporation |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __I915_IRQ_H__ |
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| 7 | #define __I915_IRQ_H__ |
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| 8 | |
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| 9 | #include <linux/ktime.h> |
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| 10 | #include <linux/types.h> |
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| 11 | |
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| 12 | #include "i915_reg_defs.h" |
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| 13 | |
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| 14 | enum pipe; |
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| 15 | struct drm_crtc; |
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| 16 | struct drm_device; |
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| 17 | struct drm_display_mode; |
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| 18 | struct drm_i915_private; |
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| 19 | struct intel_crtc; |
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| 20 | struct intel_encoder; |
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| 21 | struct intel_uncore; |
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| 22 | |
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| 23 | void intel_irq_init(struct drm_i915_private *dev_priv); |
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| 24 | void intel_irq_fini(struct drm_i915_private *dev_priv); |
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| 25 | int intel_irq_install(struct drm_i915_private *dev_priv); |
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| 26 | void intel_irq_uninstall(struct drm_i915_private *dev_priv); |
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| 27 | |
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| 28 | void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, u32 mask); |
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| 29 | void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, u32 mask); |
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| 30 | void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv); |
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| 31 | void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv); |
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| 32 | void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv); |
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| 33 | void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv); |
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| 34 | void gen6_rps_reset_ei(struct drm_i915_private *dev_priv); |
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| 35 | u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915, u32 mask); |
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| 36 | |
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| 37 | void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv); |
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| 38 | void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv); |
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| 39 | bool intel_irqs_enabled(struct drm_i915_private *dev_priv); |
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| 40 | void intel_synchronize_irq(struct drm_i915_private *i915); |
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| 41 | void intel_synchronize_hardirq(struct drm_i915_private *i915); |
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| 42 | |
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| 43 | void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg); |
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| 44 | |
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| 45 | void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr, |
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| 46 | i915_reg_t iir, i915_reg_t ier); |
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| 47 | |
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| 48 | void gen3_irq_init(struct intel_uncore *uncore, |
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| 49 | i915_reg_t imr, u32 imr_val, |
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| 50 | i915_reg_t ier, u32 ier_val, |
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| 51 | i915_reg_t iir); |
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| 52 | |
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| 53 | #define GEN8_IRQ_RESET_NDX(uncore, type, which) \ |
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| 54 | ({ \ |
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| 55 | unsigned int which_ = which; \ |
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| 56 | gen3_irq_reset((uncore), GEN8_##type##_IMR(which_), \ |
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| 57 | GEN8_##type##_IIR(which_), GEN8_##type##_IER(which_)); \ |
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| 58 | }) |
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| 59 | |
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| 60 | #define GEN3_IRQ_RESET(uncore, type) \ |
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| 61 | gen3_irq_reset((uncore), type##IMR, type##IIR, type##IER) |
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| 62 | |
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| 63 | #define GEN8_IRQ_INIT_NDX(uncore, type, which, imr_val, ier_val) \ |
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| 64 | ({ \ |
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| 65 | unsigned int which_ = which; \ |
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| 66 | gen3_irq_init((uncore), \ |
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| 67 | GEN8_##type##_IMR(which_), imr_val, \ |
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| 68 | GEN8_##type##_IER(which_), ier_val, \ |
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| 69 | GEN8_##type##_IIR(which_)); \ |
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| 70 | }) |
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| 71 | |
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| 72 | #define GEN3_IRQ_INIT(uncore, type, imr_val, ier_val) \ |
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| 73 | gen3_irq_init((uncore), \ |
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| 74 | type##IMR, imr_val, \ |
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| 75 | type##IER, ier_val, \ |
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| 76 | type##IIR) |
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| 77 | |
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| 78 | #endif /* __I915_IRQ_H__ */ |
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| 79 | |
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