1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include <linux/delay.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28#include <linux/pm_runtime.h>
29#include <linux/vga_switcheroo.h>
30#include <linux/mmu_notifier.h>
31#include <linux/dynamic_debug.h>
32
33#include <drm/drm_aperture.h>
34#include <drm/drm_drv.h>
35#include <drm/drm_fbdev_generic.h>
36#include <drm/drm_gem_ttm_helper.h>
37#include <drm/drm_ioctl.h>
38#include <drm/drm_vblank.h>
39
40#include <core/gpuobj.h>
41#include <core/option.h>
42#include <core/pci.h>
43#include <core/tegra.h>
44
45#include <nvif/driver.h>
46#include <nvif/fifo.h>
47#include <nvif/push006c.h>
48#include <nvif/user.h>
49
50#include <nvif/class.h>
51#include <nvif/cl0002.h>
52
53#include "nouveau_drv.h"
54#include "nouveau_dma.h"
55#include "nouveau_ttm.h"
56#include "nouveau_gem.h"
57#include "nouveau_vga.h"
58#include "nouveau_led.h"
59#include "nouveau_hwmon.h"
60#include "nouveau_acpi.h"
61#include "nouveau_bios.h"
62#include "nouveau_ioctl.h"
63#include "nouveau_abi16.h"
64#include "nouveau_fence.h"
65#include "nouveau_debugfs.h"
66#include "nouveau_usif.h"
67#include "nouveau_connector.h"
68#include "nouveau_platform.h"
69#include "nouveau_svm.h"
70#include "nouveau_dmem.h"
71#include "nouveau_exec.h"
72#include "nouveau_uvmm.h"
73#include "nouveau_sched.h"
74
75DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0,
76 "DRM_UT_CORE",
77 "DRM_UT_DRIVER",
78 "DRM_UT_KMS",
79 "DRM_UT_PRIME",
80 "DRM_UT_ATOMIC",
81 "DRM_UT_VBL",
82 "DRM_UT_STATE",
83 "DRM_UT_LEASE",
84 "DRM_UT_DP",
85 "DRM_UT_DRMRES");
86
87MODULE_PARM_DESC(config, "option string to pass to driver core");
88static char *nouveau_config;
89module_param_named(config, nouveau_config, charp, 0400);
90
91MODULE_PARM_DESC(debug, "debug string to pass to driver core");
92static char *nouveau_debug;
93module_param_named(debug, nouveau_debug, charp, 0400);
94
95MODULE_PARM_DESC(noaccel, "disable kernel/abi16 acceleration");
96static int nouveau_noaccel = 0;
97module_param_named(noaccel, nouveau_noaccel, int, 0400);
98
99MODULE_PARM_DESC(modeset, "enable driver (default: auto, "
100 "0 = disabled, 1 = enabled, 2 = headless)");
101int nouveau_modeset = -1;
102module_param_named(modeset, nouveau_modeset, int, 0400);
103
104MODULE_PARM_DESC(atomic, "Expose atomic ioctl (default: disabled)");
105static int nouveau_atomic = 0;
106module_param_named(atomic, nouveau_atomic, int, 0400);
107
108MODULE_PARM_DESC(runpm, "disable (0), force enable (1), optimus only default (-1)");
109static int nouveau_runtime_pm = -1;
110module_param_named(runpm, nouveau_runtime_pm, int, 0400);
111
112static struct drm_driver driver_stub;
113static struct drm_driver driver_pci;
114static struct drm_driver driver_platform;
115
116static u64
117nouveau_pci_name(struct pci_dev *pdev)
118{
119 u64 name = (u64)pci_domain_nr(bus: pdev->bus) << 32;
120 name |= pdev->bus->number << 16;
121 name |= PCI_SLOT(pdev->devfn) << 8;
122 return name | PCI_FUNC(pdev->devfn);
123}
124
125static u64
126nouveau_platform_name(struct platform_device *platformdev)
127{
128 return platformdev->id;
129}
130
131static u64
132nouveau_name(struct drm_device *dev)
133{
134 if (dev_is_pci(dev->dev))
135 return nouveau_pci_name(to_pci_dev(dev->dev));
136 else
137 return nouveau_platform_name(platformdev: to_platform_device(dev->dev));
138}
139
140static inline bool
141nouveau_cli_work_ready(struct dma_fence *fence)
142{
143 bool ret = true;
144
145 spin_lock_irq(lock: fence->lock);
146 if (!dma_fence_is_signaled_locked(fence))
147 ret = false;
148 spin_unlock_irq(lock: fence->lock);
149
150 if (ret == true)
151 dma_fence_put(fence);
152 return ret;
153}
154
155static void
156nouveau_cli_work(struct work_struct *w)
157{
158 struct nouveau_cli *cli = container_of(w, typeof(*cli), work);
159 struct nouveau_cli_work *work, *wtmp;
160 mutex_lock(&cli->lock);
161 list_for_each_entry_safe(work, wtmp, &cli->worker, head) {
162 if (!work->fence || nouveau_cli_work_ready(fence: work->fence)) {
163 list_del(entry: &work->head);
164 work->func(work);
165 }
166 }
167 mutex_unlock(lock: &cli->lock);
168}
169
170static void
171nouveau_cli_work_fence(struct dma_fence *fence, struct dma_fence_cb *cb)
172{
173 struct nouveau_cli_work *work = container_of(cb, typeof(*work), cb);
174 schedule_work(work: &work->cli->work);
175}
176
177void
178nouveau_cli_work_queue(struct nouveau_cli *cli, struct dma_fence *fence,
179 struct nouveau_cli_work *work)
180{
181 work->fence = dma_fence_get(fence);
182 work->cli = cli;
183 mutex_lock(&cli->lock);
184 list_add_tail(new: &work->head, head: &cli->worker);
185 if (dma_fence_add_callback(fence, cb: &work->cb, func: nouveau_cli_work_fence))
186 nouveau_cli_work_fence(fence, cb: &work->cb);
187 mutex_unlock(lock: &cli->lock);
188}
189
190static void
191nouveau_cli_fini(struct nouveau_cli *cli)
192{
193 /* All our channels are dead now, which means all the fences they
194 * own are signalled, and all callback functions have been called.
195 *
196 * So, after flushing the workqueue, there should be nothing left.
197 */
198 flush_work(work: &cli->work);
199 WARN_ON(!list_empty(&cli->worker));
200
201 usif_client_fini(cli);
202 nouveau_uvmm_fini(uvmm: &cli->uvmm);
203 nouveau_sched_entity_fini(entity: &cli->sched_entity);
204 nouveau_vmm_fini(&cli->svm);
205 nouveau_vmm_fini(&cli->vmm);
206 nvif_mmu_dtor(&cli->mmu);
207 nvif_device_dtor(&cli->device);
208 mutex_lock(&cli->drm->master.lock);
209 nvif_client_dtor(&cli->base);
210 mutex_unlock(lock: &cli->drm->master.lock);
211}
212
213static int
214nouveau_cli_init(struct nouveau_drm *drm, const char *sname,
215 struct nouveau_cli *cli)
216{
217 static const struct nvif_mclass
218 mems[] = {
219 { NVIF_CLASS_MEM_GF100, -1 },
220 { NVIF_CLASS_MEM_NV50 , -1 },
221 { NVIF_CLASS_MEM_NV04 , -1 },
222 {}
223 };
224 static const struct nvif_mclass
225 mmus[] = {
226 { NVIF_CLASS_MMU_GF100, -1 },
227 { NVIF_CLASS_MMU_NV50 , -1 },
228 { NVIF_CLASS_MMU_NV04 , -1 },
229 {}
230 };
231 static const struct nvif_mclass
232 vmms[] = {
233 { NVIF_CLASS_VMM_GP100, -1 },
234 { NVIF_CLASS_VMM_GM200, -1 },
235 { NVIF_CLASS_VMM_GF100, -1 },
236 { NVIF_CLASS_VMM_NV50 , -1 },
237 { NVIF_CLASS_VMM_NV04 , -1 },
238 {}
239 };
240 u64 device = nouveau_name(dev: drm->dev);
241 int ret;
242
243 snprintf(buf: cli->name, size: sizeof(cli->name), fmt: "%s", sname);
244 cli->drm = drm;
245 mutex_init(&cli->mutex);
246 usif_client_init(cli);
247
248 INIT_WORK(&cli->work, nouveau_cli_work);
249 INIT_LIST_HEAD(list: &cli->worker);
250 mutex_init(&cli->lock);
251
252 if (cli == &drm->master) {
253 ret = nvif_driver_init(NULL, nouveau_config, nouveau_debug,
254 cli->name, device, &cli->base);
255 } else {
256 mutex_lock(&drm->master.lock);
257 ret = nvif_client_ctor(&drm->master.base, cli->name, device,
258 &cli->base);
259 mutex_unlock(lock: &drm->master.lock);
260 }
261 if (ret) {
262 NV_PRINTK(err, cli, "Client allocation failed: %d\n", ret);
263 goto done;
264 }
265
266 ret = nvif_device_ctor(&cli->base.object, "drmDevice", 0, NV_DEVICE,
267 &(struct nv_device_v0) {
268 .device = ~0,
269 .priv = true,
270 }, sizeof(struct nv_device_v0),
271 &cli->device);
272 if (ret) {
273 NV_PRINTK(err, cli, "Device allocation failed: %d\n", ret);
274 goto done;
275 }
276
277 ret = nvif_mclass(&cli->device.object, mmus);
278 if (ret < 0) {
279 NV_PRINTK(err, cli, "No supported MMU class\n");
280 goto done;
281 }
282
283 ret = nvif_mmu_ctor(&cli->device.object, "drmMmu", mmus[ret].oclass,
284 &cli->mmu);
285 if (ret) {
286 NV_PRINTK(err, cli, "MMU allocation failed: %d\n", ret);
287 goto done;
288 }
289
290 ret = nvif_mclass(&cli->mmu.object, vmms);
291 if (ret < 0) {
292 NV_PRINTK(err, cli, "No supported VMM class\n");
293 goto done;
294 }
295
296 ret = nouveau_vmm_init(cli, oclass: vmms[ret].oclass, &cli->vmm);
297 if (ret) {
298 NV_PRINTK(err, cli, "VMM allocation failed: %d\n", ret);
299 goto done;
300 }
301
302 ret = nvif_mclass(&cli->mmu.object, mems);
303 if (ret < 0) {
304 NV_PRINTK(err, cli, "No supported MEM class\n");
305 goto done;
306 }
307
308 cli->mem = &mems[ret];
309
310 ret = nouveau_sched_entity_init(entity: &cli->sched_entity, sched: &drm->sched,
311 sched_wq: drm->sched_wq);
312 if (ret)
313 goto done;
314
315 return 0;
316done:
317 if (ret)
318 nouveau_cli_fini(cli);
319 return ret;
320}
321
322static void
323nouveau_accel_ce_fini(struct nouveau_drm *drm)
324{
325 nouveau_channel_idle(drm->cechan);
326 nvif_object_dtor(&drm->ttm.copy);
327 nouveau_channel_del(&drm->cechan);
328}
329
330static void
331nouveau_accel_ce_init(struct nouveau_drm *drm)
332{
333 struct nvif_device *device = &drm->client.device;
334 u64 runm;
335 int ret = 0;
336
337 /* Allocate channel that has access to a (preferably async) copy
338 * engine, to use for TTM buffer moves.
339 */
340 runm = nvif_fifo_runlist_ce(device);
341 if (!runm) {
342 NV_DEBUG(drm, "no ce runlist\n");
343 return;
344 }
345
346 ret = nouveau_channel_new(drm, device, priv: false, runm, vram: NvDmaFB, gart: NvDmaTT, &drm->cechan);
347 if (ret)
348 NV_ERROR(drm, "failed to create ce channel, %d\n", ret);
349}
350
351static void
352nouveau_accel_gr_fini(struct nouveau_drm *drm)
353{
354 nouveau_channel_idle(drm->channel);
355 nvif_object_dtor(&drm->ntfy);
356 nvkm_gpuobj_del(&drm->notify);
357 nouveau_channel_del(&drm->channel);
358}
359
360static void
361nouveau_accel_gr_init(struct nouveau_drm *drm)
362{
363 struct nvif_device *device = &drm->client.device;
364 u64 runm;
365 int ret;
366
367 /* Allocate channel that has access to the graphics engine. */
368 runm = nvif_fifo_runlist(device, NV_DEVICE_HOST_RUNLIST_ENGINES_GR);
369 if (!runm) {
370 NV_DEBUG(drm, "no gr runlist\n");
371 return;
372 }
373
374 ret = nouveau_channel_new(drm, device, priv: false, runm, vram: NvDmaFB, gart: NvDmaTT, &drm->channel);
375 if (ret) {
376 NV_ERROR(drm, "failed to create kernel channel, %d\n", ret);
377 nouveau_accel_gr_fini(drm);
378 return;
379 }
380
381 /* A SW class is used on pre-NV50 HW to assist with handling the
382 * synchronisation of page flips, as well as to implement fences
383 * on TNT/TNT2 HW that lacks any kind of support in host.
384 */
385 if (!drm->channel->nvsw.client && device->info.family < NV_DEVICE_INFO_V0_TESLA) {
386 ret = nvif_object_ctor(&drm->channel->user, "drmNvsw",
387 NVDRM_NVSW, nouveau_abi16_swclass(drm),
388 NULL, 0, &drm->channel->nvsw);
389
390 if (ret == 0 && device->info.chipset >= 0x11) {
391 ret = nvif_object_ctor(&drm->channel->user, "drmBlit",
392 0x005f, 0x009f,
393 NULL, 0, &drm->channel->blit);
394 }
395
396 if (ret == 0) {
397 struct nvif_push *push = drm->channel->chan.push;
398 ret = PUSH_WAIT(push, 8);
399 if (ret == 0) {
400 if (device->info.chipset >= 0x11) {
401 PUSH_NVSQ(push, NV05F, 0x0000, drm->channel->blit.handle);
402 PUSH_NVSQ(push, NV09F, 0x0120, 0,
403 0x0124, 1,
404 0x0128, 2);
405 }
406 PUSH_NVSQ(push, NV_SW, 0x0000, drm->channel->nvsw.handle);
407 }
408 }
409
410 if (ret) {
411 NV_ERROR(drm, "failed to allocate sw or blit class, %d\n", ret);
412 nouveau_accel_gr_fini(drm);
413 return;
414 }
415 }
416
417 /* NvMemoryToMemoryFormat requires a notifier ctxdma for some reason,
418 * even if notification is never requested, so, allocate a ctxdma on
419 * any GPU where it's possible we'll end up using M2MF for BO moves.
420 */
421 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
422 ret = nvkm_gpuobj_new(nvxx_device(device), 32, 0, false, NULL,
423 &drm->notify);
424 if (ret) {
425 NV_ERROR(drm, "failed to allocate notifier, %d\n", ret);
426 nouveau_accel_gr_fini(drm);
427 return;
428 }
429
430 ret = nvif_object_ctor(&drm->channel->user, "drmM2mfNtfy",
431 NvNotify0, NV_DMA_IN_MEMORY,
432 &(struct nv_dma_v0) {
433 .target = NV_DMA_V0_TARGET_VRAM,
434 .access = NV_DMA_V0_ACCESS_RDWR,
435 .start = drm->notify->addr,
436 .limit = drm->notify->addr + 31
437 }, sizeof(struct nv_dma_v0),
438 &drm->ntfy);
439 if (ret) {
440 nouveau_accel_gr_fini(drm);
441 return;
442 }
443 }
444}
445
446static void
447nouveau_accel_fini(struct nouveau_drm *drm)
448{
449 nouveau_accel_ce_fini(drm);
450 nouveau_accel_gr_fini(drm);
451 if (drm->fence)
452 nouveau_fence(drm)->dtor(drm);
453 nouveau_channels_fini(drm);
454}
455
456static void
457nouveau_accel_init(struct nouveau_drm *drm)
458{
459 struct nvif_device *device = &drm->client.device;
460 struct nvif_sclass *sclass;
461 int ret, i, n;
462
463 if (nouveau_noaccel)
464 return;
465
466 /* Initialise global support for channels, and synchronisation. */
467 ret = nouveau_channels_init(drm);
468 if (ret)
469 return;
470
471 /*XXX: this is crap, but the fence/channel stuff is a little
472 * backwards in some places. this will be fixed.
473 */
474 ret = n = nvif_object_sclass_get(&device->object, &sclass);
475 if (ret < 0)
476 return;
477
478 for (ret = -ENOSYS, i = 0; i < n; i++) {
479 switch (sclass[i].oclass) {
480 case NV03_CHANNEL_DMA:
481 ret = nv04_fence_create(drm);
482 break;
483 case NV10_CHANNEL_DMA:
484 ret = nv10_fence_create(drm);
485 break;
486 case NV17_CHANNEL_DMA:
487 case NV40_CHANNEL_DMA:
488 ret = nv17_fence_create(drm);
489 break;
490 case NV50_CHANNEL_GPFIFO:
491 ret = nv50_fence_create(drm);
492 break;
493 case G82_CHANNEL_GPFIFO:
494 ret = nv84_fence_create(drm);
495 break;
496 case FERMI_CHANNEL_GPFIFO:
497 case KEPLER_CHANNEL_GPFIFO_A:
498 case KEPLER_CHANNEL_GPFIFO_B:
499 case MAXWELL_CHANNEL_GPFIFO_A:
500 case PASCAL_CHANNEL_GPFIFO_A:
501 case VOLTA_CHANNEL_GPFIFO_A:
502 case TURING_CHANNEL_GPFIFO_A:
503 case AMPERE_CHANNEL_GPFIFO_A:
504 case AMPERE_CHANNEL_GPFIFO_B:
505 ret = nvc0_fence_create(drm);
506 break;
507 default:
508 break;
509 }
510 }
511
512 nvif_object_sclass_put(&sclass);
513 if (ret) {
514 NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret);
515 nouveau_accel_fini(drm);
516 return;
517 }
518
519 /* Volta requires access to a doorbell register for kickoff. */
520 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_VOLTA) {
521 ret = nvif_user_ctor(device, "drmUsermode");
522 if (ret)
523 return;
524 }
525
526 /* Allocate channels we need to support various functions. */
527 nouveau_accel_gr_init(drm);
528 nouveau_accel_ce_init(drm);
529
530 /* Initialise accelerated TTM buffer moves. */
531 nouveau_bo_move_init(drm);
532}
533
534static void __printf(2, 3)
535nouveau_drm_errorf(struct nvif_object *object, const char *fmt, ...)
536{
537 struct nouveau_drm *drm = container_of(object->parent, typeof(*drm), parent);
538 struct va_format vaf;
539 va_list va;
540
541 va_start(va, fmt);
542 vaf.fmt = fmt;
543 vaf.va = &va;
544 NV_ERROR(drm, "%pV", &vaf);
545 va_end(va);
546}
547
548static void __printf(2, 3)
549nouveau_drm_debugf(struct nvif_object *object, const char *fmt, ...)
550{
551 struct nouveau_drm *drm = container_of(object->parent, typeof(*drm), parent);
552 struct va_format vaf;
553 va_list va;
554
555 va_start(va, fmt);
556 vaf.fmt = fmt;
557 vaf.va = &va;
558 NV_DEBUG(drm, "%pV", &vaf);
559 va_end(va);
560}
561
562static const struct nvif_parent_func
563nouveau_parent = {
564 .debugf = nouveau_drm_debugf,
565 .errorf = nouveau_drm_errorf,
566};
567
568static int
569nouveau_drm_device_init(struct drm_device *dev)
570{
571 struct nouveau_drm *drm;
572 int ret;
573
574 if (!(drm = kzalloc(size: sizeof(*drm), GFP_KERNEL)))
575 return -ENOMEM;
576 dev->dev_private = drm;
577 drm->dev = dev;
578
579 nvif_parent_ctor(&nouveau_parent, &drm->parent);
580 drm->master.base.object.parent = &drm->parent;
581
582 ret = nouveau_sched_init(drm);
583 if (ret)
584 goto fail_alloc;
585
586 ret = nouveau_cli_init(drm, sname: "DRM-master", cli: &drm->master);
587 if (ret)
588 goto fail_sched;
589
590 ret = nouveau_cli_init(drm, sname: "DRM", cli: &drm->client);
591 if (ret)
592 goto fail_master;
593
594 nvxx_client(&drm->client.base)->debug =
595 nvkm_dbgopt(nouveau_debug, "DRM");
596
597 INIT_LIST_HEAD(list: &drm->clients);
598 mutex_init(&drm->clients_lock);
599 spin_lock_init(&drm->tile.lock);
600
601 /* workaround an odd issue on nvc1 by disabling the device's
602 * nosnoop capability. hopefully won't cause issues until a
603 * better fix is found - assuming there is one...
604 */
605 if (drm->client.device.info.chipset == 0xc1)
606 nvif_mask(&drm->client.device.object, 0x00088080, 0x00000800, 0x00000000);
607
608 nouveau_vga_init(drm);
609
610 ret = nouveau_ttm_init(drm);
611 if (ret)
612 goto fail_ttm;
613
614 ret = nouveau_bios_init(dev);
615 if (ret)
616 goto fail_bios;
617
618 nouveau_accel_init(drm);
619
620 ret = nouveau_display_create(dev);
621 if (ret)
622 goto fail_dispctor;
623
624 if (dev->mode_config.num_crtc) {
625 ret = nouveau_display_init(dev, false, false);
626 if (ret)
627 goto fail_dispinit;
628 }
629
630 nouveau_debugfs_init(drm);
631 nouveau_hwmon_init(dev);
632 nouveau_svm_init(drm);
633 nouveau_dmem_init(drm);
634 nouveau_led_init(dev);
635
636 if (nouveau_pmops_runtime()) {
637 pm_runtime_use_autosuspend(dev: dev->dev);
638 pm_runtime_set_autosuspend_delay(dev: dev->dev, delay: 5000);
639 pm_runtime_set_active(dev: dev->dev);
640 pm_runtime_allow(dev: dev->dev);
641 pm_runtime_mark_last_busy(dev: dev->dev);
642 pm_runtime_put(dev: dev->dev);
643 }
644
645 return 0;
646fail_dispinit:
647 nouveau_display_destroy(dev);
648fail_dispctor:
649 nouveau_accel_fini(drm);
650 nouveau_bios_takedown(dev);
651fail_bios:
652 nouveau_ttm_fini(drm);
653fail_ttm:
654 nouveau_vga_fini(drm);
655 nouveau_cli_fini(cli: &drm->client);
656fail_master:
657 nouveau_cli_fini(cli: &drm->master);
658fail_sched:
659 nouveau_sched_fini(drm);
660fail_alloc:
661 nvif_parent_dtor(&drm->parent);
662 kfree(objp: drm);
663 return ret;
664}
665
666static void
667nouveau_drm_device_fini(struct drm_device *dev)
668{
669 struct nouveau_cli *cli, *temp_cli;
670 struct nouveau_drm *drm = nouveau_drm(dev);
671
672 if (nouveau_pmops_runtime()) {
673 pm_runtime_get_sync(dev: dev->dev);
674 pm_runtime_forbid(dev: dev->dev);
675 }
676
677 nouveau_led_fini(dev);
678 nouveau_dmem_fini(drm);
679 nouveau_svm_fini(drm);
680 nouveau_hwmon_fini(dev);
681 nouveau_debugfs_fini(drm);
682
683 if (dev->mode_config.num_crtc)
684 nouveau_display_fini(dev, false, false);
685 nouveau_display_destroy(dev);
686
687 nouveau_accel_fini(drm);
688 nouveau_bios_takedown(dev);
689
690 nouveau_ttm_fini(drm);
691 nouveau_vga_fini(drm);
692
693 /*
694 * There may be existing clients from as-yet unclosed files. For now,
695 * clean them up here rather than deferring until the file is closed,
696 * but this likely not correct if we want to support hot-unplugging
697 * properly.
698 */
699 mutex_lock(&drm->clients_lock);
700 list_for_each_entry_safe(cli, temp_cli, &drm->clients, head) {
701 list_del(entry: &cli->head);
702 mutex_lock(&cli->mutex);
703 if (cli->abi16)
704 nouveau_abi16_fini(cli->abi16);
705 mutex_unlock(lock: &cli->mutex);
706 nouveau_cli_fini(cli);
707 kfree(objp: cli);
708 }
709 mutex_unlock(lock: &drm->clients_lock);
710
711 nouveau_sched_fini(drm);
712
713 nouveau_cli_fini(cli: &drm->client);
714 nouveau_cli_fini(cli: &drm->master);
715 nvif_parent_dtor(&drm->parent);
716 mutex_destroy(lock: &drm->clients_lock);
717 kfree(objp: drm);
718}
719
720/*
721 * On some Intel PCIe bridge controllers doing a
722 * D0 -> D3hot -> D3cold -> D0 sequence causes Nvidia GPUs to not reappear.
723 * Skipping the intermediate D3hot step seems to make it work again. This is
724 * probably caused by not meeting the expectation the involved AML code has
725 * when the GPU is put into D3hot state before invoking it.
726 *
727 * This leads to various manifestations of this issue:
728 * - AML code execution to power on the GPU hits an infinite loop (as the
729 * code waits on device memory to change).
730 * - kernel crashes, as all PCI reads return -1, which most code isn't able
731 * to handle well enough.
732 *
733 * In all cases dmesg will contain at least one line like this:
734 * 'nouveau 0000:01:00.0: Refused to change power state, currently in D3'
735 * followed by a lot of nouveau timeouts.
736 *
737 * In the \_SB.PCI0.PEG0.PG00._OFF code deeper down writes bit 0x80 to the not
738 * documented PCI config space register 0x248 of the Intel PCIe bridge
739 * controller (0x1901) in order to change the state of the PCIe link between
740 * the PCIe port and the GPU. There are alternative code paths using other
741 * registers, which seem to work fine (executed pre Windows 8):
742 * - 0xbc bit 0x20 (publicly available documentation claims 'reserved')
743 * - 0xb0 bit 0x10 (link disable)
744 * Changing the conditions inside the firmware by poking into the relevant
745 * addresses does resolve the issue, but it seemed to be ACPI private memory
746 * and not any device accessible memory at all, so there is no portable way of
747 * changing the conditions.
748 * On a XPS 9560 that means bits [0,3] on \CPEX need to be cleared.
749 *
750 * The only systems where this behavior can be seen are hybrid graphics laptops
751 * with a secondary Nvidia Maxwell, Pascal or Turing GPU. It's unclear whether
752 * this issue only occurs in combination with listed Intel PCIe bridge
753 * controllers and the mentioned GPUs or other devices as well.
754 *
755 * documentation on the PCIe bridge controller can be found in the
756 * "7th Generation Intel® Processor Families for H Platforms Datasheet Volume 2"
757 * Section "12 PCI Express* Controller (x16) Registers"
758 */
759
760static void quirk_broken_nv_runpm(struct pci_dev *pdev)
761{
762 struct drm_device *dev = pci_get_drvdata(pdev);
763 struct nouveau_drm *drm = nouveau_drm(dev);
764 struct pci_dev *bridge = pci_upstream_bridge(dev: pdev);
765
766 if (!bridge || bridge->vendor != PCI_VENDOR_ID_INTEL)
767 return;
768
769 switch (bridge->device) {
770 case 0x1901:
771 drm->old_pm_cap = pdev->pm_cap;
772 pdev->pm_cap = 0;
773 NV_INFO(drm, "Disabling PCI power management to avoid bug\n");
774 break;
775 }
776}
777
778static int nouveau_drm_probe(struct pci_dev *pdev,
779 const struct pci_device_id *pent)
780{
781 struct nvkm_device *device;
782 struct drm_device *drm_dev;
783 int ret;
784
785 if (vga_switcheroo_client_probe_defer(pdev))
786 return -EPROBE_DEFER;
787
788 /* We need to check that the chipset is supported before booting
789 * fbdev off the hardware, as there's no way to put it back.
790 */
791 ret = nvkm_device_pci_new(pdev, nouveau_config, "error",
792 true, false, 0, &device);
793 if (ret)
794 return ret;
795
796 nvkm_device_del(&device);
797
798 /* Remove conflicting drivers (vesafb, efifb etc). */
799 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, req_driver: &driver_pci);
800 if (ret)
801 return ret;
802
803 ret = nvkm_device_pci_new(pdev, nouveau_config, nouveau_debug,
804 true, true, ~0ULL, &device);
805 if (ret)
806 return ret;
807
808 pci_set_master(dev: pdev);
809
810 if (nouveau_atomic)
811 driver_pci.driver_features |= DRIVER_ATOMIC;
812
813 drm_dev = drm_dev_alloc(driver: &driver_pci, parent: &pdev->dev);
814 if (IS_ERR(ptr: drm_dev)) {
815 ret = PTR_ERR(ptr: drm_dev);
816 goto fail_nvkm;
817 }
818
819 ret = pci_enable_device(dev: pdev);
820 if (ret)
821 goto fail_drm;
822
823 pci_set_drvdata(pdev, data: drm_dev);
824
825 ret = nouveau_drm_device_init(dev: drm_dev);
826 if (ret)
827 goto fail_pci;
828
829 ret = drm_dev_register(dev: drm_dev, flags: pent->driver_data);
830 if (ret)
831 goto fail_drm_dev_init;
832
833 if (nouveau_drm(dev: drm_dev)->client.device.info.ram_size <= 32 * 1024 * 1024)
834 drm_fbdev_generic_setup(dev: drm_dev, preferred_bpp: 8);
835 else
836 drm_fbdev_generic_setup(dev: drm_dev, preferred_bpp: 32);
837
838 quirk_broken_nv_runpm(pdev);
839 return 0;
840
841fail_drm_dev_init:
842 nouveau_drm_device_fini(dev: drm_dev);
843fail_pci:
844 pci_disable_device(dev: pdev);
845fail_drm:
846 drm_dev_put(dev: drm_dev);
847fail_nvkm:
848 nvkm_device_del(&device);
849 return ret;
850}
851
852void
853nouveau_drm_device_remove(struct drm_device *dev)
854{
855 struct nouveau_drm *drm = nouveau_drm(dev);
856 struct nvkm_client *client;
857 struct nvkm_device *device;
858
859 drm_dev_unplug(dev);
860
861 client = nvxx_client(&drm->client.base);
862 device = nvkm_device_find(client->device);
863
864 nouveau_drm_device_fini(dev);
865 drm_dev_put(dev);
866 nvkm_device_del(&device);
867}
868
869static void
870nouveau_drm_remove(struct pci_dev *pdev)
871{
872 struct drm_device *dev = pci_get_drvdata(pdev);
873 struct nouveau_drm *drm = nouveau_drm(dev);
874
875 /* revert our workaround */
876 if (drm->old_pm_cap)
877 pdev->pm_cap = drm->old_pm_cap;
878 nouveau_drm_device_remove(dev);
879 pci_disable_device(dev: pdev);
880}
881
882static int
883nouveau_do_suspend(struct drm_device *dev, bool runtime)
884{
885 struct nouveau_drm *drm = nouveau_drm(dev);
886 struct ttm_resource_manager *man;
887 int ret;
888
889 nouveau_svm_suspend(drm);
890 nouveau_dmem_suspend(drm);
891 nouveau_led_suspend(dev);
892
893 if (dev->mode_config.num_crtc) {
894 NV_DEBUG(drm, "suspending display...\n");
895 ret = nouveau_display_suspend(dev, runtime);
896 if (ret)
897 return ret;
898 }
899
900 NV_DEBUG(drm, "evicting buffers...\n");
901
902 man = ttm_manager_type(bdev: &drm->ttm.bdev, TTM_PL_VRAM);
903 ttm_resource_manager_evict_all(bdev: &drm->ttm.bdev, man);
904
905 NV_DEBUG(drm, "waiting for kernel channels to go idle...\n");
906 if (drm->cechan) {
907 ret = nouveau_channel_idle(drm->cechan);
908 if (ret)
909 goto fail_display;
910 }
911
912 if (drm->channel) {
913 ret = nouveau_channel_idle(drm->channel);
914 if (ret)
915 goto fail_display;
916 }
917
918 NV_DEBUG(drm, "suspending fence...\n");
919 if (drm->fence && nouveau_fence(drm)->suspend) {
920 if (!nouveau_fence(drm)->suspend(drm)) {
921 ret = -ENOMEM;
922 goto fail_display;
923 }
924 }
925
926 NV_DEBUG(drm, "suspending object tree...\n");
927 ret = nvif_client_suspend(&drm->master.base);
928 if (ret)
929 goto fail_client;
930
931 return 0;
932
933fail_client:
934 if (drm->fence && nouveau_fence(drm)->resume)
935 nouveau_fence(drm)->resume(drm);
936
937fail_display:
938 if (dev->mode_config.num_crtc) {
939 NV_DEBUG(drm, "resuming display...\n");
940 nouveau_display_resume(dev, runtime);
941 }
942 return ret;
943}
944
945static int
946nouveau_do_resume(struct drm_device *dev, bool runtime)
947{
948 int ret = 0;
949 struct nouveau_drm *drm = nouveau_drm(dev);
950
951 NV_DEBUG(drm, "resuming object tree...\n");
952 ret = nvif_client_resume(&drm->master.base);
953 if (ret) {
954 NV_ERROR(drm, "Client resume failed with error: %d\n", ret);
955 return ret;
956 }
957
958 NV_DEBUG(drm, "resuming fence...\n");
959 if (drm->fence && nouveau_fence(drm)->resume)
960 nouveau_fence(drm)->resume(drm);
961
962 nouveau_run_vbios_init(dev);
963
964 if (dev->mode_config.num_crtc) {
965 NV_DEBUG(drm, "resuming display...\n");
966 nouveau_display_resume(dev, runtime);
967 }
968
969 nouveau_led_resume(dev);
970 nouveau_dmem_resume(drm);
971 nouveau_svm_resume(drm);
972 return 0;
973}
974
975int
976nouveau_pmops_suspend(struct device *dev)
977{
978 struct pci_dev *pdev = to_pci_dev(dev);
979 struct drm_device *drm_dev = pci_get_drvdata(pdev);
980 int ret;
981
982 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
983 drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
984 return 0;
985
986 ret = nouveau_do_suspend(dev: drm_dev, runtime: false);
987 if (ret)
988 return ret;
989
990 pci_save_state(dev: pdev);
991 pci_disable_device(dev: pdev);
992 pci_set_power_state(dev: pdev, PCI_D3hot);
993 udelay(200);
994 return 0;
995}
996
997int
998nouveau_pmops_resume(struct device *dev)
999{
1000 struct pci_dev *pdev = to_pci_dev(dev);
1001 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1002 int ret;
1003
1004 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
1005 drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
1006 return 0;
1007
1008 pci_set_power_state(dev: pdev, PCI_D0);
1009 pci_restore_state(dev: pdev);
1010 ret = pci_enable_device(dev: pdev);
1011 if (ret)
1012 return ret;
1013 pci_set_master(dev: pdev);
1014
1015 ret = nouveau_do_resume(dev: drm_dev, runtime: false);
1016
1017 /* Monitors may have been connected / disconnected during suspend */
1018 nouveau_display_hpd_resume(drm_dev);
1019
1020 return ret;
1021}
1022
1023static int
1024nouveau_pmops_freeze(struct device *dev)
1025{
1026 struct pci_dev *pdev = to_pci_dev(dev);
1027 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1028 return nouveau_do_suspend(dev: drm_dev, runtime: false);
1029}
1030
1031static int
1032nouveau_pmops_thaw(struct device *dev)
1033{
1034 struct pci_dev *pdev = to_pci_dev(dev);
1035 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1036 return nouveau_do_resume(dev: drm_dev, runtime: false);
1037}
1038
1039bool
1040nouveau_pmops_runtime(void)
1041{
1042 if (nouveau_runtime_pm == -1)
1043 return nouveau_is_optimus() || nouveau_is_v1_dsm();
1044 return nouveau_runtime_pm == 1;
1045}
1046
1047static int
1048nouveau_pmops_runtime_suspend(struct device *dev)
1049{
1050 struct pci_dev *pdev = to_pci_dev(dev);
1051 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1052 int ret;
1053
1054 if (!nouveau_pmops_runtime()) {
1055 pm_runtime_forbid(dev);
1056 return -EBUSY;
1057 }
1058
1059 nouveau_switcheroo_optimus_dsm();
1060 ret = nouveau_do_suspend(dev: drm_dev, runtime: true);
1061 pci_save_state(dev: pdev);
1062 pci_disable_device(dev: pdev);
1063 pci_ignore_hotplug(dev: pdev);
1064 pci_set_power_state(dev: pdev, PCI_D3cold);
1065 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
1066 return ret;
1067}
1068
1069static int
1070nouveau_pmops_runtime_resume(struct device *dev)
1071{
1072 struct pci_dev *pdev = to_pci_dev(dev);
1073 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1074 struct nouveau_drm *drm = nouveau_drm(dev: drm_dev);
1075 struct nvif_device *device = &nouveau_drm(dev: drm_dev)->client.device;
1076 int ret;
1077
1078 if (!nouveau_pmops_runtime()) {
1079 pm_runtime_forbid(dev);
1080 return -EBUSY;
1081 }
1082
1083 pci_set_power_state(dev: pdev, PCI_D0);
1084 pci_restore_state(dev: pdev);
1085 ret = pci_enable_device(dev: pdev);
1086 if (ret)
1087 return ret;
1088 pci_set_master(dev: pdev);
1089
1090 ret = nouveau_do_resume(dev: drm_dev, runtime: true);
1091 if (ret) {
1092 NV_ERROR(drm, "resume failed with: %d\n", ret);
1093 return ret;
1094 }
1095
1096 /* do magic */
1097 nvif_mask(&device->object, 0x088488, (1 << 25), (1 << 25));
1098 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
1099
1100 /* Monitors may have been connected / disconnected during suspend */
1101 nouveau_display_hpd_resume(drm_dev);
1102
1103 return ret;
1104}
1105
1106static int
1107nouveau_pmops_runtime_idle(struct device *dev)
1108{
1109 if (!nouveau_pmops_runtime()) {
1110 pm_runtime_forbid(dev);
1111 return -EBUSY;
1112 }
1113
1114 pm_runtime_mark_last_busy(dev);
1115 pm_runtime_autosuspend(dev);
1116 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
1117 return 1;
1118}
1119
1120static int
1121nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv)
1122{
1123 struct nouveau_drm *drm = nouveau_drm(dev);
1124 struct nouveau_cli *cli;
1125 char name[32], tmpname[TASK_COMM_LEN];
1126 int ret;
1127
1128 /* need to bring up power immediately if opening device */
1129 ret = pm_runtime_get_sync(dev: dev->dev);
1130 if (ret < 0 && ret != -EACCES) {
1131 pm_runtime_put_autosuspend(dev: dev->dev);
1132 return ret;
1133 }
1134
1135 get_task_comm(tmpname, current);
1136 rcu_read_lock();
1137 snprintf(buf: name, size: sizeof(name), fmt: "%s[%d]",
1138 tmpname, pid_nr(rcu_dereference(fpriv->pid)));
1139 rcu_read_unlock();
1140
1141 if (!(cli = kzalloc(size: sizeof(*cli), GFP_KERNEL))) {
1142 ret = -ENOMEM;
1143 goto done;
1144 }
1145
1146 ret = nouveau_cli_init(drm, sname: name, cli);
1147 if (ret)
1148 goto done;
1149
1150 fpriv->driver_priv = cli;
1151
1152 mutex_lock(&drm->clients_lock);
1153 list_add(new: &cli->head, head: &drm->clients);
1154 mutex_unlock(lock: &drm->clients_lock);
1155
1156done:
1157 if (ret && cli) {
1158 nouveau_cli_fini(cli);
1159 kfree(objp: cli);
1160 }
1161
1162 pm_runtime_mark_last_busy(dev: dev->dev);
1163 pm_runtime_put_autosuspend(dev: dev->dev);
1164 return ret;
1165}
1166
1167static void
1168nouveau_drm_postclose(struct drm_device *dev, struct drm_file *fpriv)
1169{
1170 struct nouveau_cli *cli = nouveau_cli(fpriv);
1171 struct nouveau_drm *drm = nouveau_drm(dev);
1172 int dev_index;
1173
1174 /*
1175 * The device is gone, and as it currently stands all clients are
1176 * cleaned up in the removal codepath. In the future this may change
1177 * so that we can support hot-unplugging, but for now we immediately
1178 * return to avoid a double-free situation.
1179 */
1180 if (!drm_dev_enter(dev, idx: &dev_index))
1181 return;
1182
1183 pm_runtime_get_sync(dev: dev->dev);
1184
1185 mutex_lock(&cli->mutex);
1186 if (cli->abi16)
1187 nouveau_abi16_fini(cli->abi16);
1188 mutex_unlock(lock: &cli->mutex);
1189
1190 mutex_lock(&drm->clients_lock);
1191 list_del(entry: &cli->head);
1192 mutex_unlock(lock: &drm->clients_lock);
1193
1194 nouveau_cli_fini(cli);
1195 kfree(objp: cli);
1196 pm_runtime_mark_last_busy(dev: dev->dev);
1197 pm_runtime_put_autosuspend(dev: dev->dev);
1198 drm_dev_exit(idx: dev_index);
1199}
1200
1201static const struct drm_ioctl_desc
1202nouveau_ioctls[] = {
1203 DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_RENDER_ALLOW),
1204 DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1205 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_RENDER_ALLOW),
1206 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_RENDER_ALLOW),
1207 DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_RENDER_ALLOW),
1208 DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_RENDER_ALLOW),
1209 DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_RENDER_ALLOW),
1210 DRM_IOCTL_DEF_DRV(NOUVEAU_SVM_INIT, nouveau_svmm_init, DRM_RENDER_ALLOW),
1211 DRM_IOCTL_DEF_DRV(NOUVEAU_SVM_BIND, nouveau_svmm_bind, DRM_RENDER_ALLOW),
1212 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_RENDER_ALLOW),
1213 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_RENDER_ALLOW),
1214 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_RENDER_ALLOW),
1215 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_RENDER_ALLOW),
1216 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_RENDER_ALLOW),
1217 DRM_IOCTL_DEF_DRV(NOUVEAU_VM_INIT, nouveau_uvmm_ioctl_vm_init, DRM_RENDER_ALLOW),
1218 DRM_IOCTL_DEF_DRV(NOUVEAU_VM_BIND, nouveau_uvmm_ioctl_vm_bind, DRM_RENDER_ALLOW),
1219 DRM_IOCTL_DEF_DRV(NOUVEAU_EXEC, nouveau_exec_ioctl_exec, DRM_RENDER_ALLOW),
1220};
1221
1222long
1223nouveau_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
1224{
1225 struct drm_file *filp = file->private_data;
1226 struct drm_device *dev = filp->minor->dev;
1227 long ret;
1228
1229 ret = pm_runtime_get_sync(dev: dev->dev);
1230 if (ret < 0 && ret != -EACCES) {
1231 pm_runtime_put_autosuspend(dev: dev->dev);
1232 return ret;
1233 }
1234
1235 switch (_IOC_NR(cmd) - DRM_COMMAND_BASE) {
1236 case DRM_NOUVEAU_NVIF:
1237 ret = usif_ioctl(filp, (void __user *)arg, _IOC_SIZE(cmd));
1238 break;
1239 default:
1240 ret = drm_ioctl(filp: file, cmd, arg);
1241 break;
1242 }
1243
1244 pm_runtime_mark_last_busy(dev: dev->dev);
1245 pm_runtime_put_autosuspend(dev: dev->dev);
1246 return ret;
1247}
1248
1249static const struct file_operations
1250nouveau_driver_fops = {
1251 .owner = THIS_MODULE,
1252 .open = drm_open,
1253 .release = drm_release,
1254 .unlocked_ioctl = nouveau_drm_ioctl,
1255 .mmap = drm_gem_mmap,
1256 .poll = drm_poll,
1257 .read = drm_read,
1258#if defined(CONFIG_COMPAT)
1259 .compat_ioctl = nouveau_compat_ioctl,
1260#endif
1261 .llseek = noop_llseek,
1262};
1263
1264static struct drm_driver
1265driver_stub = {
1266 .driver_features = DRIVER_GEM |
1267 DRIVER_SYNCOBJ | DRIVER_SYNCOBJ_TIMELINE |
1268 DRIVER_GEM_GPUVA |
1269 DRIVER_MODESET |
1270 DRIVER_RENDER,
1271 .open = nouveau_drm_open,
1272 .postclose = nouveau_drm_postclose,
1273 .lastclose = nouveau_vga_lastclose,
1274
1275#if defined(CONFIG_DEBUG_FS)
1276 .debugfs_init = nouveau_drm_debugfs_init,
1277#endif
1278
1279 .ioctls = nouveau_ioctls,
1280 .num_ioctls = ARRAY_SIZE(nouveau_ioctls),
1281 .fops = &nouveau_driver_fops,
1282
1283 .gem_prime_import_sg_table = nouveau_gem_prime_import_sg_table,
1284
1285 .dumb_create = nouveau_display_dumb_create,
1286 .dumb_map_offset = drm_gem_ttm_dumb_map_offset,
1287
1288 .name = DRIVER_NAME,
1289 .desc = DRIVER_DESC,
1290#ifdef GIT_REVISION
1291 .date = GIT_REVISION,
1292#else
1293 .date = DRIVER_DATE,
1294#endif
1295 .major = DRIVER_MAJOR,
1296 .minor = DRIVER_MINOR,
1297 .patchlevel = DRIVER_PATCHLEVEL,
1298};
1299
1300static struct pci_device_id
1301nouveau_drm_pci_table[] = {
1302 {
1303 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
1304 .class = PCI_BASE_CLASS_DISPLAY << 16,
1305 .class_mask = 0xff << 16,
1306 },
1307 {
1308 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
1309 .class = PCI_BASE_CLASS_DISPLAY << 16,
1310 .class_mask = 0xff << 16,
1311 },
1312 {}
1313};
1314
1315static void nouveau_display_options(void)
1316{
1317 DRM_DEBUG_DRIVER("Loading Nouveau with parameters:\n");
1318
1319 DRM_DEBUG_DRIVER("... tv_disable : %d\n", nouveau_tv_disable);
1320 DRM_DEBUG_DRIVER("... ignorelid : %d\n", nouveau_ignorelid);
1321 DRM_DEBUG_DRIVER("... duallink : %d\n", nouveau_duallink);
1322 DRM_DEBUG_DRIVER("... config : %s\n", nouveau_config);
1323 DRM_DEBUG_DRIVER("... debug : %s\n", nouveau_debug);
1324 DRM_DEBUG_DRIVER("... noaccel : %d\n", nouveau_noaccel);
1325 DRM_DEBUG_DRIVER("... modeset : %d\n", nouveau_modeset);
1326 DRM_DEBUG_DRIVER("... runpm : %d\n", nouveau_runtime_pm);
1327 DRM_DEBUG_DRIVER("... vram_pushbuf : %d\n", nouveau_vram_pushbuf);
1328 DRM_DEBUG_DRIVER("... hdmimhz : %d\n", nouveau_hdmimhz);
1329}
1330
1331static const struct dev_pm_ops nouveau_pm_ops = {
1332 .suspend = nouveau_pmops_suspend,
1333 .resume = nouveau_pmops_resume,
1334 .freeze = nouveau_pmops_freeze,
1335 .thaw = nouveau_pmops_thaw,
1336 .poweroff = nouveau_pmops_freeze,
1337 .restore = nouveau_pmops_resume,
1338 .runtime_suspend = nouveau_pmops_runtime_suspend,
1339 .runtime_resume = nouveau_pmops_runtime_resume,
1340 .runtime_idle = nouveau_pmops_runtime_idle,
1341};
1342
1343static struct pci_driver
1344nouveau_drm_pci_driver = {
1345 .name = "nouveau",
1346 .id_table = nouveau_drm_pci_table,
1347 .probe = nouveau_drm_probe,
1348 .remove = nouveau_drm_remove,
1349 .driver.pm = &nouveau_pm_ops,
1350};
1351
1352struct drm_device *
1353nouveau_platform_device_create(const struct nvkm_device_tegra_func *func,
1354 struct platform_device *pdev,
1355 struct nvkm_device **pdevice)
1356{
1357 struct drm_device *drm;
1358 int err;
1359
1360 err = nvkm_device_tegra_new(func, pdev, nouveau_config, nouveau_debug,
1361 true, true, ~0ULL, pdevice);
1362 if (err)
1363 goto err_free;
1364
1365 drm = drm_dev_alloc(driver: &driver_platform, parent: &pdev->dev);
1366 if (IS_ERR(ptr: drm)) {
1367 err = PTR_ERR(ptr: drm);
1368 goto err_free;
1369 }
1370
1371 err = nouveau_drm_device_init(dev: drm);
1372 if (err)
1373 goto err_put;
1374
1375 platform_set_drvdata(pdev, drm);
1376
1377 return drm;
1378
1379err_put:
1380 drm_dev_put(dev: drm);
1381err_free:
1382 nvkm_device_del(pdevice);
1383
1384 return ERR_PTR(error: err);
1385}
1386
1387static int __init
1388nouveau_drm_init(void)
1389{
1390 driver_pci = driver_stub;
1391 driver_platform = driver_stub;
1392
1393 nouveau_display_options();
1394
1395 if (nouveau_modeset == -1) {
1396 if (drm_firmware_drivers_only())
1397 nouveau_modeset = 0;
1398 }
1399
1400 if (!nouveau_modeset)
1401 return 0;
1402
1403#ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
1404 platform_driver_register(&nouveau_platform_driver);
1405#endif
1406
1407 nouveau_register_dsm_handler();
1408 nouveau_backlight_ctor();
1409
1410#ifdef CONFIG_PCI
1411 return pci_register_driver(&nouveau_drm_pci_driver);
1412#else
1413 return 0;
1414#endif
1415}
1416
1417static void __exit
1418nouveau_drm_exit(void)
1419{
1420 if (!nouveau_modeset)
1421 return;
1422
1423#ifdef CONFIG_PCI
1424 pci_unregister_driver(dev: &nouveau_drm_pci_driver);
1425#endif
1426 nouveau_backlight_dtor();
1427 nouveau_unregister_dsm_handler();
1428
1429#ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
1430 platform_driver_unregister(&nouveau_platform_driver);
1431#endif
1432 if (IS_ENABLED(CONFIG_DRM_NOUVEAU_SVM))
1433 mmu_notifier_synchronize();
1434}
1435
1436module_init(nouveau_drm_init);
1437module_exit(nouveau_drm_exit);
1438
1439MODULE_DEVICE_TABLE(pci, nouveau_drm_pci_table);
1440MODULE_AUTHOR(DRIVER_AUTHOR);
1441MODULE_DESCRIPTION(DRIVER_DESC);
1442MODULE_LICENSE("GPL and additional rights");
1443

source code of linux/drivers/gpu/drm/nouveau/nouveau_drm.c