1 | #ifndef _VC4_HDMI_H_ |
2 | #define _VC4_HDMI_H_ |
3 | |
4 | #include <drm/drm_connector.h> |
5 | #include <media/cec.h> |
6 | #include <sound/dmaengine_pcm.h> |
7 | #include <sound/hdmi-codec.h> |
8 | #include <sound/soc.h> |
9 | |
10 | #include "vc4_drv.h" |
11 | |
12 | struct vc4_hdmi; |
13 | struct vc4_hdmi_register; |
14 | |
15 | enum vc4_hdmi_phy_channel { |
16 | PHY_LANE_0 = 0, |
17 | PHY_LANE_1, |
18 | PHY_LANE_2, |
19 | PHY_LANE_CK, |
20 | }; |
21 | |
22 | struct vc4_hdmi_variant { |
23 | /* Encoder Type for that controller */ |
24 | enum vc4_encoder_type encoder_type; |
25 | |
26 | /* ALSA card name */ |
27 | const char *card_name; |
28 | |
29 | /* Filename to expose the registers in debugfs */ |
30 | const char *debugfs_name; |
31 | |
32 | /* Maximum pixel clock supported by the controller (in Hz) */ |
33 | unsigned long long max_pixel_clock; |
34 | |
35 | /* List of the registers available on that variant */ |
36 | const struct vc4_hdmi_register *registers; |
37 | |
38 | /* Number of registers on that variant */ |
39 | unsigned int num_registers; |
40 | |
41 | /* BCM2711 Only. |
42 | * The variants don't map the lane in the same order in the |
43 | * PHY, so this is an array mapping the HDMI channel (index) |
44 | * to the PHY lane (value). |
45 | */ |
46 | enum vc4_hdmi_phy_channel phy_lane_mapping[4]; |
47 | |
48 | /* The BCM2711 cannot deal with odd horizontal pixel timings */ |
49 | bool unsupported_odd_h_timings; |
50 | |
51 | /* |
52 | * The BCM2711 CEC/hotplug IRQ controller is shared between the |
53 | * two HDMI controllers, and we have a proper irqchip driver for |
54 | * it. |
55 | */ |
56 | bool external_irq_controller; |
57 | |
58 | /* Callback to get the resources (memory region, interrupts, |
59 | * clocks, etc) for that variant. |
60 | */ |
61 | int (*init_resources)(struct drm_device *drm, |
62 | struct vc4_hdmi *vc4_hdmi); |
63 | |
64 | /* Callback to reset the HDMI block */ |
65 | void (*reset)(struct vc4_hdmi *vc4_hdmi); |
66 | |
67 | /* Callback to enable / disable the CSC */ |
68 | void (*csc_setup)(struct vc4_hdmi *vc4_hdmi, |
69 | struct drm_connector_state *state, |
70 | const struct drm_display_mode *mode); |
71 | |
72 | /* Callback to configure the video timings in the HDMI block */ |
73 | void (*set_timings)(struct vc4_hdmi *vc4_hdmi, |
74 | struct drm_connector_state *state, |
75 | const struct drm_display_mode *mode); |
76 | |
77 | /* Callback to initialize the PHY according to the connector state */ |
78 | void (*phy_init)(struct vc4_hdmi *vc4_hdmi, |
79 | struct drm_connector_state *conn_state); |
80 | |
81 | /* Callback to disable the PHY */ |
82 | void (*phy_disable)(struct vc4_hdmi *vc4_hdmi); |
83 | |
84 | /* Callback to enable the RNG in the PHY */ |
85 | void (*phy_rng_enable)(struct vc4_hdmi *vc4_hdmi); |
86 | |
87 | /* Callback to disable the RNG in the PHY */ |
88 | void (*phy_rng_disable)(struct vc4_hdmi *vc4_hdmi); |
89 | |
90 | /* Callback to get channel map */ |
91 | u32 (*channel_map)(struct vc4_hdmi *vc4_hdmi, u32 channel_mask); |
92 | |
93 | /* Enables HDR metadata */ |
94 | bool supports_hdr; |
95 | |
96 | /* Callback for hardware specific hotplug detect */ |
97 | bool (*hp_detect)(struct vc4_hdmi *vc4_hdmi); |
98 | }; |
99 | |
100 | /* HDMI audio information */ |
101 | struct vc4_hdmi_audio { |
102 | struct snd_soc_card card; |
103 | struct snd_soc_dai_link link; |
104 | struct snd_soc_dai_link_component cpu; |
105 | struct snd_soc_dai_link_component codec; |
106 | struct snd_soc_dai_link_component platform; |
107 | struct snd_dmaengine_dai_dma_data dma_data; |
108 | bool streaming; |
109 | }; |
110 | |
111 | /* General HDMI hardware state. */ |
112 | struct vc4_hdmi { |
113 | struct vc4_hdmi_audio audio; |
114 | |
115 | struct platform_device *pdev; |
116 | const struct vc4_hdmi_variant *variant; |
117 | |
118 | struct vc4_encoder encoder; |
119 | struct drm_connector connector; |
120 | |
121 | struct delayed_work scrambling_work; |
122 | |
123 | struct i2c_adapter *ddc; |
124 | void __iomem *hdmicore_regs; |
125 | void __iomem *hd_regs; |
126 | |
127 | /* VC5 Only */ |
128 | void __iomem *cec_regs; |
129 | /* VC5 Only */ |
130 | void __iomem *csc_regs; |
131 | /* VC5 Only */ |
132 | void __iomem *dvp_regs; |
133 | /* VC5 Only */ |
134 | void __iomem *phy_regs; |
135 | /* VC5 Only */ |
136 | void __iomem *ram_regs; |
137 | /* VC5 Only */ |
138 | void __iomem *rm_regs; |
139 | |
140 | struct gpio_desc *hpd_gpio; |
141 | |
142 | /* |
143 | * On some systems (like the RPi4), some modes are in the same |
144 | * frequency range than the WiFi channels (1440p@60Hz for |
145 | * example). Should we take evasive actions because that system |
146 | * has a wifi adapter? |
147 | */ |
148 | bool disable_wifi_frequencies; |
149 | |
150 | struct cec_adapter *cec_adap; |
151 | struct cec_msg cec_rx_msg; |
152 | bool cec_tx_ok; |
153 | bool cec_irq_was_rx; |
154 | |
155 | struct clk *cec_clock; |
156 | struct clk *pixel_clock; |
157 | struct clk *hsm_clock; |
158 | struct clk *audio_clock; |
159 | struct clk *pixel_bvb_clock; |
160 | |
161 | struct reset_control *reset; |
162 | |
163 | struct debugfs_regset32 hdmi_regset; |
164 | struct debugfs_regset32 hd_regset; |
165 | |
166 | /* VC5 only */ |
167 | struct debugfs_regset32 cec_regset; |
168 | struct debugfs_regset32 csc_regset; |
169 | struct debugfs_regset32 dvp_regset; |
170 | struct debugfs_regset32 phy_regset; |
171 | struct debugfs_regset32 ram_regset; |
172 | struct debugfs_regset32 rm_regset; |
173 | |
174 | /** |
175 | * @hw_lock: Spinlock protecting device register access. |
176 | */ |
177 | spinlock_t hw_lock; |
178 | |
179 | /** |
180 | * @mutex: Mutex protecting the driver access across multiple |
181 | * frameworks (KMS, ALSA, CEC). |
182 | */ |
183 | struct mutex mutex; |
184 | |
185 | /** |
186 | * @saved_adjusted_mode: Copy of @drm_crtc_state.adjusted_mode |
187 | * for use by ALSA hooks and interrupt handlers. Protected by @mutex. |
188 | */ |
189 | struct drm_display_mode saved_adjusted_mode; |
190 | |
191 | /** |
192 | * @packet_ram_enabled: Is the HDMI controller packet RAM currently |
193 | * on? Protected by @mutex. |
194 | */ |
195 | bool packet_ram_enabled; |
196 | |
197 | /** |
198 | * @scdc_enabled: Is the HDMI controller currently running with |
199 | * the scrambler on? Protected by @mutex. |
200 | */ |
201 | bool scdc_enabled; |
202 | |
203 | /** |
204 | * @output_bpc: Copy of @drm_connector_state.hdmi.output_bpc for |
205 | * use outside of KMS hooks. Protected by @mutex. |
206 | */ |
207 | unsigned int output_bpc; |
208 | |
209 | /** |
210 | * @output_format: Copy of |
211 | * @drm_connector_state.hdmi.output_format for use outside of |
212 | * KMS hooks. Protected by @mutex. |
213 | */ |
214 | enum hdmi_colorspace output_format; |
215 | |
216 | /** |
217 | * @hdmi_jack: Represents the connection state of the HDMI plug, for |
218 | * ALSA jack detection. |
219 | */ |
220 | struct snd_soc_jack hdmi_jack; |
221 | }; |
222 | |
223 | #define connector_to_vc4_hdmi(_connector) \ |
224 | container_of_const(_connector, struct vc4_hdmi, connector) |
225 | |
226 | static inline struct vc4_hdmi * |
227 | encoder_to_vc4_hdmi(struct drm_encoder *encoder) |
228 | { |
229 | struct vc4_encoder *_encoder = to_vc4_encoder(encoder); |
230 | return container_of_const(_encoder, struct vc4_hdmi, encoder); |
231 | } |
232 | |
233 | void vc4_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi, |
234 | struct drm_connector_state *conn_state); |
235 | void vc4_hdmi_phy_disable(struct vc4_hdmi *vc4_hdmi); |
236 | void vc4_hdmi_phy_rng_enable(struct vc4_hdmi *vc4_hdmi); |
237 | void vc4_hdmi_phy_rng_disable(struct vc4_hdmi *vc4_hdmi); |
238 | |
239 | void vc5_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi, |
240 | struct drm_connector_state *conn_state); |
241 | void vc5_hdmi_phy_disable(struct vc4_hdmi *vc4_hdmi); |
242 | void vc5_hdmi_phy_rng_enable(struct vc4_hdmi *vc4_hdmi); |
243 | void vc5_hdmi_phy_rng_disable(struct vc4_hdmi *vc4_hdmi); |
244 | |
245 | void vc6_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi, |
246 | struct drm_connector_state *conn_state); |
247 | void vc6_hdmi_phy_disable(struct vc4_hdmi *vc4_hdmi); |
248 | |
249 | #endif /* _VC4_HDMI_H_ */ |
250 | |