| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * ZynqMP Display Driver |
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| 4 | * |
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| 5 | * Copyright (C) 2017 - 2020 Xilinx, Inc. |
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| 6 | * |
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| 7 | * Authors: |
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| 8 | * - Hyun Woo Kwon <hyun.kwon@xilinx.com> |
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| 9 | * - Laurent Pinchart <laurent.pinchart@ideasonboard.com> |
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| 10 | */ |
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| 11 | |
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| 12 | #ifndef _ZYNQMP_DISP_H_ |
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| 13 | #define _ZYNQMP_DISP_H_ |
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| 14 | |
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| 15 | #include <linux/types.h> |
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| 16 | |
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| 17 | /* |
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| 18 | * 3840x2160 is advertised as the maximum resolution, but almost any |
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| 19 | * resolutions under a 300Mhz pixel rate would work. Pick 4096x4096. |
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| 20 | */ |
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| 21 | #define ZYNQMP_DISP_MAX_WIDTH 4096 |
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| 22 | #define ZYNQMP_DISP_MAX_HEIGHT 4096 |
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| 23 | |
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| 24 | /* The DPDMA is limited to 44 bit addressing. */ |
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| 25 | #define ZYNQMP_DISP_MAX_DMA_BIT 44 |
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| 26 | |
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| 27 | struct device; |
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| 28 | struct drm_format_info; |
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| 29 | struct drm_plane_state; |
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| 30 | struct platform_device; |
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| 31 | struct zynqmp_disp; |
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| 32 | struct zynqmp_disp_layer; |
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| 33 | struct zynqmp_dpsub; |
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| 34 | |
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| 35 | /** |
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| 36 | * enum zynqmp_dpsub_layer_id - Layer identifier |
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| 37 | * @ZYNQMP_DPSUB_LAYER_VID: Video layer |
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| 38 | * @ZYNQMP_DPSUB_LAYER_GFX: Graphics layer |
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| 39 | */ |
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| 40 | enum zynqmp_dpsub_layer_id { |
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| 41 | ZYNQMP_DPSUB_LAYER_VID, |
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| 42 | ZYNQMP_DPSUB_LAYER_GFX, |
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| 43 | }; |
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| 44 | |
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| 45 | /** |
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| 46 | * enum zynqmp_dpsub_layer_mode - Layer mode |
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| 47 | * @ZYNQMP_DPSUB_LAYER_NONLIVE: non-live (memory) mode |
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| 48 | * @ZYNQMP_DPSUB_LAYER_LIVE: live (stream) mode |
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| 49 | */ |
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| 50 | enum zynqmp_dpsub_layer_mode { |
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| 51 | ZYNQMP_DPSUB_LAYER_NONLIVE, |
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| 52 | ZYNQMP_DPSUB_LAYER_LIVE, |
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| 53 | }; |
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| 54 | |
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| 55 | void zynqmp_disp_enable(struct zynqmp_disp *disp); |
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| 56 | void zynqmp_disp_disable(struct zynqmp_disp *disp); |
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| 57 | int zynqmp_disp_setup_clock(struct zynqmp_disp *disp, |
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| 58 | unsigned long mode_clock); |
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| 59 | |
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| 60 | void zynqmp_disp_blend_set_global_alpha(struct zynqmp_disp *disp, |
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| 61 | bool enable, u32 alpha); |
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| 62 | |
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| 63 | u32 *zynqmp_disp_layer_drm_formats(struct zynqmp_disp_layer *layer, |
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| 64 | unsigned int *num_formats); |
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| 65 | void zynqmp_disp_layer_enable(struct zynqmp_disp_layer *layer, |
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| 66 | enum zynqmp_dpsub_layer_mode mode); |
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| 67 | void zynqmp_disp_layer_disable(struct zynqmp_disp_layer *layer); |
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| 68 | void zynqmp_disp_layer_set_format(struct zynqmp_disp_layer *layer, |
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| 69 | const struct drm_format_info *info); |
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| 70 | int zynqmp_disp_layer_update(struct zynqmp_disp_layer *layer, |
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| 71 | struct drm_plane_state *state); |
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| 72 | |
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| 73 | int zynqmp_disp_probe(struct zynqmp_dpsub *dpsub); |
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| 74 | void zynqmp_disp_remove(struct zynqmp_dpsub *dpsub); |
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| 75 | |
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| 76 | #endif /* _ZYNQMP_DISP_H_ */ |
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| 77 | |
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