1 | /* |
2 | * This file is provided under a dual BSD/GPLv2 license. When using or |
3 | * redistributing this file, you may do so under either license. |
4 | * |
5 | * Copyright(c) 2012 Intel Corporation. All rights reserved. |
6 | * |
7 | * GPL LICENSE SUMMARY |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify |
10 | * it under the terms of version 2 of the GNU General Public License as |
11 | * published by the Free Software Foundation. |
12 | * |
13 | * This program is distributed in the hope that it will be useful, but |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
16 | * General Public License for more details. |
17 | * The full GNU General Public License is included in this distribution |
18 | * in the file called LICENSE.GPL. |
19 | * |
20 | * BSD LICENSE |
21 | * |
22 | * Redistribution and use in source and binary forms, with or without |
23 | * modification, are permitted provided that the following conditions |
24 | * are met: |
25 | * |
26 | * * Redistributions of source code must retain the above copyright |
27 | * notice, this list of conditions and the following disclaimer. |
28 | * * Redistributions in binary form must reproduce the above copyright |
29 | * notice, this list of conditions and the following disclaimer in |
30 | * the documentation and/or other materials provided with the |
31 | * distribution. |
32 | * * Neither the name of Intel Corporation nor the names of its |
33 | * contributors may be used to endorse or promote products derived |
34 | * from this software without specific prior written permission. |
35 | * |
36 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
37 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
38 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
39 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
40 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
41 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
42 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
43 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
44 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
45 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
46 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
47 | */ |
48 | |
49 | /* |
50 | * Supports the SMBus Message Transport (SMT) in the Intel Atom Processor |
51 | * S12xx Product Family. |
52 | * |
53 | * Features supported by this driver: |
54 | * Hardware PEC yes |
55 | * Block buffer yes |
56 | * Block process call transaction yes |
57 | * Slave mode no |
58 | */ |
59 | |
60 | #include <linux/module.h> |
61 | #include <linux/pci.h> |
62 | #include <linux/kernel.h> |
63 | #include <linux/stddef.h> |
64 | #include <linux/completion.h> |
65 | #include <linux/dma-mapping.h> |
66 | #include <linux/i2c.h> |
67 | #include <linux/acpi.h> |
68 | #include <linux/interrupt.h> |
69 | |
70 | #include <linux/io-64-nonatomic-lo-hi.h> |
71 | |
72 | /* PCI Address Constants */ |
73 | #define SMBBAR 0 |
74 | |
75 | /* PCI DIDs for the Intel SMBus Message Transport (SMT) Devices */ |
76 | #define PCI_DEVICE_ID_INTEL_S1200_SMT0 0x0c59 |
77 | #define PCI_DEVICE_ID_INTEL_S1200_SMT1 0x0c5a |
78 | #define PCI_DEVICE_ID_INTEL_CDF_SMT 0x18ac |
79 | #define PCI_DEVICE_ID_INTEL_DNV_SMT 0x19ac |
80 | #define PCI_DEVICE_ID_INTEL_EBG_SMT 0x1bff |
81 | #define PCI_DEVICE_ID_INTEL_AVOTON_SMT 0x1f15 |
82 | |
83 | #define ISMT_DESC_ENTRIES 2 /* number of descriptor entries */ |
84 | #define ISMT_MAX_RETRIES 3 /* number of SMBus retries to attempt */ |
85 | #define ISMT_LOG_ENTRIES 3 /* number of interrupt cause log entries */ |
86 | |
87 | /* Hardware Descriptor Constants - Control Field */ |
88 | #define ISMT_DESC_CWRL 0x01 /* Command/Write Length */ |
89 | #define ISMT_DESC_BLK 0X04 /* Perform Block Transaction */ |
90 | #define ISMT_DESC_FAIR 0x08 /* Set fairness flag upon successful arbit. */ |
91 | #define ISMT_DESC_PEC 0x10 /* Packet Error Code */ |
92 | #define ISMT_DESC_I2C 0x20 /* I2C Enable */ |
93 | #define ISMT_DESC_INT 0x40 /* Interrupt */ |
94 | #define ISMT_DESC_SOE 0x80 /* Stop On Error */ |
95 | |
96 | /* Hardware Descriptor Constants - Status Field */ |
97 | #define ISMT_DESC_SCS 0x01 /* Success */ |
98 | #define ISMT_DESC_DLTO 0x04 /* Data Low Time Out */ |
99 | #define ISMT_DESC_NAK 0x08 /* NAK Received */ |
100 | #define ISMT_DESC_CRC 0x10 /* CRC Error */ |
101 | #define ISMT_DESC_CLTO 0x20 /* Clock Low Time Out */ |
102 | #define ISMT_DESC_COL 0x40 /* Collisions */ |
103 | #define ISMT_DESC_LPR 0x80 /* Large Packet Received */ |
104 | |
105 | /* Macros */ |
106 | #define ISMT_DESC_ADDR_RW(addr, rw) (((addr) << 1) | (rw)) |
107 | |
108 | /* iSMT General Register address offsets (SMBBAR + <addr>) */ |
109 | #define ISMT_GR_GCTRL 0x000 /* General Control */ |
110 | #define ISMT_GR_SMTICL 0x008 /* SMT Interrupt Cause Location */ |
111 | #define ISMT_GR_ERRINTMSK 0x010 /* Error Interrupt Mask */ |
112 | #define ISMT_GR_ERRAERMSK 0x014 /* Error AER Mask */ |
113 | #define ISMT_GR_ERRSTS 0x018 /* Error Status */ |
114 | #define ISMT_GR_ERRINFO 0x01c /* Error Information */ |
115 | |
116 | /* iSMT Master Registers */ |
117 | #define ISMT_MSTR_MDBA 0x100 /* Master Descriptor Base Address */ |
118 | #define ISMT_MSTR_MCTRL 0x108 /* Master Control */ |
119 | #define ISMT_MSTR_MSTS 0x10c /* Master Status */ |
120 | #define ISMT_MSTR_MDS 0x110 /* Master Descriptor Size */ |
121 | #define ISMT_MSTR_RPOLICY 0x114 /* Retry Policy */ |
122 | |
123 | /* iSMT Miscellaneous Registers */ |
124 | #define ISMT_SPGT 0x300 /* SMBus PHY Global Timing */ |
125 | |
126 | /* General Control Register (GCTRL) bit definitions */ |
127 | #define ISMT_GCTRL_TRST 0x04 /* Target Reset */ |
128 | #define ISMT_GCTRL_KILL 0x08 /* Kill */ |
129 | #define ISMT_GCTRL_SRST 0x40 /* Soft Reset */ |
130 | |
131 | /* Master Control Register (MCTRL) bit definitions */ |
132 | #define ISMT_MCTRL_SS 0x01 /* Start/Stop */ |
133 | #define ISMT_MCTRL_MEIE 0x10 /* Master Error Interrupt Enable */ |
134 | #define ISMT_MCTRL_FMHP 0x00ff0000 /* Firmware Master Head Ptr (FMHP) */ |
135 | |
136 | /* Master Status Register (MSTS) bit definitions */ |
137 | #define ISMT_MSTS_HMTP 0xff0000 /* HW Master Tail Pointer (HMTP) */ |
138 | #define ISMT_MSTS_MIS 0x20 /* Master Interrupt Status (MIS) */ |
139 | #define ISMT_MSTS_MEIS 0x10 /* Master Error Int Status (MEIS) */ |
140 | #define ISMT_MSTS_IP 0x01 /* In Progress */ |
141 | |
142 | /* Master Descriptor Size (MDS) bit definitions */ |
143 | #define ISMT_MDS_MASK 0xff /* Master Descriptor Size mask (MDS) */ |
144 | |
145 | /* SMBus PHY Global Timing Register (SPGT) bit definitions */ |
146 | #define ISMT_SPGT_SPD_MASK 0xc0000000 /* SMBus Speed mask */ |
147 | #define ISMT_SPGT_SPD_80K 0x00 /* 80 kHz */ |
148 | #define ISMT_SPGT_SPD_100K (0x1 << 30) /* 100 kHz */ |
149 | #define ISMT_SPGT_SPD_400K (0x2U << 30) /* 400 kHz */ |
150 | #define ISMT_SPGT_SPD_1M (0x3U << 30) /* 1 MHz */ |
151 | |
152 | |
153 | /* MSI Control Register (MSICTL) bit definitions */ |
154 | #define ISMT_MSICTL_MSIE 0x01 /* MSI Enable */ |
155 | |
156 | /* iSMT Hardware Descriptor */ |
157 | struct ismt_desc { |
158 | u8 tgtaddr_rw; /* target address & r/w bit */ |
159 | u8 wr_len_cmd; /* write length in bytes or a command */ |
160 | u8 rd_len; /* read length */ |
161 | u8 control; /* control bits */ |
162 | u8 status; /* status bits */ |
163 | u8 retry; /* collision retry and retry count */ |
164 | u8 rxbytes; /* received bytes */ |
165 | u8 txbytes; /* transmitted bytes */ |
166 | u32 dptr_low; /* lower 32 bit of the data pointer */ |
167 | u32 dptr_high; /* upper 32 bit of the data pointer */ |
168 | } __packed; |
169 | |
170 | struct ismt_priv { |
171 | struct i2c_adapter adapter; |
172 | void __iomem *smba; /* PCI BAR */ |
173 | struct pci_dev *pci_dev; |
174 | struct ismt_desc *hw; /* descriptor virt base addr */ |
175 | dma_addr_t io_rng_dma; /* descriptor HW base addr */ |
176 | u8 head; /* ring buffer head pointer */ |
177 | struct completion cmp; /* interrupt completion */ |
178 | u8 buffer[I2C_SMBUS_BLOCK_MAX + 16]; /* temp R/W data buffer */ |
179 | dma_addr_t log_dma; |
180 | u32 *log; |
181 | }; |
182 | |
183 | static const struct pci_device_id ismt_ids[] = { |
184 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT0) }, |
185 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT1) }, |
186 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMT) }, |
187 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMT) }, |
188 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EBG_SMT) }, |
189 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMT) }, |
190 | { 0, } |
191 | }; |
192 | |
193 | MODULE_DEVICE_TABLE(pci, ismt_ids); |
194 | |
195 | /* Bus speed control bits for slow debuggers - refer to the docs for usage */ |
196 | static unsigned int bus_speed; |
197 | module_param(bus_speed, uint, S_IRUGO); |
198 | MODULE_PARM_DESC(bus_speed, "Bus Speed in kHz (0 = BIOS default)" ); |
199 | |
200 | /** |
201 | * __ismt_desc_dump() - dump the contents of a specific descriptor |
202 | * @dev: the iSMT device |
203 | * @desc: the iSMT hardware descriptor |
204 | */ |
205 | static void __ismt_desc_dump(struct device *dev, const struct ismt_desc *desc) |
206 | { |
207 | |
208 | dev_dbg(dev, "Descriptor struct: %p\n" , desc); |
209 | dev_dbg(dev, "\ttgtaddr_rw=0x%02X\n" , desc->tgtaddr_rw); |
210 | dev_dbg(dev, "\twr_len_cmd=0x%02X\n" , desc->wr_len_cmd); |
211 | dev_dbg(dev, "\trd_len= 0x%02X\n" , desc->rd_len); |
212 | dev_dbg(dev, "\tcontrol= 0x%02X\n" , desc->control); |
213 | dev_dbg(dev, "\tstatus= 0x%02X\n" , desc->status); |
214 | dev_dbg(dev, "\tretry= 0x%02X\n" , desc->retry); |
215 | dev_dbg(dev, "\trxbytes= 0x%02X\n" , desc->rxbytes); |
216 | dev_dbg(dev, "\ttxbytes= 0x%02X\n" , desc->txbytes); |
217 | dev_dbg(dev, "\tdptr_low= 0x%08X\n" , desc->dptr_low); |
218 | dev_dbg(dev, "\tdptr_high= 0x%08X\n" , desc->dptr_high); |
219 | } |
220 | /** |
221 | * ismt_desc_dump() - dump the contents of a descriptor for debug purposes |
222 | * @priv: iSMT private data |
223 | */ |
224 | static void ismt_desc_dump(struct ismt_priv *priv) |
225 | { |
226 | struct device *dev = &priv->pci_dev->dev; |
227 | struct ismt_desc *desc = &priv->hw[priv->head]; |
228 | |
229 | dev_dbg(dev, "Dump of the descriptor struct: 0x%X\n" , priv->head); |
230 | __ismt_desc_dump(dev, desc); |
231 | } |
232 | |
233 | /** |
234 | * ismt_gen_reg_dump() - dump the iSMT General Registers |
235 | * @priv: iSMT private data |
236 | */ |
237 | static void ismt_gen_reg_dump(struct ismt_priv *priv) |
238 | { |
239 | struct device *dev = &priv->pci_dev->dev; |
240 | |
241 | dev_dbg(dev, "Dump of the iSMT General Registers\n" ); |
242 | dev_dbg(dev, " GCTRL.... : (0x%p)=0x%X\n" , |
243 | priv->smba + ISMT_GR_GCTRL, |
244 | readl(priv->smba + ISMT_GR_GCTRL)); |
245 | dev_dbg(dev, " SMTICL... : (0x%p)=0x%016llX\n" , |
246 | priv->smba + ISMT_GR_SMTICL, |
247 | (long long unsigned int)readq(priv->smba + ISMT_GR_SMTICL)); |
248 | dev_dbg(dev, " ERRINTMSK : (0x%p)=0x%X\n" , |
249 | priv->smba + ISMT_GR_ERRINTMSK, |
250 | readl(priv->smba + ISMT_GR_ERRINTMSK)); |
251 | dev_dbg(dev, " ERRAERMSK : (0x%p)=0x%X\n" , |
252 | priv->smba + ISMT_GR_ERRAERMSK, |
253 | readl(priv->smba + ISMT_GR_ERRAERMSK)); |
254 | dev_dbg(dev, " ERRSTS... : (0x%p)=0x%X\n" , |
255 | priv->smba + ISMT_GR_ERRSTS, |
256 | readl(priv->smba + ISMT_GR_ERRSTS)); |
257 | dev_dbg(dev, " ERRINFO.. : (0x%p)=0x%X\n" , |
258 | priv->smba + ISMT_GR_ERRINFO, |
259 | readl(priv->smba + ISMT_GR_ERRINFO)); |
260 | } |
261 | |
262 | /** |
263 | * ismt_mstr_reg_dump() - dump the iSMT Master Registers |
264 | * @priv: iSMT private data |
265 | */ |
266 | static void ismt_mstr_reg_dump(struct ismt_priv *priv) |
267 | { |
268 | struct device *dev = &priv->pci_dev->dev; |
269 | |
270 | dev_dbg(dev, "Dump of the iSMT Master Registers\n" ); |
271 | dev_dbg(dev, " MDBA..... : (0x%p)=0x%016llX\n" , |
272 | priv->smba + ISMT_MSTR_MDBA, |
273 | (long long unsigned int)readq(priv->smba + ISMT_MSTR_MDBA)); |
274 | dev_dbg(dev, " MCTRL.... : (0x%p)=0x%X\n" , |
275 | priv->smba + ISMT_MSTR_MCTRL, |
276 | readl(priv->smba + ISMT_MSTR_MCTRL)); |
277 | dev_dbg(dev, " MSTS..... : (0x%p)=0x%X\n" , |
278 | priv->smba + ISMT_MSTR_MSTS, |
279 | readl(priv->smba + ISMT_MSTR_MSTS)); |
280 | dev_dbg(dev, " MDS...... : (0x%p)=0x%X\n" , |
281 | priv->smba + ISMT_MSTR_MDS, |
282 | readl(priv->smba + ISMT_MSTR_MDS)); |
283 | dev_dbg(dev, " RPOLICY.. : (0x%p)=0x%X\n" , |
284 | priv->smba + ISMT_MSTR_RPOLICY, |
285 | readl(priv->smba + ISMT_MSTR_RPOLICY)); |
286 | dev_dbg(dev, " SPGT..... : (0x%p)=0x%X\n" , |
287 | priv->smba + ISMT_SPGT, |
288 | readl(priv->smba + ISMT_SPGT)); |
289 | } |
290 | |
291 | /** |
292 | * ismt_submit_desc() - add a descriptor to the ring |
293 | * @priv: iSMT private data |
294 | */ |
295 | static void ismt_submit_desc(struct ismt_priv *priv) |
296 | { |
297 | uint fmhp; |
298 | uint val; |
299 | |
300 | ismt_desc_dump(priv); |
301 | ismt_gen_reg_dump(priv); |
302 | ismt_mstr_reg_dump(priv); |
303 | |
304 | /* Set the FMHP (Firmware Master Head Pointer)*/ |
305 | fmhp = ((priv->head + 1) % ISMT_DESC_ENTRIES) << 16; |
306 | val = readl(addr: priv->smba + ISMT_MSTR_MCTRL); |
307 | writel(val: (val & ~ISMT_MCTRL_FMHP) | fmhp, |
308 | addr: priv->smba + ISMT_MSTR_MCTRL); |
309 | |
310 | /* Set the start bit */ |
311 | val = readl(addr: priv->smba + ISMT_MSTR_MCTRL); |
312 | writel(val: val | ISMT_MCTRL_SS, |
313 | addr: priv->smba + ISMT_MSTR_MCTRL); |
314 | } |
315 | |
316 | /** |
317 | * ismt_process_desc() - handle the completion of the descriptor |
318 | * @desc: the iSMT hardware descriptor |
319 | * @data: data buffer from the upper layer |
320 | * @priv: ismt_priv struct holding our dma buffer |
321 | * @size: SMBus transaction type |
322 | * @read_write: flag to indicate if this is a read or write |
323 | */ |
324 | static int ismt_process_desc(const struct ismt_desc *desc, |
325 | union i2c_smbus_data *data, |
326 | struct ismt_priv *priv, int size, |
327 | char read_write) |
328 | { |
329 | u8 *dma_buffer = PTR_ALIGN(&priv->buffer[0], 16); |
330 | |
331 | dev_dbg(&priv->pci_dev->dev, "Processing completed descriptor\n" ); |
332 | __ismt_desc_dump(dev: &priv->pci_dev->dev, desc); |
333 | ismt_gen_reg_dump(priv); |
334 | ismt_mstr_reg_dump(priv); |
335 | |
336 | if (desc->status & ISMT_DESC_SCS) { |
337 | if (read_write == I2C_SMBUS_WRITE && |
338 | size != I2C_SMBUS_PROC_CALL && |
339 | size != I2C_SMBUS_BLOCK_PROC_CALL) |
340 | return 0; |
341 | |
342 | switch (size) { |
343 | case I2C_SMBUS_BYTE: |
344 | case I2C_SMBUS_BYTE_DATA: |
345 | data->byte = dma_buffer[0]; |
346 | break; |
347 | case I2C_SMBUS_WORD_DATA: |
348 | case I2C_SMBUS_PROC_CALL: |
349 | data->word = dma_buffer[0] | (dma_buffer[1] << 8); |
350 | break; |
351 | case I2C_SMBUS_BLOCK_DATA: |
352 | case I2C_SMBUS_BLOCK_PROC_CALL: |
353 | if (desc->rxbytes != dma_buffer[0] + 1) |
354 | return -EMSGSIZE; |
355 | |
356 | memcpy(data->block, dma_buffer, desc->rxbytes); |
357 | break; |
358 | case I2C_SMBUS_I2C_BLOCK_DATA: |
359 | memcpy(&data->block[1], dma_buffer, desc->rxbytes); |
360 | data->block[0] = desc->rxbytes; |
361 | break; |
362 | } |
363 | return 0; |
364 | } |
365 | |
366 | if (likely(desc->status & ISMT_DESC_NAK)) |
367 | return -ENXIO; |
368 | |
369 | if (desc->status & ISMT_DESC_CRC) |
370 | return -EBADMSG; |
371 | |
372 | if (desc->status & ISMT_DESC_COL) |
373 | return -EAGAIN; |
374 | |
375 | if (desc->status & ISMT_DESC_LPR) |
376 | return -EPROTO; |
377 | |
378 | if (desc->status & (ISMT_DESC_DLTO | ISMT_DESC_CLTO)) |
379 | return -ETIMEDOUT; |
380 | |
381 | return -EIO; |
382 | } |
383 | |
384 | /** |
385 | * ismt_access() - process an SMBus command |
386 | * @adap: the i2c host adapter |
387 | * @addr: address of the i2c/SMBus target |
388 | * @flags: command options |
389 | * @read_write: read from or write to device |
390 | * @command: the i2c/SMBus command to issue |
391 | * @size: SMBus transaction type |
392 | * @data: read/write data buffer |
393 | */ |
394 | static int ismt_access(struct i2c_adapter *adap, u16 addr, |
395 | unsigned short flags, char read_write, u8 command, |
396 | int size, union i2c_smbus_data *data) |
397 | { |
398 | int ret; |
399 | unsigned long time_left; |
400 | dma_addr_t dma_addr = 0; /* address of the data buffer */ |
401 | u8 dma_size = 0; |
402 | enum dma_data_direction dma_direction = 0; |
403 | struct ismt_desc *desc; |
404 | struct ismt_priv *priv = i2c_get_adapdata(adap); |
405 | struct device *dev = &priv->pci_dev->dev; |
406 | u8 *dma_buffer = PTR_ALIGN(&priv->buffer[0], 16); |
407 | |
408 | desc = &priv->hw[priv->head]; |
409 | |
410 | /* Initialize the DMA buffer */ |
411 | memset(priv->buffer, 0, sizeof(priv->buffer)); |
412 | |
413 | /* Initialize the descriptor */ |
414 | memset(desc, 0, sizeof(struct ismt_desc)); |
415 | desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, read_write); |
416 | |
417 | /* Always clear the log entries */ |
418 | memset(priv->log, 0, ISMT_LOG_ENTRIES * sizeof(u32)); |
419 | |
420 | /* Initialize common control bits */ |
421 | if (likely(pci_dev_msi_enabled(priv->pci_dev))) |
422 | desc->control = ISMT_DESC_INT | ISMT_DESC_FAIR; |
423 | else |
424 | desc->control = ISMT_DESC_FAIR; |
425 | |
426 | if ((flags & I2C_CLIENT_PEC) && (size != I2C_SMBUS_QUICK) |
427 | && (size != I2C_SMBUS_I2C_BLOCK_DATA)) |
428 | desc->control |= ISMT_DESC_PEC; |
429 | |
430 | switch (size) { |
431 | case I2C_SMBUS_QUICK: |
432 | dev_dbg(dev, "I2C_SMBUS_QUICK\n" ); |
433 | break; |
434 | |
435 | case I2C_SMBUS_BYTE: |
436 | if (read_write == I2C_SMBUS_WRITE) { |
437 | /* |
438 | * Send Byte |
439 | * The command field contains the write data |
440 | */ |
441 | dev_dbg(dev, "I2C_SMBUS_BYTE: WRITE\n" ); |
442 | desc->control |= ISMT_DESC_CWRL; |
443 | desc->wr_len_cmd = command; |
444 | } else { |
445 | /* Receive Byte */ |
446 | dev_dbg(dev, "I2C_SMBUS_BYTE: READ\n" ); |
447 | dma_size = 1; |
448 | dma_direction = DMA_FROM_DEVICE; |
449 | desc->rd_len = 1; |
450 | } |
451 | break; |
452 | |
453 | case I2C_SMBUS_BYTE_DATA: |
454 | if (read_write == I2C_SMBUS_WRITE) { |
455 | /* |
456 | * Write Byte |
457 | * Command plus 1 data byte |
458 | */ |
459 | dev_dbg(dev, "I2C_SMBUS_BYTE_DATA: WRITE\n" ); |
460 | desc->wr_len_cmd = 2; |
461 | dma_size = 2; |
462 | dma_direction = DMA_TO_DEVICE; |
463 | dma_buffer[0] = command; |
464 | dma_buffer[1] = data->byte; |
465 | } else { |
466 | /* Read Byte */ |
467 | dev_dbg(dev, "I2C_SMBUS_BYTE_DATA: READ\n" ); |
468 | desc->control |= ISMT_DESC_CWRL; |
469 | desc->wr_len_cmd = command; |
470 | desc->rd_len = 1; |
471 | dma_size = 1; |
472 | dma_direction = DMA_FROM_DEVICE; |
473 | } |
474 | break; |
475 | |
476 | case I2C_SMBUS_WORD_DATA: |
477 | if (read_write == I2C_SMBUS_WRITE) { |
478 | /* Write Word */ |
479 | dev_dbg(dev, "I2C_SMBUS_WORD_DATA: WRITE\n" ); |
480 | desc->wr_len_cmd = 3; |
481 | dma_size = 3; |
482 | dma_direction = DMA_TO_DEVICE; |
483 | dma_buffer[0] = command; |
484 | dma_buffer[1] = data->word & 0xff; |
485 | dma_buffer[2] = data->word >> 8; |
486 | } else { |
487 | /* Read Word */ |
488 | dev_dbg(dev, "I2C_SMBUS_WORD_DATA: READ\n" ); |
489 | desc->wr_len_cmd = command; |
490 | desc->control |= ISMT_DESC_CWRL; |
491 | desc->rd_len = 2; |
492 | dma_size = 2; |
493 | dma_direction = DMA_FROM_DEVICE; |
494 | } |
495 | break; |
496 | |
497 | case I2C_SMBUS_PROC_CALL: |
498 | dev_dbg(dev, "I2C_SMBUS_PROC_CALL\n" ); |
499 | desc->wr_len_cmd = 3; |
500 | desc->rd_len = 2; |
501 | dma_size = 3; |
502 | dma_direction = DMA_BIDIRECTIONAL; |
503 | dma_buffer[0] = command; |
504 | dma_buffer[1] = data->word & 0xff; |
505 | dma_buffer[2] = data->word >> 8; |
506 | break; |
507 | |
508 | case I2C_SMBUS_BLOCK_DATA: |
509 | if (read_write == I2C_SMBUS_WRITE) { |
510 | /* Block Write */ |
511 | dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA: WRITE\n" ); |
512 | if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX) |
513 | return -EINVAL; |
514 | |
515 | dma_size = data->block[0] + 1; |
516 | dma_direction = DMA_TO_DEVICE; |
517 | desc->wr_len_cmd = dma_size; |
518 | desc->control |= ISMT_DESC_BLK; |
519 | dma_buffer[0] = command; |
520 | memcpy(&dma_buffer[1], &data->block[1], dma_size - 1); |
521 | } else { |
522 | /* Block Read */ |
523 | dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA: READ\n" ); |
524 | dma_size = I2C_SMBUS_BLOCK_MAX; |
525 | dma_direction = DMA_FROM_DEVICE; |
526 | desc->rd_len = dma_size; |
527 | desc->wr_len_cmd = command; |
528 | desc->control |= (ISMT_DESC_BLK | ISMT_DESC_CWRL); |
529 | } |
530 | break; |
531 | |
532 | case I2C_SMBUS_BLOCK_PROC_CALL: |
533 | dev_dbg(dev, "I2C_SMBUS_BLOCK_PROC_CALL\n" ); |
534 | if (data->block[0] > I2C_SMBUS_BLOCK_MAX) |
535 | return -EINVAL; |
536 | |
537 | dma_size = I2C_SMBUS_BLOCK_MAX; |
538 | desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, 1); |
539 | desc->wr_len_cmd = data->block[0] + 1; |
540 | desc->rd_len = dma_size; |
541 | desc->control |= ISMT_DESC_BLK; |
542 | dma_direction = DMA_BIDIRECTIONAL; |
543 | dma_buffer[0] = command; |
544 | memcpy(&dma_buffer[1], &data->block[1], data->block[0]); |
545 | break; |
546 | |
547 | case I2C_SMBUS_I2C_BLOCK_DATA: |
548 | /* Make sure the length is valid */ |
549 | if (data->block[0] < 1) |
550 | data->block[0] = 1; |
551 | |
552 | if (data->block[0] > I2C_SMBUS_BLOCK_MAX) |
553 | data->block[0] = I2C_SMBUS_BLOCK_MAX; |
554 | |
555 | if (read_write == I2C_SMBUS_WRITE) { |
556 | /* i2c Block Write */ |
557 | dev_dbg(dev, "I2C_SMBUS_I2C_BLOCK_DATA: WRITE\n" ); |
558 | dma_size = data->block[0] + 1; |
559 | dma_direction = DMA_TO_DEVICE; |
560 | desc->wr_len_cmd = dma_size; |
561 | desc->control |= ISMT_DESC_I2C; |
562 | dma_buffer[0] = command; |
563 | memcpy(&dma_buffer[1], &data->block[1], dma_size - 1); |
564 | } else { |
565 | /* i2c Block Read */ |
566 | dev_dbg(dev, "I2C_SMBUS_I2C_BLOCK_DATA: READ\n" ); |
567 | dma_size = data->block[0]; |
568 | dma_direction = DMA_FROM_DEVICE; |
569 | desc->rd_len = dma_size; |
570 | desc->wr_len_cmd = command; |
571 | desc->control |= (ISMT_DESC_I2C | ISMT_DESC_CWRL); |
572 | /* |
573 | * Per the "Table 15-15. I2C Commands", |
574 | * in the External Design Specification (EDS), |
575 | * (Document Number: 508084, Revision: 2.0), |
576 | * the _rw bit must be 0 |
577 | */ |
578 | desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, 0); |
579 | } |
580 | break; |
581 | |
582 | default: |
583 | dev_err(dev, "Unsupported transaction %d\n" , |
584 | size); |
585 | return -EOPNOTSUPP; |
586 | } |
587 | |
588 | /* map the data buffer */ |
589 | if (dma_size != 0) { |
590 | dev_dbg(dev, " dev=%p\n" , dev); |
591 | dev_dbg(dev, " data=%p\n" , data); |
592 | dev_dbg(dev, " dma_buffer=%p\n" , dma_buffer); |
593 | dev_dbg(dev, " dma_size=%d\n" , dma_size); |
594 | dev_dbg(dev, " dma_direction=%d\n" , dma_direction); |
595 | |
596 | dma_addr = dma_map_single(dev, |
597 | dma_buffer, |
598 | dma_size, |
599 | dma_direction); |
600 | |
601 | if (dma_mapping_error(dev, dma_addr)) { |
602 | dev_err(dev, "Error in mapping dma buffer %p\n" , |
603 | dma_buffer); |
604 | return -EIO; |
605 | } |
606 | |
607 | dev_dbg(dev, " dma_addr = %pad\n" , &dma_addr); |
608 | |
609 | desc->dptr_low = lower_32_bits(dma_addr); |
610 | desc->dptr_high = upper_32_bits(dma_addr); |
611 | } |
612 | |
613 | reinit_completion(x: &priv->cmp); |
614 | |
615 | /* Add the descriptor */ |
616 | ismt_submit_desc(priv); |
617 | |
618 | /* Now we wait for interrupt completion, 1s */ |
619 | time_left = wait_for_completion_timeout(x: &priv->cmp, HZ*1); |
620 | |
621 | /* unmap the data buffer */ |
622 | if (dma_size != 0) |
623 | dma_unmap_single(dev, dma_addr, dma_size, dma_direction); |
624 | |
625 | if (unlikely(!time_left)) { |
626 | dev_err(dev, "completion wait timed out\n" ); |
627 | ret = -ETIMEDOUT; |
628 | goto out; |
629 | } |
630 | |
631 | /* do any post processing of the descriptor here */ |
632 | ret = ismt_process_desc(desc, data, priv, size, read_write); |
633 | |
634 | out: |
635 | /* Update the ring pointer */ |
636 | priv->head++; |
637 | priv->head %= ISMT_DESC_ENTRIES; |
638 | |
639 | return ret; |
640 | } |
641 | |
642 | /** |
643 | * ismt_func() - report which i2c commands are supported by this adapter |
644 | * @adap: the i2c host adapter |
645 | */ |
646 | static u32 ismt_func(struct i2c_adapter *adap) |
647 | { |
648 | return I2C_FUNC_SMBUS_QUICK | |
649 | I2C_FUNC_SMBUS_BYTE | |
650 | I2C_FUNC_SMBUS_BYTE_DATA | |
651 | I2C_FUNC_SMBUS_WORD_DATA | |
652 | I2C_FUNC_SMBUS_PROC_CALL | |
653 | I2C_FUNC_SMBUS_BLOCK_PROC_CALL | |
654 | I2C_FUNC_SMBUS_BLOCK_DATA | |
655 | I2C_FUNC_SMBUS_I2C_BLOCK | |
656 | I2C_FUNC_SMBUS_PEC; |
657 | } |
658 | |
659 | static const struct i2c_algorithm smbus_algorithm = { |
660 | .smbus_xfer = ismt_access, |
661 | .functionality = ismt_func, |
662 | }; |
663 | |
664 | /** |
665 | * ismt_handle_isr() - interrupt handler bottom half |
666 | * @priv: iSMT private data |
667 | */ |
668 | static irqreturn_t ismt_handle_isr(struct ismt_priv *priv) |
669 | { |
670 | complete(&priv->cmp); |
671 | |
672 | return IRQ_HANDLED; |
673 | } |
674 | |
675 | |
676 | /** |
677 | * ismt_do_interrupt() - IRQ interrupt handler |
678 | * @vec: interrupt vector |
679 | * @data: iSMT private data |
680 | */ |
681 | static irqreturn_t ismt_do_interrupt(int vec, void *data) |
682 | { |
683 | u32 val; |
684 | struct ismt_priv *priv = data; |
685 | |
686 | /* |
687 | * check to see it's our interrupt, return IRQ_NONE if not ours |
688 | * since we are sharing interrupt |
689 | */ |
690 | val = readl(addr: priv->smba + ISMT_MSTR_MSTS); |
691 | |
692 | if (!(val & (ISMT_MSTS_MIS | ISMT_MSTS_MEIS))) |
693 | return IRQ_NONE; |
694 | else |
695 | writel(val: val | ISMT_MSTS_MIS | ISMT_MSTS_MEIS, |
696 | addr: priv->smba + ISMT_MSTR_MSTS); |
697 | |
698 | return ismt_handle_isr(priv); |
699 | } |
700 | |
701 | /** |
702 | * ismt_do_msi_interrupt() - MSI interrupt handler |
703 | * @vec: interrupt vector |
704 | * @data: iSMT private data |
705 | */ |
706 | static irqreturn_t ismt_do_msi_interrupt(int vec, void *data) |
707 | { |
708 | return ismt_handle_isr(priv: data); |
709 | } |
710 | |
711 | /** |
712 | * ismt_hw_init() - initialize the iSMT hardware |
713 | * @priv: iSMT private data |
714 | */ |
715 | static void ismt_hw_init(struct ismt_priv *priv) |
716 | { |
717 | u32 val; |
718 | struct device *dev = &priv->pci_dev->dev; |
719 | |
720 | /* initialize the Master Descriptor Base Address (MDBA) */ |
721 | writeq(val: priv->io_rng_dma, addr: priv->smba + ISMT_MSTR_MDBA); |
722 | |
723 | writeq(val: priv->log_dma, addr: priv->smba + ISMT_GR_SMTICL); |
724 | |
725 | /* initialize the Master Control Register (MCTRL) */ |
726 | writel(ISMT_MCTRL_MEIE, addr: priv->smba + ISMT_MSTR_MCTRL); |
727 | |
728 | /* initialize the Master Status Register (MSTS) */ |
729 | writel(val: 0, addr: priv->smba + ISMT_MSTR_MSTS); |
730 | |
731 | /* initialize the Master Descriptor Size (MDS) */ |
732 | val = readl(addr: priv->smba + ISMT_MSTR_MDS); |
733 | writel(val: (val & ~ISMT_MDS_MASK) | (ISMT_DESC_ENTRIES - 1), |
734 | addr: priv->smba + ISMT_MSTR_MDS); |
735 | |
736 | /* |
737 | * Set the SMBus speed (could use this for slow HW debuggers) |
738 | */ |
739 | |
740 | val = readl(addr: priv->smba + ISMT_SPGT); |
741 | |
742 | switch (bus_speed) { |
743 | case 0: |
744 | break; |
745 | |
746 | case 80: |
747 | dev_dbg(dev, "Setting SMBus clock to 80 kHz\n" ); |
748 | writel(val: ((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_80K), |
749 | addr: priv->smba + ISMT_SPGT); |
750 | break; |
751 | |
752 | case 100: |
753 | dev_dbg(dev, "Setting SMBus clock to 100 kHz\n" ); |
754 | writel(val: ((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_100K), |
755 | addr: priv->smba + ISMT_SPGT); |
756 | break; |
757 | |
758 | case 400: |
759 | dev_dbg(dev, "Setting SMBus clock to 400 kHz\n" ); |
760 | writel(val: ((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_400K), |
761 | addr: priv->smba + ISMT_SPGT); |
762 | break; |
763 | |
764 | case 1000: |
765 | dev_dbg(dev, "Setting SMBus clock to 1000 kHz\n" ); |
766 | writel(val: ((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_1M), |
767 | addr: priv->smba + ISMT_SPGT); |
768 | break; |
769 | |
770 | default: |
771 | dev_warn(dev, "Invalid SMBus clock speed, only 0, 80, 100, 400, and 1000 are valid\n" ); |
772 | break; |
773 | } |
774 | |
775 | val = readl(addr: priv->smba + ISMT_SPGT); |
776 | |
777 | switch (val & ISMT_SPGT_SPD_MASK) { |
778 | case ISMT_SPGT_SPD_80K: |
779 | bus_speed = 80; |
780 | break; |
781 | case ISMT_SPGT_SPD_100K: |
782 | bus_speed = 100; |
783 | break; |
784 | case ISMT_SPGT_SPD_400K: |
785 | bus_speed = 400; |
786 | break; |
787 | case ISMT_SPGT_SPD_1M: |
788 | bus_speed = 1000; |
789 | break; |
790 | } |
791 | dev_dbg(dev, "SMBus clock is running at %d kHz\n" , bus_speed); |
792 | } |
793 | |
794 | /** |
795 | * ismt_dev_init() - initialize the iSMT data structures |
796 | * @priv: iSMT private data |
797 | */ |
798 | static int ismt_dev_init(struct ismt_priv *priv) |
799 | { |
800 | /* allocate memory for the descriptor */ |
801 | priv->hw = dmam_alloc_coherent(dev: &priv->pci_dev->dev, |
802 | size: (ISMT_DESC_ENTRIES |
803 | * sizeof(struct ismt_desc)), |
804 | dma_handle: &priv->io_rng_dma, |
805 | GFP_KERNEL); |
806 | if (!priv->hw) |
807 | return -ENOMEM; |
808 | |
809 | priv->head = 0; |
810 | init_completion(x: &priv->cmp); |
811 | |
812 | priv->log = dmam_alloc_coherent(dev: &priv->pci_dev->dev, |
813 | ISMT_LOG_ENTRIES * sizeof(u32), |
814 | dma_handle: &priv->log_dma, GFP_KERNEL); |
815 | if (!priv->log) |
816 | return -ENOMEM; |
817 | |
818 | return 0; |
819 | } |
820 | |
821 | /** |
822 | * ismt_int_init() - initialize interrupts |
823 | * @priv: iSMT private data |
824 | */ |
825 | static int ismt_int_init(struct ismt_priv *priv) |
826 | { |
827 | int err; |
828 | |
829 | /* Try using MSI interrupts */ |
830 | err = pci_enable_msi(dev: priv->pci_dev); |
831 | if (err) |
832 | goto intx; |
833 | |
834 | err = devm_request_irq(dev: &priv->pci_dev->dev, |
835 | irq: priv->pci_dev->irq, |
836 | handler: ismt_do_msi_interrupt, |
837 | irqflags: 0, |
838 | devname: "ismt-msi" , |
839 | dev_id: priv); |
840 | if (err) { |
841 | pci_disable_msi(dev: priv->pci_dev); |
842 | goto intx; |
843 | } |
844 | |
845 | return 0; |
846 | |
847 | /* Try using legacy interrupts */ |
848 | intx: |
849 | dev_warn(&priv->pci_dev->dev, |
850 | "Unable to use MSI interrupts, falling back to legacy\n" ); |
851 | |
852 | err = devm_request_irq(dev: &priv->pci_dev->dev, |
853 | irq: priv->pci_dev->irq, |
854 | handler: ismt_do_interrupt, |
855 | IRQF_SHARED, |
856 | devname: "ismt-intx" , |
857 | dev_id: priv); |
858 | if (err) { |
859 | dev_err(&priv->pci_dev->dev, "no usable interrupts\n" ); |
860 | return err; |
861 | } |
862 | |
863 | return 0; |
864 | } |
865 | |
866 | static struct pci_driver ismt_driver; |
867 | |
868 | /** |
869 | * ismt_probe() - probe for iSMT devices |
870 | * @pdev: PCI-Express device |
871 | * @id: PCI-Express device ID |
872 | */ |
873 | static int |
874 | ismt_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
875 | { |
876 | int err; |
877 | struct ismt_priv *priv; |
878 | unsigned long start, len; |
879 | |
880 | priv = devm_kzalloc(dev: &pdev->dev, size: sizeof(*priv), GFP_KERNEL); |
881 | if (!priv) |
882 | return -ENOMEM; |
883 | |
884 | pci_set_drvdata(pdev, data: priv); |
885 | |
886 | i2c_set_adapdata(adap: &priv->adapter, data: priv); |
887 | priv->adapter.owner = THIS_MODULE; |
888 | priv->adapter.class = I2C_CLASS_HWMON; |
889 | priv->adapter.algo = &smbus_algorithm; |
890 | priv->adapter.dev.parent = &pdev->dev; |
891 | ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&pdev->dev)); |
892 | priv->adapter.retries = ISMT_MAX_RETRIES; |
893 | |
894 | priv->pci_dev = pdev; |
895 | |
896 | err = pcim_enable_device(pdev); |
897 | if (err) { |
898 | dev_err(&pdev->dev, "Failed to enable SMBus PCI device (%d)\n" , |
899 | err); |
900 | return err; |
901 | } |
902 | |
903 | /* enable bus mastering */ |
904 | pci_set_master(dev: pdev); |
905 | |
906 | /* Determine the address of the SMBus area */ |
907 | start = pci_resource_start(pdev, SMBBAR); |
908 | len = pci_resource_len(pdev, SMBBAR); |
909 | if (!start || !len) { |
910 | dev_err(&pdev->dev, |
911 | "SMBus base address uninitialized, upgrade BIOS\n" ); |
912 | return -ENODEV; |
913 | } |
914 | |
915 | snprintf(buf: priv->adapter.name, size: sizeof(priv->adapter.name), |
916 | fmt: "SMBus iSMT adapter at %lx" , start); |
917 | |
918 | dev_dbg(&priv->pci_dev->dev, " start=0x%lX\n" , start); |
919 | dev_dbg(&priv->pci_dev->dev, " len=0x%lX\n" , len); |
920 | |
921 | err = acpi_check_resource_conflict(res: &pdev->resource[SMBBAR]); |
922 | if (err) { |
923 | dev_err(&pdev->dev, "ACPI resource conflict!\n" ); |
924 | return err; |
925 | } |
926 | |
927 | err = pci_request_region(pdev, SMBBAR, ismt_driver.name); |
928 | if (err) { |
929 | dev_err(&pdev->dev, |
930 | "Failed to request SMBus region 0x%lx-0x%lx\n" , |
931 | start, start + len); |
932 | return err; |
933 | } |
934 | |
935 | priv->smba = pcim_iomap(pdev, SMBBAR, maxlen: len); |
936 | if (!priv->smba) { |
937 | dev_err(&pdev->dev, "Unable to ioremap SMBus BAR\n" ); |
938 | return -ENODEV; |
939 | } |
940 | |
941 | err = dma_set_mask_and_coherent(dev: &pdev->dev, DMA_BIT_MASK(64)); |
942 | if (err) { |
943 | dev_err(&pdev->dev, "dma_set_mask fail\n" ); |
944 | return -ENODEV; |
945 | } |
946 | |
947 | err = ismt_dev_init(priv); |
948 | if (err) |
949 | return err; |
950 | |
951 | ismt_hw_init(priv); |
952 | |
953 | err = ismt_int_init(priv); |
954 | if (err) |
955 | return err; |
956 | |
957 | err = i2c_add_adapter(adap: &priv->adapter); |
958 | if (err) |
959 | return -ENODEV; |
960 | return 0; |
961 | } |
962 | |
963 | /** |
964 | * ismt_remove() - release driver resources |
965 | * @pdev: PCI-Express device |
966 | */ |
967 | static void ismt_remove(struct pci_dev *pdev) |
968 | { |
969 | struct ismt_priv *priv = pci_get_drvdata(pdev); |
970 | |
971 | i2c_del_adapter(adap: &priv->adapter); |
972 | } |
973 | |
974 | static struct pci_driver ismt_driver = { |
975 | .name = "ismt_smbus" , |
976 | .id_table = ismt_ids, |
977 | .probe = ismt_probe, |
978 | .remove = ismt_remove, |
979 | }; |
980 | |
981 | module_pci_driver(ismt_driver); |
982 | |
983 | MODULE_LICENSE("Dual BSD/GPL" ); |
984 | MODULE_AUTHOR("Bill E. Brown <bill.e.brown@intel.com>" ); |
985 | MODULE_DESCRIPTION("Intel SMBus Message Transport (iSMT) driver" ); |
986 | |