1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Microchip PCI1XXXX I2C adapter driver for PCIe Switch |
4 | * which has I2C controller in one of its downstream functions |
5 | * |
6 | * Copyright (C) 2021 - 2022 Microchip Technology Inc. |
7 | * |
8 | * Authors: Tharun Kumar P <tharunkumar.pasumarthi@microchip.com> |
9 | * Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com> |
10 | */ |
11 | |
12 | #include <linux/bits.h> |
13 | #include <linux/delay.h> |
14 | #include <linux/i2c.h> |
15 | #include <linux/i2c-smbus.h> |
16 | #include <linux/interrupt.h> |
17 | #include <linux/kernel.h> |
18 | #include <linux/module.h> |
19 | #include <linux/pci.h> |
20 | #include <linux/types.h> |
21 | |
22 | #define SMBUS_MAST_CORE_ADDR_BASE 0x00000 |
23 | #define SMBUS_MAST_SYS_REG_ADDR_BASE 0x01000 |
24 | |
25 | /* SMB register space. */ |
26 | #define SMB_CORE_CTRL_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x00) |
27 | |
28 | #define SMB_CORE_CTRL_ESO BIT(6) |
29 | #define SMB_CORE_CTRL_FW_ACK BIT(4) |
30 | #define SMB_CORE_CTRL_ACK BIT(0) |
31 | |
32 | #define SMB_CORE_CMD_REG_OFF3 (SMBUS_MAST_CORE_ADDR_BASE + 0x0F) |
33 | #define SMB_CORE_CMD_REG_OFF2 (SMBUS_MAST_CORE_ADDR_BASE + 0x0E) |
34 | #define SMB_CORE_CMD_REG_OFF1 (SMBUS_MAST_CORE_ADDR_BASE + 0x0D) |
35 | |
36 | #define SMB_CORE_CMD_READM BIT(4) |
37 | #define SMB_CORE_CMD_STOP BIT(2) |
38 | #define SMB_CORE_CMD_START BIT(0) |
39 | |
40 | #define SMB_CORE_CMD_REG_OFF0 (SMBUS_MAST_CORE_ADDR_BASE + 0x0C) |
41 | |
42 | #define SMB_CORE_CMD_M_PROCEED BIT(1) |
43 | #define SMB_CORE_CMD_M_RUN BIT(0) |
44 | |
45 | #define SMB_CORE_SR_HOLD_TIME_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x18) |
46 | |
47 | /* |
48 | * SR_HOLD_TIME_XK_TICKS field will indicate the number of ticks of the |
49 | * baud clock required to program 'Hold Time' at X KHz. |
50 | */ |
51 | #define SR_HOLD_TIME_100K_TICKS 150 |
52 | #define SR_HOLD_TIME_400K_TICKS 20 |
53 | #define SR_HOLD_TIME_1000K_TICKS 12 |
54 | |
55 | #define SMB_CORE_COMPLETION_REG_OFF3 (SMBUS_MAST_CORE_ADDR_BASE + 0x23) |
56 | |
57 | #define COMPLETION_MDONE BIT(6) |
58 | #define COMPLETION_IDLE BIT(5) |
59 | #define COMPLETION_MNAKX BIT(0) |
60 | |
61 | #define SMB_CORE_IDLE_SCALING_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x24) |
62 | |
63 | /* |
64 | * FAIR_BUS_IDLE_MIN_XK_TICKS field will indicate the number of ticks of |
65 | * the baud clock required to program 'fair idle delay' at X KHz. Fair idle |
66 | * delay establishes the MCTP T(IDLE_DELAY) period. |
67 | */ |
68 | #define FAIR_BUS_IDLE_MIN_100K_TICKS 992 |
69 | #define FAIR_BUS_IDLE_MIN_400K_TICKS 500 |
70 | #define FAIR_BUS_IDLE_MIN_1000K_TICKS 500 |
71 | |
72 | /* |
73 | * FAIR_IDLE_DELAY_XK_TICKS field will indicate the number of ticks of the |
74 | * baud clock required to satisfy the fairness protocol at X KHz. |
75 | */ |
76 | #define FAIR_IDLE_DELAY_100K_TICKS 963 |
77 | #define FAIR_IDLE_DELAY_400K_TICKS 156 |
78 | #define FAIR_IDLE_DELAY_1000K_TICKS 156 |
79 | |
80 | #define SMB_IDLE_SCALING_100K \ |
81 | ((FAIR_IDLE_DELAY_100K_TICKS << 16) | FAIR_BUS_IDLE_MIN_100K_TICKS) |
82 | #define SMB_IDLE_SCALING_400K \ |
83 | ((FAIR_IDLE_DELAY_400K_TICKS << 16) | FAIR_BUS_IDLE_MIN_400K_TICKS) |
84 | #define SMB_IDLE_SCALING_1000K \ |
85 | ((FAIR_IDLE_DELAY_1000K_TICKS << 16) | FAIR_BUS_IDLE_MIN_1000K_TICKS) |
86 | |
87 | #define SMB_CORE_CONFIG_REG3 (SMBUS_MAST_CORE_ADDR_BASE + 0x2B) |
88 | |
89 | #define SMB_CONFIG3_ENMI BIT(6) |
90 | #define SMB_CONFIG3_ENIDI BIT(5) |
91 | |
92 | #define SMB_CORE_CONFIG_REG2 (SMBUS_MAST_CORE_ADDR_BASE + 0x2A) |
93 | #define SMB_CORE_CONFIG_REG1 (SMBUS_MAST_CORE_ADDR_BASE + 0x29) |
94 | |
95 | #define SMB_CONFIG1_ASR BIT(7) |
96 | #define SMB_CONFIG1_ENAB BIT(2) |
97 | #define SMB_CONFIG1_RESET BIT(1) |
98 | #define SMB_CONFIG1_FEN BIT(0) |
99 | |
100 | #define SMB_CORE_BUS_CLK_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x2C) |
101 | |
102 | /* |
103 | * BUS_CLK_XK_LOW_PERIOD_TICKS field defines the number of I2C Baud Clock |
104 | * periods that make up the low phase of the I2C/SMBus bus clock at X KHz. |
105 | */ |
106 | #define BUS_CLK_100K_LOW_PERIOD_TICKS 156 |
107 | #define BUS_CLK_400K_LOW_PERIOD_TICKS 41 |
108 | #define BUS_CLK_1000K_LOW_PERIOD_TICKS 15 |
109 | |
110 | /* |
111 | * BUS_CLK_XK_HIGH_PERIOD_TICKS field defines the number of I2C Baud Clock |
112 | * periods that make up the high phase of the I2C/SMBus bus clock at X KHz. |
113 | */ |
114 | #define BUS_CLK_100K_HIGH_PERIOD_TICKS 154 |
115 | #define BUS_CLK_400K_HIGH_PERIOD_TICKS 35 |
116 | #define BUS_CLK_1000K_HIGH_PERIOD_TICKS 14 |
117 | |
118 | #define BUS_CLK_100K \ |
119 | ((BUS_CLK_100K_HIGH_PERIOD_TICKS << 8) | BUS_CLK_100K_LOW_PERIOD_TICKS) |
120 | #define BUS_CLK_400K \ |
121 | ((BUS_CLK_400K_HIGH_PERIOD_TICKS << 8) | BUS_CLK_400K_LOW_PERIOD_TICKS) |
122 | #define BUS_CLK_1000K \ |
123 | ((BUS_CLK_1000K_HIGH_PERIOD_TICKS << 8) | BUS_CLK_1000K_LOW_PERIOD_TICKS) |
124 | |
125 | #define SMB_CORE_CLK_SYNC_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x3C) |
126 | |
127 | /* |
128 | * CLK_SYNC_XK defines the number of clock cycles to sync up to the external |
129 | * clock before comparing the internal and external clocks for clock stretching |
130 | * at X KHz. |
131 | */ |
132 | #define CLK_SYNC_100K 4 |
133 | #define CLK_SYNC_400K 4 |
134 | #define CLK_SYNC_1000K 4 |
135 | |
136 | #define SMB_CORE_DATA_TIMING_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x40) |
137 | |
138 | /* |
139 | * |
140 | * FIRST_START_HOLD_XK_TICKS will indicate the number of ticks of the baud |
141 | * clock required to program 'FIRST_START_HOLD' timer at X KHz. This timer |
142 | * determines the SCLK hold time following SDAT driven low during the first |
143 | * START bit in a transfer. |
144 | */ |
145 | #define FIRST_START_HOLD_100K_TICKS 23 |
146 | #define FIRST_START_HOLD_400K_TICKS 8 |
147 | #define FIRST_START_HOLD_1000K_TICKS 12 |
148 | |
149 | /* |
150 | * STOP_SETUP_XK_TICKS will indicate the number of ticks of the baud clock |
151 | * required to program 'STOP_SETUP' timer at X KHz. This timer determines the |
152 | * SDAT setup time from the rising edge of SCLK for a STOP condition. |
153 | */ |
154 | #define STOP_SETUP_100K_TICKS 150 |
155 | #define STOP_SETUP_400K_TICKS 20 |
156 | #define STOP_SETUP_1000K_TICKS 12 |
157 | |
158 | /* |
159 | * RESTART_SETUP_XK_TICKS will indicate the number of ticks of the baud clock |
160 | * required to program 'RESTART_SETUP' timer at X KHz. This timer determines the |
161 | * SDAT setup time from the rising edge of SCLK for a repeated START condition. |
162 | */ |
163 | #define RESTART_SETUP_100K_TICKS 156 |
164 | #define RESTART_SETUP_400K_TICKS 20 |
165 | #define RESTART_SETUP_1000K_TICKS 12 |
166 | |
167 | /* |
168 | * DATA_HOLD_XK_TICKS will indicate the number of ticks of the baud clock |
169 | * required to program 'DATA_HOLD' timer at X KHz. This timer determines the |
170 | * SDAT hold time following SCLK driven low. |
171 | */ |
172 | #define DATA_HOLD_100K_TICKS 12 |
173 | #define DATA_HOLD_400K_TICKS 2 |
174 | #define DATA_HOLD_1000K_TICKS 2 |
175 | |
176 | #define DATA_TIMING_100K \ |
177 | ((FIRST_START_HOLD_100K_TICKS << 24) | (STOP_SETUP_100K_TICKS << 16) | \ |
178 | (RESTART_SETUP_100K_TICKS << 8) | DATA_HOLD_100K_TICKS) |
179 | #define DATA_TIMING_400K \ |
180 | ((FIRST_START_HOLD_400K_TICKS << 24) | (STOP_SETUP_400K_TICKS << 16) | \ |
181 | (RESTART_SETUP_400K_TICKS << 8) | DATA_HOLD_400K_TICKS) |
182 | #define DATA_TIMING_1000K \ |
183 | ((FIRST_START_HOLD_1000K_TICKS << 24) | (STOP_SETUP_1000K_TICKS << 16) | \ |
184 | (RESTART_SETUP_1000K_TICKS << 8) | DATA_HOLD_1000K_TICKS) |
185 | |
186 | #define SMB_CORE_TO_SCALING_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x44) |
187 | |
188 | /* |
189 | * BUS_IDLE_MIN_XK_TICKS defines Bus Idle Minimum Time. |
190 | * Bus Idle Minimum time = BUS_IDLE_MIN[7:0] x Baud_Clock_Period x |
191 | * (BUS_IDLE_MIN_XK_TICKS[7] ? 4,1) |
192 | */ |
193 | #define BUS_IDLE_MIN_100K_TICKS 36UL |
194 | #define BUS_IDLE_MIN_400K_TICKS 10UL |
195 | #define BUS_IDLE_MIN_1000K_TICKS 4UL |
196 | |
197 | /* |
198 | * CTRL_CUM_TIME_OUT_XK_TICKS defines SMBus Controller Cumulative Time-Out. |
199 | * SMBus Controller Cumulative Time-Out duration = |
200 | * CTRL_CUM_TIME_OUT_XK_TICKS[7:0] x Baud_Clock_Period x 2048 |
201 | */ |
202 | #define CTRL_CUM_TIME_OUT_100K_TICKS 76 |
203 | #define CTRL_CUM_TIME_OUT_400K_TICKS 76 |
204 | #define CTRL_CUM_TIME_OUT_1000K_TICKS 76 |
205 | |
206 | /* |
207 | * TARGET_CUM_TIME_OUT_XK_TICKS defines SMBus Target Cumulative Time-Out duration. |
208 | * SMBus Target Cumulative Time-Out duration = TARGET_CUM_TIME_OUT_XK_TICKS[7:0] x |
209 | * Baud_Clock_Period x 4096 |
210 | */ |
211 | #define TARGET_CUM_TIME_OUT_100K_TICKS 95 |
212 | #define TARGET_CUM_TIME_OUT_400K_TICKS 95 |
213 | #define TARGET_CUM_TIME_OUT_1000K_TICKS 95 |
214 | |
215 | /* |
216 | * CLOCK_HIGH_TIME_OUT_XK defines Clock High time out period. |
217 | * Clock High time out period = CLOCK_HIGH_TIME_OUT_XK[7:0] x Baud_Clock_Period x 8 |
218 | */ |
219 | #define CLOCK_HIGH_TIME_OUT_100K_TICKS 97 |
220 | #define CLOCK_HIGH_TIME_OUT_400K_TICKS 97 |
221 | #define CLOCK_HIGH_TIME_OUT_1000K_TICKS 97 |
222 | |
223 | #define TO_SCALING_100K \ |
224 | ((BUS_IDLE_MIN_100K_TICKS << 24) | (CTRL_CUM_TIME_OUT_100K_TICKS << 16) | \ |
225 | (TARGET_CUM_TIME_OUT_100K_TICKS << 8) | CLOCK_HIGH_TIME_OUT_100K_TICKS) |
226 | #define TO_SCALING_400K \ |
227 | ((BUS_IDLE_MIN_400K_TICKS << 24) | (CTRL_CUM_TIME_OUT_400K_TICKS << 16) | \ |
228 | (TARGET_CUM_TIME_OUT_400K_TICKS << 8) | CLOCK_HIGH_TIME_OUT_400K_TICKS) |
229 | #define TO_SCALING_1000K \ |
230 | ((BUS_IDLE_MIN_1000K_TICKS << 24) | (CTRL_CUM_TIME_OUT_1000K_TICKS << 16) | \ |
231 | (TARGET_CUM_TIME_OUT_1000K_TICKS << 8) | CLOCK_HIGH_TIME_OUT_1000K_TICKS) |
232 | |
233 | #define I2C_SCL_PAD_CTRL_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x100) |
234 | #define I2C_SDA_PAD_CTRL_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x101) |
235 | |
236 | #define I2C_FOD_EN BIT(4) |
237 | #define I2C_PULL_UP_EN BIT(3) |
238 | #define I2C_PULL_DOWN_EN BIT(2) |
239 | #define I2C_INPUT_EN BIT(1) |
240 | #define I2C_OUTPUT_EN BIT(0) |
241 | |
242 | #define SMBUS_CONTROL_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x200) |
243 | |
244 | #define CTL_RESET_COUNTERS BIT(3) |
245 | #define CTL_TRANSFER_DIR BIT(2) |
246 | #define CTL_HOST_FIFO_ENTRY BIT(1) |
247 | #define CTL_RUN BIT(0) |
248 | |
249 | #define I2C_DIRN_WRITE 0 |
250 | #define I2C_DIRN_READ 1 |
251 | |
252 | #define SMBUS_STATUS_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x204) |
253 | |
254 | #define STA_DMA_TERM BIT(7) |
255 | #define STA_DMA_REQ BIT(6) |
256 | #define STA_THRESHOLD BIT(2) |
257 | #define STA_BUF_FULL BIT(1) |
258 | #define STA_BUF_EMPTY BIT(0) |
259 | |
260 | #define SMBUS_INTR_STAT_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x208) |
261 | |
262 | #define INTR_STAT_DMA_TERM BIT(7) |
263 | #define INTR_STAT_THRESHOLD BIT(2) |
264 | #define INTR_STAT_BUF_FULL BIT(1) |
265 | #define INTR_STAT_BUF_EMPTY BIT(0) |
266 | |
267 | #define SMBUS_INTR_MSK_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x20C) |
268 | |
269 | #define INTR_MSK_DMA_TERM BIT(7) |
270 | #define INTR_MSK_THRESHOLD BIT(2) |
271 | #define INTR_MSK_BUF_FULL BIT(1) |
272 | #define INTR_MSK_BUF_EMPTY BIT(0) |
273 | |
274 | #define ALL_NW_LAYER_INTERRUPTS \ |
275 | (INTR_MSK_DMA_TERM | INTR_MSK_THRESHOLD | INTR_MSK_BUF_FULL | \ |
276 | INTR_MSK_BUF_EMPTY) |
277 | |
278 | #define SMBUS_MCU_COUNTER_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x214) |
279 | |
280 | #define SMBALERT_MST_PAD_CTRL_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x230) |
281 | |
282 | #define SMBALERT_MST_PU BIT(0) |
283 | |
284 | #define SMBUS_GEN_INT_STAT_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x23C) |
285 | |
286 | #define SMBUS_GEN_INT_MASK_REG_OFF (SMBUS_MAST_CORE_ADDR_BASE + 0x240) |
287 | |
288 | #define SMBALERT_INTR_MASK BIT(10) |
289 | #define I2C_BUF_MSTR_INTR_MASK BIT(9) |
290 | #define I2C_INTR_MASK BIT(8) |
291 | #define SMBALERT_WAKE_INTR_MASK BIT(2) |
292 | #define I2C_BUF_MSTR_WAKE_INTR_MASK BIT(1) |
293 | #define I2C_WAKE_INTR_MASK BIT(0) |
294 | |
295 | #define ALL_HIGH_LAYER_INTR \ |
296 | (SMBALERT_INTR_MASK | I2C_BUF_MSTR_INTR_MASK | I2C_INTR_MASK | \ |
297 | SMBALERT_WAKE_INTR_MASK | I2C_BUF_MSTR_WAKE_INTR_MASK | \ |
298 | I2C_WAKE_INTR_MASK) |
299 | |
300 | #define SMBUS_RESET_REG (SMBUS_MAST_CORE_ADDR_BASE + 0x248) |
301 | |
302 | #define PERI_SMBUS_D3_RESET_DIS BIT(16) |
303 | |
304 | #define SMBUS_MST_BUF (SMBUS_MAST_CORE_ADDR_BASE + 0x280) |
305 | |
306 | #define SMBUS_BUF_MAX_SIZE 0x80 |
307 | |
308 | #define I2C_FLAGS_DIRECT_MODE BIT(7) |
309 | #define I2C_FLAGS_POLLING_MODE BIT(6) |
310 | #define I2C_FLAGS_STOP BIT(5) |
311 | #define I2C_FLAGS_SMB_BLK_READ BIT(4) |
312 | |
313 | #define PCI1XXXX_I2C_TIMEOUT_MS 1000 |
314 | |
315 | /* General Purpose Register. */ |
316 | #define SMB_GPR_REG (SMBUS_MAST_CORE_ADDR_BASE + 0x1000 + 0x0c00 + \ |
317 | 0x00) |
318 | |
319 | /* Lock Register. */ |
320 | #define SMB_GPR_LOCK_REG (SMBUS_MAST_CORE_ADDR_BASE + 0x1000 + 0x0000 + \ |
321 | 0x00A0) |
322 | |
323 | #define SMBUS_PERI_LOCK BIT(3) |
324 | |
325 | struct pci1xxxx_i2c { |
326 | struct completion i2c_xfer_done; |
327 | bool i2c_xfer_in_progress; |
328 | struct i2c_adapter adap; |
329 | void __iomem *i2c_base; |
330 | u32 freq; |
331 | u32 flags; |
332 | }; |
333 | |
334 | static int set_sys_lock(struct pci1xxxx_i2c *i2c) |
335 | { |
336 | void __iomem *p = i2c->i2c_base + SMB_GPR_LOCK_REG; |
337 | u8 data; |
338 | |
339 | writel(SMBUS_PERI_LOCK, addr: p); |
340 | data = readl(addr: p); |
341 | if (data != SMBUS_PERI_LOCK) |
342 | return -EPERM; |
343 | |
344 | return 0; |
345 | } |
346 | |
347 | static int release_sys_lock(struct pci1xxxx_i2c *i2c) |
348 | { |
349 | void __iomem *p = i2c->i2c_base + SMB_GPR_LOCK_REG; |
350 | u8 data; |
351 | |
352 | data = readl(addr: p); |
353 | if (data != SMBUS_PERI_LOCK) |
354 | return 0; |
355 | |
356 | writel(val: 0, addr: p); |
357 | data = readl(addr: p); |
358 | if (data & SMBUS_PERI_LOCK) |
359 | return -EPERM; |
360 | |
361 | return 0; |
362 | } |
363 | |
364 | static void pci1xxxx_ack_high_level_intr(struct pci1xxxx_i2c *i2c, u16 intr_msk) |
365 | { |
366 | writew(val: intr_msk, addr: i2c->i2c_base + SMBUS_GEN_INT_STAT_REG_OFF); |
367 | } |
368 | |
369 | static void pci1xxxx_i2c_configure_smbalert_pin(struct pci1xxxx_i2c *i2c, |
370 | bool enable) |
371 | { |
372 | void __iomem *p = i2c->i2c_base + SMBALERT_MST_PAD_CTRL_REG_OFF; |
373 | u8 regval; |
374 | |
375 | regval = readb(addr: p); |
376 | |
377 | if (enable) |
378 | regval |= SMBALERT_MST_PU; |
379 | else |
380 | regval &= ~SMBALERT_MST_PU; |
381 | |
382 | writeb(val: regval, addr: p); |
383 | } |
384 | |
385 | static void pci1xxxx_i2c_send_start_stop(struct pci1xxxx_i2c *i2c, bool start) |
386 | { |
387 | void __iomem *p = i2c->i2c_base + SMB_CORE_CMD_REG_OFF1; |
388 | u8 regval; |
389 | |
390 | regval = readb(addr: p); |
391 | |
392 | if (start) |
393 | regval |= SMB_CORE_CMD_START; |
394 | else |
395 | regval |= SMB_CORE_CMD_STOP; |
396 | |
397 | writeb(val: regval, addr: p); |
398 | } |
399 | |
400 | /* |
401 | * When accessing the core control reg, we should not do a read modified write |
402 | * as they are write '1' to clear bits. Instead we need to write with the |
403 | * specific bits that needs to be set. |
404 | */ |
405 | static void pci1xxxx_i2c_set_clear_FW_ACK(struct pci1xxxx_i2c *i2c, bool set) |
406 | { |
407 | u8 regval; |
408 | |
409 | if (set) |
410 | regval = SMB_CORE_CTRL_FW_ACK | SMB_CORE_CTRL_ESO | SMB_CORE_CTRL_ACK; |
411 | else |
412 | regval = SMB_CORE_CTRL_ESO | SMB_CORE_CTRL_ACK; |
413 | |
414 | writeb(val: regval, addr: i2c->i2c_base + SMB_CORE_CTRL_REG_OFF); |
415 | } |
416 | |
417 | static void pci1xxxx_i2c_buffer_write(struct pci1xxxx_i2c *i2c, u8 slaveaddr, |
418 | u8 transferlen, unsigned char *buf) |
419 | { |
420 | void __iomem *p = i2c->i2c_base + SMBUS_MST_BUF; |
421 | |
422 | if (slaveaddr) |
423 | writeb(val: slaveaddr, addr: p++); |
424 | |
425 | if (buf) |
426 | memcpy_toio(p, buf, transferlen); |
427 | } |
428 | |
429 | /* |
430 | * When accessing the core control reg, we should not do a read modified write |
431 | * as there are write '1' to clear bits. Instead we need to write with the |
432 | * specific bits that needs to be set. |
433 | */ |
434 | static void pci1xxxx_i2c_enable_ESO(struct pci1xxxx_i2c *i2c) |
435 | { |
436 | writeb(SMB_CORE_CTRL_ESO, addr: i2c->i2c_base + SMB_CORE_CTRL_REG_OFF); |
437 | } |
438 | |
439 | static void pci1xxxx_i2c_reset_counters(struct pci1xxxx_i2c *i2c) |
440 | { |
441 | void __iomem *p = i2c->i2c_base + SMBUS_CONTROL_REG_OFF; |
442 | u8 regval; |
443 | |
444 | regval = readb(addr: p); |
445 | regval |= CTL_RESET_COUNTERS; |
446 | writeb(val: regval, addr: p); |
447 | } |
448 | |
449 | static void pci1xxxx_i2c_set_transfer_dir(struct pci1xxxx_i2c *i2c, u8 direction) |
450 | { |
451 | void __iomem *p = i2c->i2c_base + SMBUS_CONTROL_REG_OFF; |
452 | u8 regval; |
453 | |
454 | regval = readb(addr: p); |
455 | if (direction == I2C_DIRN_WRITE) |
456 | regval &= ~CTL_TRANSFER_DIR; |
457 | else |
458 | regval |= CTL_TRANSFER_DIR; |
459 | |
460 | writeb(val: regval, addr: p); |
461 | } |
462 | |
463 | static void pci1xxxx_i2c_set_mcu_count(struct pci1xxxx_i2c *i2c, u8 count) |
464 | { |
465 | writeb(val: count, addr: i2c->i2c_base + SMBUS_MCU_COUNTER_REG_OFF); |
466 | } |
467 | |
468 | static void pci1xxxx_i2c_set_read_count(struct pci1xxxx_i2c *i2c, u8 readcount) |
469 | { |
470 | writeb(val: readcount, addr: i2c->i2c_base + SMB_CORE_CMD_REG_OFF3); |
471 | } |
472 | |
473 | static void pci1xxxx_i2c_set_write_count(struct pci1xxxx_i2c *i2c, u8 writecount) |
474 | { |
475 | writeb(val: writecount, addr: i2c->i2c_base + SMB_CORE_CMD_REG_OFF2); |
476 | } |
477 | |
478 | static void pci1xxxx_i2c_set_DMA_run(struct pci1xxxx_i2c *i2c) |
479 | { |
480 | void __iomem *p = i2c->i2c_base + SMBUS_CONTROL_REG_OFF; |
481 | u8 regval; |
482 | |
483 | regval = readb(addr: p); |
484 | regval |= CTL_RUN; |
485 | writeb(val: regval, addr: p); |
486 | } |
487 | |
488 | static void pci1xxxx_i2c_set_mrun_proceed(struct pci1xxxx_i2c *i2c) |
489 | { |
490 | void __iomem *p = i2c->i2c_base + SMB_CORE_CMD_REG_OFF0; |
491 | u8 regval; |
492 | |
493 | regval = readb(addr: p); |
494 | regval |= SMB_CORE_CMD_M_RUN; |
495 | regval |= SMB_CORE_CMD_M_PROCEED; |
496 | writeb(val: regval, addr: p); |
497 | } |
498 | |
499 | static void pci1xxxx_i2c_start_DMA(struct pci1xxxx_i2c *i2c) |
500 | { |
501 | pci1xxxx_i2c_set_DMA_run(i2c); |
502 | pci1xxxx_i2c_set_mrun_proceed(i2c); |
503 | } |
504 | |
505 | static void pci1xxxx_i2c_config_asr(struct pci1xxxx_i2c *i2c, bool enable) |
506 | { |
507 | void __iomem *p = i2c->i2c_base + SMB_CORE_CONFIG_REG1; |
508 | u8 regval; |
509 | |
510 | regval = readb(addr: p); |
511 | if (enable) |
512 | regval |= SMB_CONFIG1_ASR; |
513 | else |
514 | regval &= ~SMB_CONFIG1_ASR; |
515 | writeb(val: regval, addr: p); |
516 | } |
517 | |
518 | static irqreturn_t pci1xxxx_i2c_isr(int irq, void *dev) |
519 | { |
520 | struct pci1xxxx_i2c *i2c = dev; |
521 | void __iomem *p1 = i2c->i2c_base + SMBUS_GEN_INT_STAT_REG_OFF; |
522 | void __iomem *p2 = i2c->i2c_base + SMBUS_INTR_STAT_REG_OFF; |
523 | irqreturn_t intr_handled = IRQ_NONE; |
524 | u16 reg1; |
525 | u8 reg3; |
526 | |
527 | /* |
528 | * Read the SMBus interrupt status register to see if the |
529 | * DMA_TERM interrupt has caused this callback. |
530 | */ |
531 | reg1 = readw(addr: p1); |
532 | |
533 | if (reg1 & I2C_BUF_MSTR_INTR_MASK) { |
534 | reg3 = readb(addr: p2); |
535 | if (reg3 & INTR_STAT_DMA_TERM) { |
536 | complete(&i2c->i2c_xfer_done); |
537 | intr_handled = IRQ_HANDLED; |
538 | writeb(INTR_STAT_DMA_TERM, addr: p2); |
539 | } |
540 | pci1xxxx_ack_high_level_intr(i2c, I2C_BUF_MSTR_INTR_MASK); |
541 | } |
542 | |
543 | if (reg1 & SMBALERT_INTR_MASK) { |
544 | intr_handled = IRQ_HANDLED; |
545 | pci1xxxx_ack_high_level_intr(i2c, SMBALERT_INTR_MASK); |
546 | } |
547 | |
548 | return intr_handled; |
549 | } |
550 | |
551 | static void pci1xxxx_i2c_set_count(struct pci1xxxx_i2c *i2c, u8 mcucount, |
552 | u8 writecount, u8 readcount) |
553 | { |
554 | pci1xxxx_i2c_set_mcu_count(i2c, count: mcucount); |
555 | pci1xxxx_i2c_set_write_count(i2c, writecount); |
556 | pci1xxxx_i2c_set_read_count(i2c, readcount); |
557 | } |
558 | |
559 | static void pci1xxxx_i2c_set_readm(struct pci1xxxx_i2c *i2c, bool enable) |
560 | { |
561 | void __iomem *p = i2c->i2c_base + SMB_CORE_CMD_REG_OFF1; |
562 | u8 regval; |
563 | |
564 | regval = readb(addr: p); |
565 | if (enable) |
566 | regval |= SMB_CORE_CMD_READM; |
567 | else |
568 | regval &= ~SMB_CORE_CMD_READM; |
569 | |
570 | writeb(val: regval, addr: p); |
571 | } |
572 | |
573 | static void pci1xxxx_ack_nw_layer_intr(struct pci1xxxx_i2c *i2c, u8 ack_intr_msk) |
574 | { |
575 | writeb(val: ack_intr_msk, addr: i2c->i2c_base + SMBUS_INTR_STAT_REG_OFF); |
576 | } |
577 | |
578 | static void pci1xxxx_config_nw_layer_intr(struct pci1xxxx_i2c *i2c, |
579 | u8 intr_msk, bool enable) |
580 | { |
581 | void __iomem *p = i2c->i2c_base + SMBUS_INTR_MSK_REG_OFF; |
582 | u8 regval; |
583 | |
584 | regval = readb(addr: p); |
585 | if (enable) |
586 | regval &= ~intr_msk; |
587 | else |
588 | regval |= intr_msk; |
589 | |
590 | writeb(val: regval, addr: p); |
591 | } |
592 | |
593 | static void pci1xxxx_i2c_config_padctrl(struct pci1xxxx_i2c *i2c, bool enable) |
594 | { |
595 | void __iomem *p1 = i2c->i2c_base + I2C_SCL_PAD_CTRL_REG_OFF; |
596 | void __iomem *p2 = i2c->i2c_base + I2C_SDA_PAD_CTRL_REG_OFF; |
597 | u8 regval; |
598 | |
599 | regval = readb(addr: p1); |
600 | if (enable) |
601 | regval |= I2C_INPUT_EN | I2C_OUTPUT_EN; |
602 | else |
603 | regval &= ~(I2C_INPUT_EN | I2C_OUTPUT_EN); |
604 | |
605 | writeb(val: regval, addr: p1); |
606 | |
607 | regval = readb(addr: p2); |
608 | if (enable) |
609 | regval |= I2C_INPUT_EN | I2C_OUTPUT_EN; |
610 | else |
611 | regval &= ~(I2C_INPUT_EN | I2C_OUTPUT_EN); |
612 | |
613 | writeb(val: regval, addr: p2); |
614 | } |
615 | |
616 | static void pci1xxxx_i2c_set_mode(struct pci1xxxx_i2c *i2c) |
617 | { |
618 | void __iomem *p = i2c->i2c_base + SMBUS_CONTROL_REG_OFF; |
619 | u8 regval; |
620 | |
621 | regval = readb(addr: p); |
622 | if (i2c->flags & I2C_FLAGS_DIRECT_MODE) |
623 | regval &= ~CTL_HOST_FIFO_ENTRY; |
624 | else |
625 | regval |= CTL_HOST_FIFO_ENTRY; |
626 | |
627 | writeb(val: regval, addr: p); |
628 | } |
629 | |
630 | static void pci1xxxx_i2c_config_high_level_intr(struct pci1xxxx_i2c *i2c, |
631 | u16 intr_msk, bool enable) |
632 | { |
633 | void __iomem *p = i2c->i2c_base + SMBUS_GEN_INT_MASK_REG_OFF; |
634 | u16 regval; |
635 | |
636 | regval = readw(addr: p); |
637 | if (enable) |
638 | regval &= ~intr_msk; |
639 | else |
640 | regval |= intr_msk; |
641 | writew(val: regval, addr: p); |
642 | } |
643 | |
644 | static void pci1xxxx_i2c_configure_core_reg(struct pci1xxxx_i2c *i2c, bool enable) |
645 | { |
646 | void __iomem *p1 = i2c->i2c_base + SMB_CORE_CONFIG_REG1; |
647 | void __iomem *p3 = i2c->i2c_base + SMB_CORE_CONFIG_REG3; |
648 | u8 reg1; |
649 | u8 reg3; |
650 | |
651 | reg1 = readb(addr: p1); |
652 | reg3 = readb(addr: p3); |
653 | if (enable) { |
654 | reg1 |= SMB_CONFIG1_ENAB | SMB_CONFIG1_FEN; |
655 | reg3 |= SMB_CONFIG3_ENMI | SMB_CONFIG3_ENIDI; |
656 | } else { |
657 | reg1 &= ~(SMB_CONFIG1_ENAB | SMB_CONFIG1_FEN); |
658 | reg3 &= ~(SMB_CONFIG3_ENMI | SMB_CONFIG3_ENIDI); |
659 | } |
660 | |
661 | writeb(val: reg1, addr: p1); |
662 | writeb(val: reg3, addr: p3); |
663 | } |
664 | |
665 | static void pci1xxxx_i2c_set_freq(struct pci1xxxx_i2c *i2c) |
666 | { |
667 | void __iomem *bp = i2c->i2c_base; |
668 | void __iomem *p_idle_scaling = bp + SMB_CORE_IDLE_SCALING_REG_OFF; |
669 | void __iomem *p_data_timing = bp + SMB_CORE_DATA_TIMING_REG_OFF; |
670 | void __iomem *p_hold_time = bp + SMB_CORE_SR_HOLD_TIME_REG_OFF; |
671 | void __iomem *p_to_scaling = bp + SMB_CORE_TO_SCALING_REG_OFF; |
672 | void __iomem *p_clk_sync = bp + SMB_CORE_CLK_SYNC_REG_OFF; |
673 | void __iomem *p_clk_reg = bp + SMB_CORE_BUS_CLK_REG_OFF; |
674 | |
675 | switch (i2c->freq) { |
676 | case I2C_MAX_STANDARD_MODE_FREQ: |
677 | writeb(SR_HOLD_TIME_100K_TICKS, addr: p_hold_time); |
678 | writel(SMB_IDLE_SCALING_100K, addr: p_idle_scaling); |
679 | writew(BUS_CLK_100K, addr: p_clk_reg); |
680 | writel(CLK_SYNC_100K, addr: p_clk_sync); |
681 | writel(DATA_TIMING_100K, addr: p_data_timing); |
682 | writel(TO_SCALING_100K, addr: p_to_scaling); |
683 | break; |
684 | |
685 | case I2C_MAX_FAST_MODE_PLUS_FREQ: |
686 | writeb(SR_HOLD_TIME_1000K_TICKS, addr: p_hold_time); |
687 | writel(SMB_IDLE_SCALING_1000K, addr: p_idle_scaling); |
688 | writew(BUS_CLK_1000K, addr: p_clk_reg); |
689 | writel(CLK_SYNC_1000K, addr: p_clk_sync); |
690 | writel(DATA_TIMING_1000K, addr: p_data_timing); |
691 | writel(TO_SCALING_1000K, addr: p_to_scaling); |
692 | break; |
693 | |
694 | case I2C_MAX_FAST_MODE_FREQ: |
695 | default: |
696 | writeb(SR_HOLD_TIME_400K_TICKS, addr: p_hold_time); |
697 | writel(SMB_IDLE_SCALING_400K, addr: p_idle_scaling); |
698 | writew(BUS_CLK_400K, addr: p_clk_reg); |
699 | writel(CLK_SYNC_400K, addr: p_clk_sync); |
700 | writel(DATA_TIMING_400K, addr: p_data_timing); |
701 | writel(TO_SCALING_400K, addr: p_to_scaling); |
702 | break; |
703 | } |
704 | } |
705 | |
706 | static void pci1xxxx_i2c_init(struct pci1xxxx_i2c *i2c) |
707 | { |
708 | void __iomem *p2 = i2c->i2c_base + SMBUS_STATUS_REG_OFF; |
709 | void __iomem *p1 = i2c->i2c_base + SMB_GPR_REG; |
710 | u8 regval; |
711 | int ret; |
712 | |
713 | ret = set_sys_lock(i2c); |
714 | if (ret == -EPERM) { |
715 | /* |
716 | * Configure I2C Fast Mode as default frequency if unable |
717 | * to acquire sys lock. |
718 | */ |
719 | regval = 0; |
720 | } else { |
721 | regval = readl(addr: p1); |
722 | release_sys_lock(i2c); |
723 | } |
724 | |
725 | switch (regval) { |
726 | case 0: |
727 | i2c->freq = I2C_MAX_FAST_MODE_FREQ; |
728 | pci1xxxx_i2c_set_freq(i2c); |
729 | break; |
730 | case 1: |
731 | i2c->freq = I2C_MAX_STANDARD_MODE_FREQ; |
732 | pci1xxxx_i2c_set_freq(i2c); |
733 | break; |
734 | case 2: |
735 | i2c->freq = I2C_MAX_FAST_MODE_PLUS_FREQ; |
736 | pci1xxxx_i2c_set_freq(i2c); |
737 | break; |
738 | case 3: |
739 | default: |
740 | break; |
741 | } |
742 | |
743 | pci1xxxx_i2c_config_padctrl(i2c, enable: true); |
744 | i2c->flags |= I2C_FLAGS_DIRECT_MODE; |
745 | pci1xxxx_i2c_set_mode(i2c); |
746 | |
747 | /* |
748 | * Added as a precaution since BUF_EMPTY in status register |
749 | * also trigered an Interrupt. |
750 | */ |
751 | writeb(STA_BUF_EMPTY, addr: p2); |
752 | |
753 | /* Configure core I2c control registers. */ |
754 | pci1xxxx_i2c_configure_core_reg(i2c, enable: true); |
755 | |
756 | /* |
757 | * Enable pull-up for the SMB alert pin which is just used for |
758 | * wakeup right now. |
759 | */ |
760 | pci1xxxx_i2c_configure_smbalert_pin(i2c, enable: true); |
761 | } |
762 | |
763 | static void pci1xxxx_i2c_clear_flags(struct pci1xxxx_i2c *i2c) |
764 | { |
765 | u8 regval; |
766 | |
767 | /* Reset the internal buffer counters. */ |
768 | pci1xxxx_i2c_reset_counters(i2c); |
769 | |
770 | /* Clear low level interrupts. */ |
771 | regval = COMPLETION_MNAKX | COMPLETION_IDLE | COMPLETION_MDONE; |
772 | writeb(val: regval, addr: i2c->i2c_base + SMB_CORE_COMPLETION_REG_OFF3); |
773 | reinit_completion(x: &i2c->i2c_xfer_done); |
774 | pci1xxxx_ack_nw_layer_intr(i2c, ALL_NW_LAYER_INTERRUPTS); |
775 | pci1xxxx_ack_high_level_intr(i2c, ALL_HIGH_LAYER_INTR); |
776 | } |
777 | |
778 | static int pci1xxxx_i2c_read(struct pci1xxxx_i2c *i2c, u8 slaveaddr, |
779 | unsigned char *buf, u16 total_len) |
780 | { |
781 | void __iomem *p2 = i2c->i2c_base + SMB_CORE_COMPLETION_REG_OFF3; |
782 | void __iomem *p1 = i2c->i2c_base + SMB_CORE_CMD_REG_OFF1; |
783 | void __iomem *p3 = i2c->i2c_base + SMBUS_MST_BUF; |
784 | unsigned long time_left; |
785 | u16 remainingbytes; |
786 | u8 transferlen; |
787 | int retval = 0; |
788 | u8 read_count; |
789 | u32 regval; |
790 | u16 count; |
791 | |
792 | /* Enable I2C host controller by setting the ESO bit in the CONTROL REG. */ |
793 | pci1xxxx_i2c_enable_ESO(i2c); |
794 | pci1xxxx_i2c_clear_flags(i2c); |
795 | pci1xxxx_config_nw_layer_intr(i2c, INTR_MSK_DMA_TERM, enable: true); |
796 | pci1xxxx_i2c_config_high_level_intr(i2c, I2C_BUF_MSTR_INTR_MASK, enable: true); |
797 | |
798 | /* |
799 | * The I2C transfer could be more than 128 bytes. Our Core is |
800 | * capable of only sending 128 at a time. |
801 | * As far as the I2C read is concerned, initailly send the |
802 | * read slave address along with the number of bytes to read in |
803 | * ReadCount. After sending the slave address the interrupt |
804 | * is generated. On seeing the ACK for the slave address, reverse the |
805 | * buffer direction and run the DMA to initiate Read from slave. |
806 | */ |
807 | for (count = 0; count < total_len; count += transferlen) { |
808 | |
809 | /* |
810 | * Before start of any transaction clear the existing |
811 | * START/STOP conditions. |
812 | */ |
813 | writeb(val: 0, addr: p1); |
814 | remainingbytes = total_len - count; |
815 | transferlen = min_t(u16, remainingbytes, SMBUS_BUF_MAX_SIZE); |
816 | |
817 | /* |
818 | * Send STOP bit for the last chunk in the transaction. |
819 | * For I2C read transaction of more than BUF_SIZE, NACK should |
820 | * only be sent for the last read. |
821 | * Hence a bit FW_ACK is set for all the read chunks except for |
822 | * the last chunk. For the last chunk NACK should be sent and |
823 | * FW_ACK is cleared Send STOP only when I2C_FLAGS_STOP bit is |
824 | * set in the flags and only for the last transaction. |
825 | */ |
826 | if ((count + transferlen >= total_len) && |
827 | (i2c->flags & I2C_FLAGS_STOP)) { |
828 | pci1xxxx_i2c_set_clear_FW_ACK(i2c, set: false); |
829 | pci1xxxx_i2c_send_start_stop(i2c, start: 0); |
830 | } else { |
831 | pci1xxxx_i2c_set_clear_FW_ACK(i2c, set: true); |
832 | } |
833 | |
834 | /* Send START bit for the first transaction. */ |
835 | if (count == 0) { |
836 | pci1xxxx_i2c_set_transfer_dir(i2c, I2C_DIRN_WRITE); |
837 | pci1xxxx_i2c_send_start_stop(i2c, start: 1); |
838 | |
839 | /* Write I2c buffer with just the slave addr. */ |
840 | pci1xxxx_i2c_buffer_write(i2c, slaveaddr, transferlen: 0, NULL); |
841 | |
842 | /* Set the count. Readcount is the transfer bytes. */ |
843 | pci1xxxx_i2c_set_count(i2c, mcucount: 1, writecount: 1, readcount: transferlen); |
844 | |
845 | /* |
846 | * Set the Auto_start_read bit so that the HW itself |
847 | * will take care of the read phase. |
848 | */ |
849 | pci1xxxx_i2c_config_asr(i2c, enable: true); |
850 | if (i2c->flags & I2C_FLAGS_SMB_BLK_READ) |
851 | pci1xxxx_i2c_set_readm(i2c, enable: true); |
852 | } else { |
853 | pci1xxxx_i2c_set_count(i2c, mcucount: 0, writecount: 0, readcount: transferlen); |
854 | pci1xxxx_i2c_config_asr(i2c, enable: false); |
855 | pci1xxxx_i2c_clear_flags(i2c); |
856 | pci1xxxx_i2c_set_transfer_dir(i2c, I2C_DIRN_READ); |
857 | } |
858 | |
859 | /* Start the DMA. */ |
860 | pci1xxxx_i2c_start_DMA(i2c); |
861 | |
862 | /* Wait for the DMA_TERM interrupt. */ |
863 | time_left = wait_for_completion_timeout(x: &i2c->i2c_xfer_done, |
864 | timeout: msecs_to_jiffies(PCI1XXXX_I2C_TIMEOUT_MS)); |
865 | if (time_left == 0) { |
866 | /* Reset the I2C core to release the bus lock. */ |
867 | pci1xxxx_i2c_init(i2c); |
868 | retval = -ETIMEDOUT; |
869 | goto cleanup; |
870 | } |
871 | |
872 | /* Read the completion reg to know the reason for DMA_TERM. */ |
873 | regval = readb(addr: p2); |
874 | |
875 | /* Slave did not respond. */ |
876 | if (regval & COMPLETION_MNAKX) { |
877 | writeb(COMPLETION_MNAKX, addr: p2); |
878 | retval = -ETIMEDOUT; |
879 | goto cleanup; |
880 | } |
881 | |
882 | if (i2c->flags & I2C_FLAGS_SMB_BLK_READ) { |
883 | buf[0] = readb(addr: p3); |
884 | read_count = buf[0]; |
885 | memcpy_fromio(&buf[1], p3 + 1, read_count); |
886 | } else { |
887 | memcpy_fromio(&buf[count], p3, transferlen); |
888 | } |
889 | } |
890 | |
891 | cleanup: |
892 | /* Disable all the interrupts. */ |
893 | pci1xxxx_config_nw_layer_intr(i2c, INTR_MSK_DMA_TERM, enable: false); |
894 | pci1xxxx_i2c_config_high_level_intr(i2c, I2C_BUF_MSTR_INTR_MASK, enable: false); |
895 | pci1xxxx_i2c_config_asr(i2c, enable: false); |
896 | return retval; |
897 | } |
898 | |
899 | static int pci1xxxx_i2c_write(struct pci1xxxx_i2c *i2c, u8 slaveaddr, |
900 | unsigned char *buf, u16 total_len) |
901 | { |
902 | void __iomem *p2 = i2c->i2c_base + SMB_CORE_COMPLETION_REG_OFF3; |
903 | void __iomem *p1 = i2c->i2c_base + SMB_CORE_CMD_REG_OFF1; |
904 | unsigned long time_left; |
905 | u16 remainingbytes; |
906 | u8 actualwritelen; |
907 | u8 transferlen; |
908 | int retval = 0; |
909 | u32 regval; |
910 | u16 count; |
911 | |
912 | /* Enable I2C host controller by setting the ESO bit in the CONTROL REG. */ |
913 | pci1xxxx_i2c_enable_ESO(i2c); |
914 | |
915 | /* Set the Buffer direction. */ |
916 | pci1xxxx_i2c_set_transfer_dir(i2c, I2C_DIRN_WRITE); |
917 | pci1xxxx_config_nw_layer_intr(i2c, INTR_MSK_DMA_TERM, enable: true); |
918 | pci1xxxx_i2c_config_high_level_intr(i2c, I2C_BUF_MSTR_INTR_MASK, enable: true); |
919 | |
920 | /* |
921 | * The i2c transfer could be more than 128 bytes. Our Core is |
922 | * capable of only sending 128 at a time. |
923 | */ |
924 | for (count = 0; count < total_len; count += transferlen) { |
925 | /* |
926 | * Before start of any transaction clear the existing |
927 | * START/STOP conditions. |
928 | */ |
929 | writeb(val: 0, addr: p1); |
930 | pci1xxxx_i2c_clear_flags(i2c); |
931 | remainingbytes = total_len - count; |
932 | |
933 | /* If it is the starting of the transaction send START. */ |
934 | if (count == 0) { |
935 | pci1xxxx_i2c_send_start_stop(i2c, start: 1); |
936 | |
937 | /* -1 for the slave address. */ |
938 | transferlen = min_t(u16, SMBUS_BUF_MAX_SIZE - 1, |
939 | remainingbytes); |
940 | pci1xxxx_i2c_buffer_write(i2c, slaveaddr, |
941 | transferlen, buf: &buf[count]); |
942 | /* |
943 | * The actual number of bytes written on the I2C bus |
944 | * is including the slave address. |
945 | */ |
946 | actualwritelen = transferlen + 1; |
947 | } else { |
948 | transferlen = min_t(u16, SMBUS_BUF_MAX_SIZE, remainingbytes); |
949 | pci1xxxx_i2c_buffer_write(i2c, slaveaddr: 0, transferlen, buf: &buf[count]); |
950 | actualwritelen = transferlen; |
951 | } |
952 | |
953 | pci1xxxx_i2c_set_count(i2c, mcucount: actualwritelen, writecount: actualwritelen, readcount: 0); |
954 | |
955 | /* |
956 | * Send STOP only when I2C_FLAGS_STOP bit is set in the flags and |
957 | * only for the last transaction. |
958 | */ |
959 | if (remainingbytes <= transferlen && |
960 | (i2c->flags & I2C_FLAGS_STOP)) |
961 | pci1xxxx_i2c_send_start_stop(i2c, start: 0); |
962 | |
963 | pci1xxxx_i2c_start_DMA(i2c); |
964 | |
965 | /* |
966 | * Wait for the DMA_TERM interrupt. |
967 | */ |
968 | time_left = wait_for_completion_timeout(x: &i2c->i2c_xfer_done, |
969 | timeout: msecs_to_jiffies(PCI1XXXX_I2C_TIMEOUT_MS)); |
970 | if (time_left == 0) { |
971 | /* Reset the I2C core to release the bus lock. */ |
972 | pci1xxxx_i2c_init(i2c); |
973 | retval = -ETIMEDOUT; |
974 | goto cleanup; |
975 | } |
976 | |
977 | regval = readb(addr: p2); |
978 | if (regval & COMPLETION_MNAKX) { |
979 | writeb(COMPLETION_MNAKX, addr: p2); |
980 | retval = -ETIMEDOUT; |
981 | goto cleanup; |
982 | } |
983 | } |
984 | cleanup: |
985 | /* Disable all the interrupts. */ |
986 | pci1xxxx_config_nw_layer_intr(i2c, INTR_MSK_DMA_TERM, enable: false); |
987 | pci1xxxx_i2c_config_high_level_intr(i2c, I2C_BUF_MSTR_INTR_MASK, enable: false); |
988 | |
989 | return retval; |
990 | } |
991 | |
992 | static int pci1xxxx_i2c_xfer(struct i2c_adapter *adap, |
993 | struct i2c_msg *msgs, int num) |
994 | { |
995 | struct pci1xxxx_i2c *i2c = i2c_get_adapdata(adap); |
996 | u8 slaveaddr; |
997 | int retval; |
998 | u32 i; |
999 | |
1000 | i2c->i2c_xfer_in_progress = true; |
1001 | for (i = 0; i < num; i++) { |
1002 | slaveaddr = i2c_8bit_addr_from_msg(msg: &msgs[i]); |
1003 | |
1004 | /* |
1005 | * Send the STOP bit if the transfer is the final one or |
1006 | * if the I2C_M_STOP flag is set. |
1007 | */ |
1008 | if ((i == num - 1) || (msgs[i].flags & I2C_M_STOP)) |
1009 | i2c->flags |= I2C_FLAGS_STOP; |
1010 | else |
1011 | i2c->flags &= ~I2C_FLAGS_STOP; |
1012 | |
1013 | if (msgs[i].flags & I2C_M_RECV_LEN) |
1014 | i2c->flags |= I2C_FLAGS_SMB_BLK_READ; |
1015 | else |
1016 | i2c->flags &= ~I2C_FLAGS_SMB_BLK_READ; |
1017 | |
1018 | if (msgs[i].flags & I2C_M_RD) |
1019 | retval = pci1xxxx_i2c_read(i2c, slaveaddr, |
1020 | buf: msgs[i].buf, total_len: msgs[i].len); |
1021 | else |
1022 | retval = pci1xxxx_i2c_write(i2c, slaveaddr, |
1023 | buf: msgs[i].buf, total_len: msgs[i].len); |
1024 | |
1025 | if (retval < 0) |
1026 | break; |
1027 | } |
1028 | i2c->i2c_xfer_in_progress = false; |
1029 | |
1030 | if (retval < 0) |
1031 | return retval; |
1032 | |
1033 | return num; |
1034 | } |
1035 | |
1036 | /* |
1037 | * List of supported functions by the driver. |
1038 | */ |
1039 | static u32 pci1xxxx_i2c_get_funcs(struct i2c_adapter *adap) |
1040 | { |
1041 | return I2C_FUNC_I2C | I2C_FUNC_PROTOCOL_MANGLING | |
1042 | I2C_FUNC_SMBUS_BLOCK_PROC_CALL | |
1043 | I2C_FUNC_SMBUS_BYTE | |
1044 | I2C_FUNC_SMBUS_BYTE_DATA | |
1045 | I2C_FUNC_SMBUS_WORD_DATA | |
1046 | I2C_FUNC_SMBUS_PROC_CALL | |
1047 | I2C_FUNC_SMBUS_BLOCK_DATA; |
1048 | } |
1049 | |
1050 | static const struct i2c_algorithm pci1xxxx_i2c_algo = { |
1051 | .master_xfer = pci1xxxx_i2c_xfer, |
1052 | .functionality = pci1xxxx_i2c_get_funcs, |
1053 | }; |
1054 | |
1055 | static const struct i2c_adapter_quirks pci1xxxx_i2c_quirks = { |
1056 | .flags = I2C_AQ_NO_ZERO_LEN, |
1057 | }; |
1058 | |
1059 | static const struct i2c_adapter pci1xxxx_i2c_ops = { |
1060 | .owner = THIS_MODULE, |
1061 | .name = "PCI1xxxx I2C Adapter" , |
1062 | .algo = &pci1xxxx_i2c_algo, |
1063 | .quirks = &pci1xxxx_i2c_quirks, |
1064 | }; |
1065 | |
1066 | static int pci1xxxx_i2c_suspend(struct device *dev) |
1067 | { |
1068 | struct pci1xxxx_i2c *i2c = dev_get_drvdata(dev); |
1069 | void __iomem *p = i2c->i2c_base + SMBUS_RESET_REG; |
1070 | struct pci_dev *pdev = to_pci_dev(dev); |
1071 | u32 regval; |
1072 | |
1073 | i2c_mark_adapter_suspended(adap: &i2c->adap); |
1074 | |
1075 | /* |
1076 | * If the system is put into 'suspend' state when the I2C transfer is in |
1077 | * progress, wait until the transfer completes. |
1078 | */ |
1079 | while (i2c->i2c_xfer_in_progress) |
1080 | msleep(msecs: 20); |
1081 | |
1082 | pci1xxxx_i2c_config_high_level_intr(i2c, SMBALERT_WAKE_INTR_MASK, enable: true); |
1083 | |
1084 | /* |
1085 | * Enable the PERST_DIS bit to mask the PERST from resetting the core |
1086 | * registers. |
1087 | */ |
1088 | regval = readl(addr: p); |
1089 | regval |= PERI_SMBUS_D3_RESET_DIS; |
1090 | writel(val: regval, addr: p); |
1091 | |
1092 | /* Enable PCI wake in the PMCSR register. */ |
1093 | device_set_wakeup_enable(dev, enable: true); |
1094 | pci_wake_from_d3(dev: pdev, enable: true); |
1095 | |
1096 | return 0; |
1097 | } |
1098 | |
1099 | static int pci1xxxx_i2c_resume(struct device *dev) |
1100 | { |
1101 | struct pci1xxxx_i2c *i2c = dev_get_drvdata(dev); |
1102 | void __iomem *p1 = i2c->i2c_base + SMBUS_GEN_INT_STAT_REG_OFF; |
1103 | void __iomem *p2 = i2c->i2c_base + SMBUS_RESET_REG; |
1104 | struct pci_dev *pdev = to_pci_dev(dev); |
1105 | u32 regval; |
1106 | |
1107 | regval = readw(addr: p1); |
1108 | writew(val: regval, addr: p1); |
1109 | pci1xxxx_i2c_config_high_level_intr(i2c, SMBALERT_WAKE_INTR_MASK, enable: false); |
1110 | regval = readl(addr: p2); |
1111 | regval &= ~PERI_SMBUS_D3_RESET_DIS; |
1112 | writel(val: regval, addr: p2); |
1113 | i2c_mark_adapter_resumed(adap: &i2c->adap); |
1114 | pci_wake_from_d3(dev: pdev, enable: false); |
1115 | return 0; |
1116 | } |
1117 | |
1118 | static DEFINE_SIMPLE_DEV_PM_OPS(pci1xxxx_i2c_pm_ops, pci1xxxx_i2c_suspend, |
1119 | pci1xxxx_i2c_resume); |
1120 | |
1121 | static void pci1xxxx_i2c_shutdown(void *data) |
1122 | { |
1123 | struct pci1xxxx_i2c *i2c = data; |
1124 | |
1125 | pci1xxxx_i2c_config_padctrl(i2c, enable: false); |
1126 | pci1xxxx_i2c_configure_core_reg(i2c, enable: false); |
1127 | } |
1128 | |
1129 | static int pci1xxxx_i2c_probe_pci(struct pci_dev *pdev, |
1130 | const struct pci_device_id *ent) |
1131 | { |
1132 | struct device *dev = &pdev->dev; |
1133 | struct pci1xxxx_i2c *i2c; |
1134 | int ret; |
1135 | |
1136 | i2c = devm_kzalloc(dev, size: sizeof(*i2c), GFP_KERNEL); |
1137 | if (!i2c) |
1138 | return -ENOMEM; |
1139 | |
1140 | pci_set_drvdata(pdev, data: i2c); |
1141 | i2c->i2c_xfer_in_progress = false; |
1142 | |
1143 | ret = pcim_enable_device(pdev); |
1144 | if (ret) |
1145 | return ret; |
1146 | |
1147 | pci_set_master(dev: pdev); |
1148 | |
1149 | /* |
1150 | * We are getting the base address of the SMB core. SMB core uses |
1151 | * BAR0 and size is 32K. |
1152 | */ |
1153 | ret = pcim_iomap_regions(pdev, BIT(0), name: pci_name(pdev)); |
1154 | if (ret < 0) |
1155 | return ret; |
1156 | |
1157 | i2c->i2c_base = pcim_iomap_table(pdev)[0]; |
1158 | init_completion(x: &i2c->i2c_xfer_done); |
1159 | pci1xxxx_i2c_init(i2c); |
1160 | |
1161 | ret = devm_add_action(dev, pci1xxxx_i2c_shutdown, i2c); |
1162 | if (ret) |
1163 | return ret; |
1164 | |
1165 | ret = pci_alloc_irq_vectors(dev: pdev, min_vecs: 1, max_vecs: 1, PCI_IRQ_ALL_TYPES); |
1166 | if (ret < 0) |
1167 | return ret; |
1168 | |
1169 | ret = devm_request_irq(dev, irq: pci_irq_vector(dev: pdev, nr: 0), handler: pci1xxxx_i2c_isr, |
1170 | irqflags: 0, devname: pci_name(pdev), dev_id: i2c); |
1171 | if (ret) |
1172 | return ret; |
1173 | |
1174 | i2c->adap = pci1xxxx_i2c_ops; |
1175 | i2c->adap.dev.parent = dev; |
1176 | |
1177 | snprintf(buf: i2c->adap.name, size: sizeof(i2c->adap.name), |
1178 | fmt: "MCHP PCI1xxxx i2c adapter at %s" , pci_name(pdev)); |
1179 | |
1180 | i2c_set_adapdata(adap: &i2c->adap, data: i2c); |
1181 | |
1182 | ret = devm_i2c_add_adapter(dev, adapter: &i2c->adap); |
1183 | if (ret) |
1184 | return dev_err_probe(dev, err: ret, fmt: "i2c add adapter failed\n" ); |
1185 | |
1186 | return 0; |
1187 | } |
1188 | |
1189 | static const struct pci_device_id pci1xxxx_i2c_pci_id_table[] = { |
1190 | { PCI_VDEVICE(EFAR, 0xA003) }, |
1191 | { PCI_VDEVICE(EFAR, 0xA013) }, |
1192 | { PCI_VDEVICE(EFAR, 0xA023) }, |
1193 | { PCI_VDEVICE(EFAR, 0xA033) }, |
1194 | { PCI_VDEVICE(EFAR, 0xA043) }, |
1195 | { } |
1196 | }; |
1197 | MODULE_DEVICE_TABLE(pci, pci1xxxx_i2c_pci_id_table); |
1198 | |
1199 | static struct pci_driver pci1xxxx_i2c_pci_driver = { |
1200 | .name = "i2c-mchp-pci1xxxx" , |
1201 | .id_table = pci1xxxx_i2c_pci_id_table, |
1202 | .probe = pci1xxxx_i2c_probe_pci, |
1203 | .driver = { |
1204 | .pm = pm_sleep_ptr(&pci1xxxx_i2c_pm_ops), |
1205 | }, |
1206 | }; |
1207 | module_pci_driver(pci1xxxx_i2c_pci_driver); |
1208 | |
1209 | MODULE_LICENSE("GPL" ); |
1210 | MODULE_AUTHOR("Tharun Kumar P<tharunkumar.pasumarthi@microchip.com>" ); |
1211 | MODULE_AUTHOR("Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com>" ); |
1212 | MODULE_DESCRIPTION("Microchip Technology Inc. pci1xxxx I2C bus driver" ); |
1213 | |