1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Analog Devices AD7944/85/86 PulSAR ADC family driver.
4 *
5 * Copyright 2024 Analog Devices, Inc.
6 * Copyright 2024 BayLibre, SAS
7 */
8
9#include <linux/align.h>
10#include <linux/bitfield.h>
11#include <linux/bitops.h>
12#include <linux/delay.h>
13#include <linux/device.h>
14#include <linux/err.h>
15#include <linux/gpio/consumer.h>
16#include <linux/module.h>
17#include <linux/property.h>
18#include <linux/regulator/consumer.h>
19#include <linux/spi/offload/consumer.h>
20#include <linux/spi/spi.h>
21#include <linux/string_helpers.h>
22#include <linux/units.h>
23
24#include <linux/iio/iio.h>
25#include <linux/iio/sysfs.h>
26#include <linux/iio/buffer-dmaengine.h>
27#include <linux/iio/trigger_consumer.h>
28#include <linux/iio/triggered_buffer.h>
29
30#define AD7944_INTERNAL_REF_MV 4096
31
32struct ad7944_timing_spec {
33 /* Normal mode max conversion time (t_{CONV}). */
34 unsigned int conv_ns;
35 /* TURBO mode max conversion time (t_{CONV}). */
36 unsigned int turbo_conv_ns;
37};
38
39enum ad7944_spi_mode {
40 /* datasheet calls this "4-wire mode" */
41 AD7944_SPI_MODE_DEFAULT,
42 /* datasheet calls this "3-wire mode" (not related to SPI_3WIRE!) */
43 AD7944_SPI_MODE_SINGLE,
44 /* datasheet calls this "chain mode" */
45 AD7944_SPI_MODE_CHAIN,
46};
47
48/* maps adi,spi-mode property value to enum */
49static const char * const ad7944_spi_modes[] = {
50 [AD7944_SPI_MODE_DEFAULT] = "",
51 [AD7944_SPI_MODE_SINGLE] = "single",
52 [AD7944_SPI_MODE_CHAIN] = "chain",
53};
54
55struct ad7944_adc {
56 struct spi_device *spi;
57 enum ad7944_spi_mode spi_mode;
58 struct spi_transfer xfers[3];
59 struct spi_message msg;
60 struct spi_transfer offload_xfers[2];
61 struct spi_message offload_msg;
62 struct spi_offload *offload;
63 struct spi_offload_trigger *offload_trigger;
64 unsigned long offload_trigger_hz;
65 int sample_freq_range[3];
66 void *chain_mode_buf;
67 /* Chip-specific timing specifications. */
68 const struct ad7944_timing_spec *timing_spec;
69 /* GPIO connected to CNV pin. */
70 struct gpio_desc *cnv;
71 /* Optional GPIO to enable turbo mode. */
72 struct gpio_desc *turbo;
73 /* Indicates TURBO is hard-wired to be always enabled. */
74 bool always_turbo;
75 /* Reference voltage (millivolts). */
76 unsigned int ref_mv;
77
78 /*
79 * DMA (thus cache coherency maintenance) requires the
80 * transfer buffers to live in their own cache lines.
81 */
82 struct {
83 union {
84 u16 u16;
85 u32 u32;
86 } raw;
87 aligned_s64 timestamp;
88 } sample __aligned(IIO_DMA_MINALIGN);
89};
90
91/* quite time before CNV rising edge */
92#define AD7944_T_QUIET_NS 20
93/* minimum CNV high time to trigger conversion */
94#define AD7944_T_CNVH_NS 10
95
96static const struct ad7944_timing_spec ad7944_timing_spec = {
97 .conv_ns = 420,
98 .turbo_conv_ns = 320,
99};
100
101static const struct ad7944_timing_spec ad7986_timing_spec = {
102 .conv_ns = 500,
103 .turbo_conv_ns = 400,
104};
105
106struct ad7944_chip_info {
107 const char *name;
108 const struct ad7944_timing_spec *timing_spec;
109 u32 max_sample_rate_hz;
110 const struct iio_chan_spec channels[2];
111 const struct iio_chan_spec offload_channels[1];
112};
113
114/* get number of bytes for SPI xfer */
115#define AD7944_SPI_BYTES(scan_type) ((scan_type).realbits > 16 ? 4 : 2)
116
117/*
118 * AD7944_DEFINE_CHIP_INFO - Define a chip info structure for a specific chip
119 * @_name: The name of the chip
120 * @_ts: The timing specification for the chip
121 * @_max: The maximum sample rate in Hz
122 * @_bits: The number of bits in the conversion result
123 * @_diff: Whether the chip is true differential or not
124 */
125#define AD7944_DEFINE_CHIP_INFO(_name, _ts, _max, _bits, _diff) \
126static const struct ad7944_chip_info _name##_chip_info = { \
127 .name = #_name, \
128 .timing_spec = &_ts##_timing_spec, \
129 .max_sample_rate_hz = _max, \
130 .channels = { \
131 { \
132 .type = IIO_VOLTAGE, \
133 .indexed = 1, \
134 .differential = _diff, \
135 .channel = 0, \
136 .channel2 = _diff ? 1 : 0, \
137 .scan_index = 0, \
138 .scan_type.sign = _diff ? 's' : 'u', \
139 .scan_type.realbits = _bits, \
140 .scan_type.storagebits = _bits > 16 ? 32 : 16, \
141 .scan_type.endianness = IIO_CPU, \
142 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \
143 | BIT(IIO_CHAN_INFO_SCALE), \
144 }, \
145 IIO_CHAN_SOFT_TIMESTAMP(1), \
146 }, \
147 .offload_channels = { \
148 { \
149 .type = IIO_VOLTAGE, \
150 .indexed = 1, \
151 .differential = _diff, \
152 .channel = 0, \
153 .channel2 = _diff ? 1 : 0, \
154 .scan_index = 0, \
155 .scan_type.sign = _diff ? 's' : 'u', \
156 .scan_type.realbits = _bits, \
157 .scan_type.storagebits = 32, \
158 .scan_type.endianness = IIO_CPU, \
159 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \
160 | BIT(IIO_CHAN_INFO_SCALE) \
161 | BIT(IIO_CHAN_INFO_SAMP_FREQ), \
162 .info_mask_separate_available = \
163 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
164 }, \
165 }, \
166}
167
168/*
169 * Notes on the offload channels:
170 * - There is no soft timestamp since everything is done in hardware.
171 * - There is a sampling frequency attribute added. This controls the SPI
172 * offload trigger.
173 * - The storagebits value depends on the SPI offload provider. Currently there
174 * is only one supported provider, namely the ADI PULSAR ADC HDL project,
175 * which always uses 32-bit words for data values, even for <= 16-bit ADCs.
176 * So the value is just hardcoded to 32 for now.
177 */
178
179/* pseudo-differential with ground sense */
180AD7944_DEFINE_CHIP_INFO(ad7944, ad7944, 2.5 * MEGA, 14, 0);
181AD7944_DEFINE_CHIP_INFO(ad7985, ad7944, 2.5 * MEGA, 16, 0);
182/* fully differential */
183AD7944_DEFINE_CHIP_INFO(ad7986, ad7986, 2 * MEGA, 18, 1);
184
185static int ad7944_3wire_cs_mode_init_msg(struct device *dev, struct ad7944_adc *adc,
186 const struct iio_chan_spec *chan)
187{
188 unsigned int t_conv_ns = adc->always_turbo ? adc->timing_spec->turbo_conv_ns
189 : adc->timing_spec->conv_ns;
190 struct spi_transfer *xfers = adc->xfers;
191
192 /*
193 * CS is tied to CNV and we need a low to high transition to start the
194 * conversion, so place CNV low for t_QUIET to prepare for this.
195 */
196 xfers[0].delay.value = AD7944_T_QUIET_NS;
197 xfers[0].delay.unit = SPI_DELAY_UNIT_NSECS;
198
199 /*
200 * CS has to be high for full conversion time to avoid triggering the
201 * busy indication.
202 */
203 xfers[1].cs_off = 1;
204 xfers[1].delay.value = t_conv_ns;
205 xfers[1].delay.unit = SPI_DELAY_UNIT_NSECS;
206
207 /* Then we can read the data during the acquisition phase */
208 xfers[2].rx_buf = &adc->sample.raw;
209 xfers[2].len = AD7944_SPI_BYTES(chan->scan_type);
210 xfers[2].bits_per_word = chan->scan_type.realbits;
211
212 spi_message_init_with_transfers(m: &adc->msg, xfers, num_xfers: 3);
213
214 return devm_spi_optimize_message(dev, spi: adc->spi, msg: &adc->msg);
215}
216
217static int ad7944_4wire_mode_init_msg(struct device *dev, struct ad7944_adc *adc,
218 const struct iio_chan_spec *chan)
219{
220 unsigned int t_conv_ns = adc->always_turbo ? adc->timing_spec->turbo_conv_ns
221 : adc->timing_spec->conv_ns;
222 struct spi_transfer *xfers = adc->xfers;
223
224 /*
225 * CS has to be high for full conversion time to avoid triggering the
226 * busy indication.
227 */
228 xfers[0].cs_off = 1;
229 xfers[0].delay.value = t_conv_ns;
230 xfers[0].delay.unit = SPI_DELAY_UNIT_NSECS;
231
232 xfers[1].rx_buf = &adc->sample.raw;
233 xfers[1].len = AD7944_SPI_BYTES(chan->scan_type);
234 xfers[1].bits_per_word = chan->scan_type.realbits;
235
236 spi_message_init_with_transfers(m: &adc->msg, xfers, num_xfers: 2);
237
238 return devm_spi_optimize_message(dev, spi: adc->spi, msg: &adc->msg);
239}
240
241static int ad7944_chain_mode_init_msg(struct device *dev, struct ad7944_adc *adc,
242 const struct iio_chan_spec *chan,
243 u32 n_chain_dev)
244{
245 struct spi_transfer *xfers = adc->xfers;
246
247 /*
248 * NB: SCLK has to be low before we toggle CS to avoid triggering the
249 * busy indication.
250 */
251 if (adc->spi->mode & SPI_CPOL)
252 return dev_err_probe(dev, err: -EINVAL,
253 fmt: "chain mode requires ~SPI_CPOL\n");
254
255 /*
256 * We only support CNV connected to CS in chain mode and we need CNV
257 * to be high during the transfer to trigger the conversion.
258 */
259 if (!(adc->spi->mode & SPI_CS_HIGH))
260 return dev_err_probe(dev, err: -EINVAL,
261 fmt: "chain mode requires SPI_CS_HIGH\n");
262
263 /* CNV has to be high for full conversion time before reading data. */
264 xfers[0].delay.value = adc->timing_spec->conv_ns;
265 xfers[0].delay.unit = SPI_DELAY_UNIT_NSECS;
266
267 xfers[1].rx_buf = adc->chain_mode_buf;
268 xfers[1].len = AD7944_SPI_BYTES(chan->scan_type) * n_chain_dev;
269 xfers[1].bits_per_word = chan->scan_type.realbits;
270
271 spi_message_init_with_transfers(m: &adc->msg, xfers, num_xfers: 2);
272
273 return devm_spi_optimize_message(dev, spi: adc->spi, msg: &adc->msg);
274}
275
276/*
277 * Unlike ad7944_3wire_cs_mode_init_msg(), this creates a message that reads
278 * during the conversion phase instead of the acquisition phase when reading
279 * a sample from the ADC. This is needed to be able to read at the maximum
280 * sample rate. It requires the SPI controller to have offload support and a
281 * high enough SCLK rate to read the sample during the conversion phase.
282 */
283static int ad7944_3wire_cs_mode_init_offload_msg(struct device *dev,
284 struct ad7944_adc *adc,
285 const struct iio_chan_spec *chan)
286{
287 struct spi_transfer *xfers = adc->offload_xfers;
288 int ret;
289
290 /*
291 * CS is tied to CNV and we need a low to high transition to start the
292 * conversion, so place CNV low for t_QUIET to prepare for this.
293 */
294 xfers[0].delay.value = AD7944_T_QUIET_NS;
295 xfers[0].delay.unit = SPI_DELAY_UNIT_NSECS;
296 /* CNV has to be high for a minimum time to trigger conversion. */
297 xfers[0].cs_change = 1;
298 xfers[0].cs_change_delay.value = AD7944_T_CNVH_NS;
299 xfers[0].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS;
300
301 /* Then we can read the previous sample during the conversion phase */
302 xfers[1].offload_flags = SPI_OFFLOAD_XFER_RX_STREAM;
303 xfers[1].len = AD7944_SPI_BYTES(chan->scan_type);
304 xfers[1].bits_per_word = chan->scan_type.realbits;
305
306 spi_message_init_with_transfers(m: &adc->offload_msg, xfers,
307 ARRAY_SIZE(adc->offload_xfers));
308
309 adc->offload_msg.offload = adc->offload;
310
311 ret = devm_spi_optimize_message(dev, spi: adc->spi, msg: &adc->offload_msg);
312 if (ret)
313 return dev_err_probe(dev, err: ret, fmt: "failed to prepare offload msg\n");
314
315 return 0;
316}
317
318/**
319 * ad7944_convert_and_acquire - Perform a single conversion and acquisition
320 * @adc: The ADC device structure
321 * Return: 0 on success, a negative error code on failure
322 *
323 * Perform a conversion and acquisition of a single sample using the
324 * pre-optimized adc->msg.
325 *
326 * Upon successful return adc->sample.raw will contain the conversion result
327 * (or adc->chain_mode_buf if the device is using chain mode).
328 */
329static int ad7944_convert_and_acquire(struct ad7944_adc *adc)
330{
331 int ret;
332
333 /*
334 * In 4-wire mode, the CNV line is held high for the entire conversion
335 * and acquisition process. In other modes adc->cnv is NULL and is
336 * ignored (CS is wired to CNV in those cases).
337 */
338 gpiod_set_value_cansleep(desc: adc->cnv, value: 1);
339 ret = spi_sync(spi: adc->spi, message: &adc->msg);
340 gpiod_set_value_cansleep(desc: adc->cnv, value: 0);
341
342 return ret;
343}
344
345static int ad7944_single_conversion(struct ad7944_adc *adc,
346 const struct iio_chan_spec *chan,
347 int *val)
348{
349 int ret;
350
351 ret = ad7944_convert_and_acquire(adc);
352 if (ret)
353 return ret;
354
355 if (adc->spi_mode == AD7944_SPI_MODE_CHAIN) {
356 if (chan->scan_type.realbits > 16)
357 *val = ((u32 *)adc->chain_mode_buf)[chan->scan_index];
358 else
359 *val = ((u16 *)adc->chain_mode_buf)[chan->scan_index];
360 } else {
361 if (chan->scan_type.realbits > 16)
362 *val = adc->sample.raw.u32;
363 else
364 *val = adc->sample.raw.u16;
365 }
366
367 if (chan->scan_type.sign == 's')
368 *val = sign_extend32(value: *val, index: chan->scan_type.realbits - 1);
369 else
370 *val &= GENMASK(chan->scan_type.realbits - 1, 0);
371
372 return IIO_VAL_INT;
373}
374
375static int ad7944_read_avail(struct iio_dev *indio_dev,
376 struct iio_chan_spec const *chan,
377 const int **vals, int *type, int *length,
378 long mask)
379{
380 struct ad7944_adc *adc = iio_priv(indio_dev);
381
382 switch (mask) {
383 case IIO_CHAN_INFO_SAMP_FREQ:
384 *vals = adc->sample_freq_range;
385 *type = IIO_VAL_INT;
386 return IIO_AVAIL_RANGE;
387 default:
388 return -EINVAL;
389 }
390}
391
392static int ad7944_read_raw(struct iio_dev *indio_dev,
393 const struct iio_chan_spec *chan,
394 int *val, int *val2, long info)
395{
396 struct ad7944_adc *adc = iio_priv(indio_dev);
397 int ret;
398
399 switch (info) {
400 case IIO_CHAN_INFO_RAW:
401 if (!iio_device_claim_direct(indio_dev))
402 return -EBUSY;
403
404 ret = ad7944_single_conversion(adc, chan, val);
405 iio_device_release_direct(indio_dev);
406 return ret;
407
408 case IIO_CHAN_INFO_SCALE:
409 switch (chan->type) {
410 case IIO_VOLTAGE:
411 *val = adc->ref_mv;
412
413 if (chan->scan_type.sign == 's')
414 *val2 = chan->scan_type.realbits - 1;
415 else
416 *val2 = chan->scan_type.realbits;
417
418 return IIO_VAL_FRACTIONAL_LOG2;
419 default:
420 return -EINVAL;
421 }
422
423 case IIO_CHAN_INFO_SAMP_FREQ:
424 *val = adc->offload_trigger_hz;
425 return IIO_VAL_INT;
426
427 default:
428 return -EINVAL;
429 }
430}
431
432static int ad7944_set_sample_freq(struct ad7944_adc *adc, int val)
433{
434 struct spi_offload_trigger_config config = {
435 .type = SPI_OFFLOAD_TRIGGER_PERIODIC,
436 .periodic = {
437 .frequency_hz = val,
438 },
439 };
440 int ret;
441
442 ret = spi_offload_trigger_validate(trigger: adc->offload_trigger, config: &config);
443 if (ret)
444 return ret;
445
446 adc->offload_trigger_hz = config.periodic.frequency_hz;
447
448 return 0;
449}
450
451static int ad7944_write_raw(struct iio_dev *indio_dev,
452 const struct iio_chan_spec *chan,
453 int val, int val2, long info)
454{
455 struct ad7944_adc *adc = iio_priv(indio_dev);
456
457 switch (info) {
458 case IIO_CHAN_INFO_SAMP_FREQ:
459 if (val < 1 || val > adc->sample_freq_range[2])
460 return -EINVAL;
461
462 return ad7944_set_sample_freq(adc, val);
463 default:
464 return -EINVAL;
465 }
466}
467
468static int ad7944_write_raw_get_fmt(struct iio_dev *indio_dev,
469 const struct iio_chan_spec *chan,
470 long mask)
471{
472 switch (mask) {
473 case IIO_CHAN_INFO_SAMP_FREQ:
474 return IIO_VAL_INT;
475 default:
476 return IIO_VAL_INT_PLUS_MICRO;
477 }
478}
479
480static const struct iio_info ad7944_iio_info = {
481 .read_avail = &ad7944_read_avail,
482 .read_raw = &ad7944_read_raw,
483 .write_raw = &ad7944_write_raw,
484 .write_raw_get_fmt = &ad7944_write_raw_get_fmt,
485};
486
487static int ad7944_offload_buffer_postenable(struct iio_dev *indio_dev)
488{
489 struct ad7944_adc *adc = iio_priv(indio_dev);
490 struct spi_offload_trigger_config config = {
491 .type = SPI_OFFLOAD_TRIGGER_PERIODIC,
492 .periodic = {
493 .frequency_hz = adc->offload_trigger_hz,
494 },
495 };
496 int ret;
497
498 gpiod_set_value_cansleep(desc: adc->turbo, value: 1);
499
500 ret = spi_offload_trigger_enable(offload: adc->offload, trigger: adc->offload_trigger,
501 config: &config);
502 if (ret)
503 gpiod_set_value_cansleep(desc: adc->turbo, value: 0);
504
505 return ret;
506}
507
508static int ad7944_offload_buffer_predisable(struct iio_dev *indio_dev)
509{
510 struct ad7944_adc *adc = iio_priv(indio_dev);
511
512 spi_offload_trigger_disable(offload: adc->offload, trigger: adc->offload_trigger);
513 gpiod_set_value_cansleep(desc: adc->turbo, value: 0);
514
515 return 0;
516}
517
518static const struct iio_buffer_setup_ops ad7944_offload_buffer_setup_ops = {
519 .postenable = &ad7944_offload_buffer_postenable,
520 .predisable = &ad7944_offload_buffer_predisable,
521};
522
523static irqreturn_t ad7944_trigger_handler(int irq, void *p)
524{
525 struct iio_poll_func *pf = p;
526 struct iio_dev *indio_dev = pf->indio_dev;
527 struct ad7944_adc *adc = iio_priv(indio_dev);
528 int ret;
529
530 ret = ad7944_convert_and_acquire(adc);
531 if (ret)
532 goto out;
533
534 if (adc->spi_mode == AD7944_SPI_MODE_CHAIN)
535 iio_push_to_buffers_with_timestamp(indio_dev, data: adc->chain_mode_buf,
536 timestamp: pf->timestamp);
537 else
538 iio_push_to_buffers_with_timestamp(indio_dev, data: &adc->sample.raw,
539 timestamp: pf->timestamp);
540
541out:
542 iio_trigger_notify_done(trig: indio_dev->trig);
543
544 return IRQ_HANDLED;
545}
546
547/**
548 * ad7944_chain_mode_alloc - allocate and initialize channel specs and buffers
549 * for daisy-chained devices
550 * @dev: The device for devm_ functions
551 * @chan_template: The channel template for the devices (array of 2 channels
552 * voltage and timestamp)
553 * @n_chain_dev: The number of devices in the chain
554 * @chain_chan: Pointer to receive the allocated channel specs
555 * @chain_mode_buf: Pointer to receive the allocated rx buffer
556 * @chain_scan_masks: Pointer to receive the allocated scan masks
557 * Return: 0 on success, a negative error code on failure
558 */
559static int ad7944_chain_mode_alloc(struct device *dev,
560 const struct iio_chan_spec *chan_template,
561 u32 n_chain_dev,
562 struct iio_chan_spec **chain_chan,
563 void **chain_mode_buf,
564 unsigned long **chain_scan_masks)
565{
566 struct iio_chan_spec *chan;
567 size_t chain_mode_buf_size;
568 unsigned long *scan_masks;
569 void *buf;
570 int i;
571
572 /* 1 channel for each device in chain plus 1 for soft timestamp */
573
574 chan = devm_kcalloc(dev, n: n_chain_dev + 1, size: sizeof(*chan), GFP_KERNEL);
575 if (!chan)
576 return -ENOMEM;
577
578 for (i = 0; i < n_chain_dev; i++) {
579 chan[i] = chan_template[0];
580
581 if (chan_template[0].differential) {
582 chan[i].channel = 2 * i;
583 chan[i].channel2 = 2 * i + 1;
584 } else {
585 chan[i].channel = i;
586 }
587
588 chan[i].scan_index = i;
589 }
590
591 /* soft timestamp */
592 chan[i] = chan_template[1];
593 chan[i].scan_index = i;
594
595 *chain_chan = chan;
596
597 /* 1 word for each voltage channel + aligned u64 for timestamp */
598
599 chain_mode_buf_size = ALIGN(n_chain_dev *
600 AD7944_SPI_BYTES(chan[0].scan_type), sizeof(u64)) + sizeof(u64);
601 buf = devm_kzalloc(dev, size: chain_mode_buf_size, GFP_KERNEL);
602 if (!buf)
603 return -ENOMEM;
604
605 *chain_mode_buf = buf;
606
607 /*
608 * Have to limit n_chain_dev due to current implementation of
609 * available_scan_masks.
610 */
611 if (n_chain_dev > BITS_PER_LONG)
612 return dev_err_probe(dev, err: -EINVAL,
613 fmt: "chain is limited to 32 devices\n");
614
615 scan_masks = devm_kcalloc(dev, n: 2, size: sizeof(*scan_masks), GFP_KERNEL);
616 if (!scan_masks)
617 return -ENOMEM;
618
619 /*
620 * Scan mask is needed since we always have to read all devices in the
621 * chain in one SPI transfer.
622 */
623 scan_masks[0] = GENMASK(n_chain_dev - 1, 0);
624
625 *chain_scan_masks = scan_masks;
626
627 return 0;
628}
629
630static const char * const ad7944_power_supplies[] = {
631 "avdd", "dvdd", "bvdd", "vio"
632};
633
634static const struct spi_offload_config ad7944_offload_config = {
635 .capability_flags = SPI_OFFLOAD_CAP_TRIGGER |
636 SPI_OFFLOAD_CAP_RX_STREAM_DMA,
637};
638
639static int ad7944_probe(struct spi_device *spi)
640{
641 const struct ad7944_chip_info *chip_info;
642 struct device *dev = &spi->dev;
643 struct iio_dev *indio_dev;
644 struct ad7944_adc *adc;
645 bool have_refin;
646 struct iio_chan_spec *chain_chan;
647 unsigned long *chain_scan_masks;
648 u32 n_chain_dev;
649 int ret, ref_mv;
650
651 indio_dev = devm_iio_device_alloc(parent: dev, sizeof_priv: sizeof(*adc));
652 if (!indio_dev)
653 return -ENOMEM;
654
655 adc = iio_priv(indio_dev);
656 adc->spi = spi;
657
658 chip_info = spi_get_device_match_data(sdev: spi);
659 if (!chip_info)
660 return dev_err_probe(dev, err: -EINVAL, fmt: "no chip info\n");
661
662 adc->timing_spec = chip_info->timing_spec;
663
664 adc->sample_freq_range[0] = 1; /* min */
665 adc->sample_freq_range[1] = 1; /* step */
666 adc->sample_freq_range[2] = chip_info->max_sample_rate_hz; /* max */
667
668 ret = device_property_match_property_string(dev, propname: "adi,spi-mode",
669 array: ad7944_spi_modes,
670 ARRAY_SIZE(ad7944_spi_modes));
671 /* absence of adi,spi-mode property means default mode */
672 if (ret == -EINVAL)
673 adc->spi_mode = AD7944_SPI_MODE_DEFAULT;
674 else if (ret < 0)
675 return dev_err_probe(dev, err: ret,
676 fmt: "getting adi,spi-mode property failed\n");
677 else
678 adc->spi_mode = ret;
679
680 /*
681 * Some chips use unusual word sizes, so check now instead of waiting
682 * for the first xfer.
683 */
684 if (!spi_is_bpw_supported(spi, bpw: chip_info->channels[0].scan_type.realbits))
685 return dev_err_probe(dev, err: -EINVAL,
686 fmt: "SPI host does not support %d bits per word\n",
687 chip_info->channels[0].scan_type.realbits);
688
689 ret = devm_regulator_bulk_get_enable(dev,
690 ARRAY_SIZE(ad7944_power_supplies),
691 id: ad7944_power_supplies);
692 if (ret)
693 return dev_err_probe(dev, err: ret,
694 fmt: "failed to get and enable supplies\n");
695
696 /*
697 * Sort out what is being used for the reference voltage. Options are:
698 * - internal reference: neither REF or REFIN is connected
699 * - internal reference with external buffer: REF not connected, REFIN
700 * is connected
701 * - external reference: REF is connected, REFIN is not connected
702 */
703
704 ret = devm_regulator_get_enable_read_voltage(dev, id: "ref");
705 if (ret < 0 && ret != -ENODEV)
706 return dev_err_probe(dev, err: ret, fmt: "failed to get REF voltage\n");
707
708 ref_mv = ret == -ENODEV ? 0 : ret / 1000;
709
710 ret = devm_regulator_get_enable_optional(dev, id: "refin");
711 if (ret < 0 && ret != -ENODEV)
712 return dev_err_probe(dev, err: ret, fmt: "failed to get REFIN voltage\n");
713
714 have_refin = ret != -ENODEV;
715
716 if (have_refin && ref_mv)
717 return dev_err_probe(dev, err: -EINVAL,
718 fmt: "cannot have both refin and ref supplies\n");
719
720 adc->ref_mv = ref_mv ?: AD7944_INTERNAL_REF_MV;
721
722 adc->cnv = devm_gpiod_get_optional(dev, con_id: "cnv", flags: GPIOD_OUT_LOW);
723 if (IS_ERR(ptr: adc->cnv))
724 return dev_err_probe(dev, err: PTR_ERR(ptr: adc->cnv),
725 fmt: "failed to get CNV GPIO\n");
726
727 if (!adc->cnv && adc->spi_mode == AD7944_SPI_MODE_DEFAULT)
728 return dev_err_probe(dev: &spi->dev, err: -EINVAL, fmt: "CNV GPIO is required\n");
729 if (adc->cnv && adc->spi_mode != AD7944_SPI_MODE_DEFAULT)
730 return dev_err_probe(dev: &spi->dev, err: -EINVAL,
731 fmt: "CNV GPIO in single and chain mode is not currently supported\n");
732
733 adc->turbo = devm_gpiod_get_optional(dev, con_id: "turbo", flags: GPIOD_OUT_LOW);
734 if (IS_ERR(ptr: adc->turbo))
735 return dev_err_probe(dev, err: PTR_ERR(ptr: adc->turbo),
736 fmt: "failed to get TURBO GPIO\n");
737
738 adc->always_turbo = device_property_present(dev, propname: "adi,always-turbo");
739
740 if (adc->turbo && adc->always_turbo)
741 return dev_err_probe(dev, err: -EINVAL,
742 fmt: "cannot have both turbo-gpios and adi,always-turbo\n");
743
744 if (adc->spi_mode == AD7944_SPI_MODE_CHAIN && adc->always_turbo)
745 return dev_err_probe(dev, err: -EINVAL,
746 fmt: "cannot have both chain mode and always turbo\n");
747
748 switch (adc->spi_mode) {
749 case AD7944_SPI_MODE_DEFAULT:
750 ret = ad7944_4wire_mode_init_msg(dev, adc, chan: &chip_info->channels[0]);
751 if (ret)
752 return ret;
753
754 break;
755 case AD7944_SPI_MODE_SINGLE:
756 ret = ad7944_3wire_cs_mode_init_msg(dev, adc, chan: &chip_info->channels[0]);
757 if (ret)
758 return ret;
759
760 break;
761 case AD7944_SPI_MODE_CHAIN:
762 ret = device_property_read_u32(dev, propname: "#daisy-chained-devices",
763 val: &n_chain_dev);
764 if (ret)
765 return dev_err_probe(dev, err: ret,
766 fmt: "failed to get #daisy-chained-devices\n");
767
768 ret = ad7944_chain_mode_alloc(dev, chan_template: chip_info->channels,
769 n_chain_dev, chain_chan: &chain_chan,
770 chain_mode_buf: &adc->chain_mode_buf,
771 chain_scan_masks: &chain_scan_masks);
772 if (ret)
773 return ret;
774
775 ret = ad7944_chain_mode_init_msg(dev, adc, chan: &chain_chan[0],
776 n_chain_dev);
777 if (ret)
778 return ret;
779
780 break;
781 }
782
783 indio_dev->name = chip_info->name;
784 indio_dev->modes = INDIO_DIRECT_MODE;
785 indio_dev->info = &ad7944_iio_info;
786
787 adc->offload = devm_spi_offload_get(dev, spi, config: &ad7944_offload_config);
788 ret = PTR_ERR_OR_ZERO(ptr: adc->offload);
789 if (ret && ret != -ENODEV)
790 return dev_err_probe(dev, err: ret, fmt: "failed to get offload\n");
791
792 /* Fall back to low speed usage when no SPI offload available. */
793 if (ret == -ENODEV) {
794 if (adc->spi_mode == AD7944_SPI_MODE_CHAIN) {
795 indio_dev->available_scan_masks = chain_scan_masks;
796 indio_dev->channels = chain_chan;
797 indio_dev->num_channels = n_chain_dev + 1;
798 } else {
799 indio_dev->channels = chip_info->channels;
800 indio_dev->num_channels = ARRAY_SIZE(chip_info->channels);
801 }
802
803 ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
804 iio_pollfunc_store_time,
805 ad7944_trigger_handler,
806 NULL);
807 if (ret)
808 return ret;
809 } else {
810 struct dma_chan *rx_dma;
811
812 if (adc->spi_mode != AD7944_SPI_MODE_SINGLE)
813 return dev_err_probe(dev, err: -EINVAL,
814 fmt: "offload only supported in single mode\n");
815
816 indio_dev->setup_ops = &ad7944_offload_buffer_setup_ops;
817 indio_dev->channels = chip_info->offload_channels;
818 indio_dev->num_channels = ARRAY_SIZE(chip_info->offload_channels);
819
820 adc->offload_trigger = devm_spi_offload_trigger_get(dev,
821 offload: adc->offload, type: SPI_OFFLOAD_TRIGGER_PERIODIC);
822 if (IS_ERR(ptr: adc->offload_trigger))
823 return dev_err_probe(dev, err: PTR_ERR(ptr: adc->offload_trigger),
824 fmt: "failed to get offload trigger\n");
825
826 ret = ad7944_set_sample_freq(adc, val: 2 * MEGA);
827 if (ret)
828 return dev_err_probe(dev, err: ret,
829 fmt: "failed to init sample rate\n");
830
831 rx_dma = devm_spi_offload_rx_stream_request_dma_chan(dev,
832 offload: adc->offload);
833 if (IS_ERR(ptr: rx_dma))
834 return dev_err_probe(dev, err: PTR_ERR(ptr: rx_dma),
835 fmt: "failed to get offload RX DMA\n");
836
837 /*
838 * REVISIT: ideally, we would confirm that the offload RX DMA
839 * buffer layout is the same as what is hard-coded in
840 * offload_channels. Right now, the only supported offload
841 * is the pulsar_adc project which always uses 32-bit word
842 * size for data values, regardless of the SPI bits per word.
843 */
844
845 ret = devm_iio_dmaengine_buffer_setup_with_handle(dev,
846 indio_dev, chan: rx_dma, dir: IIO_BUFFER_DIRECTION_IN);
847 if (ret)
848 return ret;
849
850 ret = ad7944_3wire_cs_mode_init_offload_msg(dev, adc,
851 chan: &chip_info->offload_channels[0]);
852 if (ret)
853 return ret;
854 }
855
856 return devm_iio_device_register(dev, indio_dev);
857}
858
859static const struct of_device_id ad7944_of_match[] = {
860 { .compatible = "adi,ad7944", .data = &ad7944_chip_info },
861 { .compatible = "adi,ad7985", .data = &ad7985_chip_info },
862 { .compatible = "adi,ad7986", .data = &ad7986_chip_info },
863 { }
864};
865MODULE_DEVICE_TABLE(of, ad7944_of_match);
866
867static const struct spi_device_id ad7944_spi_id[] = {
868 { "ad7944", (kernel_ulong_t)&ad7944_chip_info },
869 { "ad7985", (kernel_ulong_t)&ad7985_chip_info },
870 { "ad7986", (kernel_ulong_t)&ad7986_chip_info },
871 { }
872
873};
874MODULE_DEVICE_TABLE(spi, ad7944_spi_id);
875
876static struct spi_driver ad7944_driver = {
877 .driver = {
878 .name = "ad7944",
879 .of_match_table = ad7944_of_match,
880 },
881 .probe = ad7944_probe,
882 .id_table = ad7944_spi_id,
883};
884module_spi_driver(ad7944_driver);
885
886MODULE_AUTHOR("David Lechner <dlechner@baylibre.com>");
887MODULE_DESCRIPTION("Analog Devices AD7944 PulSAR ADC family driver");
888MODULE_LICENSE("GPL");
889MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER");
890

source code of linux/drivers/iio/adc/ad7944.c