1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Analog Devices AD5766, AD5767 |
4 | * Digital to Analog Converters driver |
5 | * Copyright 2019-2020 Analog Devices Inc. |
6 | */ |
7 | #include <linux/bitfield.h> |
8 | #include <linux/bitops.h> |
9 | #include <linux/delay.h> |
10 | #include <linux/device.h> |
11 | #include <linux/gpio/consumer.h> |
12 | #include <linux/iio/iio.h> |
13 | #include <linux/iio/triggered_buffer.h> |
14 | #include <linux/iio/trigger_consumer.h> |
15 | #include <linux/module.h> |
16 | #include <linux/spi/spi.h> |
17 | #include <asm/unaligned.h> |
18 | |
19 | #define AD5766_UPPER_WORD_SPI_MASK GENMASK(31, 16) |
20 | #define AD5766_LOWER_WORD_SPI_MASK GENMASK(15, 0) |
21 | #define AD5766_DITHER_SOURCE_MASK(ch) GENMASK(((2 * ch) + 1), (2 * ch)) |
22 | #define AD5766_DITHER_SOURCE(ch, source) BIT((ch * 2) + source) |
23 | #define AD5766_DITHER_SCALE_MASK(x) AD5766_DITHER_SOURCE_MASK(x) |
24 | #define AD5766_DITHER_SCALE(ch, scale) (scale << (ch * 2)) |
25 | #define AD5766_DITHER_ENABLE_MASK(ch) BIT(ch) |
26 | #define AD5766_DITHER_ENABLE(ch, state) ((!state) << ch) |
27 | #define AD5766_DITHER_INVERT_MASK(ch) BIT(ch) |
28 | #define AD5766_DITHER_INVERT(ch, state) (state << ch) |
29 | |
30 | #define AD5766_CMD_NOP_MUX_OUT 0x00 |
31 | #define AD5766_CMD_SDO_CNTRL 0x01 |
32 | #define AD5766_CMD_WR_IN_REG(x) (0x10 | ((x) & GENMASK(3, 0))) |
33 | #define AD5766_CMD_WR_DAC_REG(x) (0x20 | ((x) & GENMASK(3, 0))) |
34 | #define AD5766_CMD_SW_LDAC 0x30 |
35 | #define AD5766_CMD_SPAN_REG 0x40 |
36 | #define AD5766_CMD_WR_PWR_DITHER 0x51 |
37 | #define AD5766_CMD_WR_DAC_REG_ALL 0x60 |
38 | #define AD5766_CMD_SW_FULL_RESET 0x70 |
39 | #define AD5766_CMD_READBACK_REG(x) (0x80 | ((x) & GENMASK(3, 0))) |
40 | #define AD5766_CMD_DITHER_SIG_1 0x90 |
41 | #define AD5766_CMD_DITHER_SIG_2 0xA0 |
42 | #define AD5766_CMD_INV_DITHER 0xB0 |
43 | #define AD5766_CMD_DITHER_SCALE_1 0xC0 |
44 | #define AD5766_CMD_DITHER_SCALE_2 0xD0 |
45 | |
46 | #define AD5766_FULL_RESET_CODE 0x1234 |
47 | |
48 | enum ad5766_type { |
49 | ID_AD5766, |
50 | ID_AD5767, |
51 | }; |
52 | |
53 | enum ad5766_voltage_range { |
54 | AD5766_VOLTAGE_RANGE_M20V_0V, |
55 | AD5766_VOLTAGE_RANGE_M16V_to_0V, |
56 | AD5766_VOLTAGE_RANGE_M10V_to_0V, |
57 | AD5766_VOLTAGE_RANGE_M12V_to_14V, |
58 | AD5766_VOLTAGE_RANGE_M16V_to_10V, |
59 | AD5766_VOLTAGE_RANGE_M10V_to_6V, |
60 | AD5766_VOLTAGE_RANGE_M5V_to_5V, |
61 | AD5766_VOLTAGE_RANGE_M10V_to_10V, |
62 | }; |
63 | |
64 | /** |
65 | * struct ad5766_chip_info - chip specific information |
66 | * @num_channels: number of channels |
67 | * @channels: channel specification |
68 | */ |
69 | struct ad5766_chip_info { |
70 | unsigned int num_channels; |
71 | const struct iio_chan_spec *channels; |
72 | }; |
73 | |
74 | enum { |
75 | AD5766_DITHER_ENABLE, |
76 | AD5766_DITHER_INVERT, |
77 | AD5766_DITHER_SOURCE, |
78 | }; |
79 | |
80 | /* |
81 | * Dither signal can also be scaled. |
82 | * Available dither scale strings corresponding to "dither_scale" field in |
83 | * "struct ad5766_state". |
84 | */ |
85 | static const char * const ad5766_dither_scales[] = { |
86 | "1" , |
87 | "0.75" , |
88 | "0.5" , |
89 | "0.25" , |
90 | }; |
91 | |
92 | /** |
93 | * struct ad5766_state - driver instance specific data |
94 | * @spi: SPI device |
95 | * @lock: Lock used to restrict concurrent access to SPI device |
96 | * @chip_info: Chip model specific constants |
97 | * @gpio_reset: Reset GPIO, used to reset the device |
98 | * @crt_range: Current selected output range |
99 | * @dither_enable: Power enable bit for each channel dither block (for |
100 | * example, D15 = DAC 15,D8 = DAC 8, and D0 = DAC 0) |
101 | * 0 - Normal operation, 1 - Power down |
102 | * @dither_invert: Inverts the dither signal applied to the selected DAC |
103 | * outputs |
104 | * @dither_source: Selects between 2 possible sources: |
105 | * 1: N0, 2: N1 |
106 | * Two bits are used for each channel |
107 | * @dither_scale: Two bits are used for each of the 16 channels: |
108 | * 0: 1 SCALING, 1: 0.75 SCALING, 2: 0.5 SCALING, |
109 | * 3: 0.25 SCALING. |
110 | * @data: SPI transfer buffers |
111 | */ |
112 | struct ad5766_state { |
113 | struct spi_device *spi; |
114 | struct mutex lock; |
115 | const struct ad5766_chip_info *chip_info; |
116 | struct gpio_desc *gpio_reset; |
117 | enum ad5766_voltage_range crt_range; |
118 | u16 dither_enable; |
119 | u16 dither_invert; |
120 | u32 dither_source; |
121 | u32 dither_scale; |
122 | union { |
123 | u32 d32; |
124 | u16 w16[2]; |
125 | u8 b8[4]; |
126 | } data[3] __aligned(IIO_DMA_MINALIGN); |
127 | }; |
128 | |
129 | struct ad5766_span_tbl { |
130 | int min; |
131 | int max; |
132 | }; |
133 | |
134 | static const struct ad5766_span_tbl ad5766_span_tbl[] = { |
135 | [AD5766_VOLTAGE_RANGE_M20V_0V] = {-20, 0}, |
136 | [AD5766_VOLTAGE_RANGE_M16V_to_0V] = {.min: -16, .max: 0}, |
137 | [AD5766_VOLTAGE_RANGE_M10V_to_0V] = {.min: -10, .max: 0}, |
138 | [AD5766_VOLTAGE_RANGE_M12V_to_14V] = {.min: -12, .max: 14}, |
139 | [AD5766_VOLTAGE_RANGE_M16V_to_10V] = {.min: -16, .max: 10}, |
140 | [AD5766_VOLTAGE_RANGE_M10V_to_6V] = {.min: -10, .max: 6}, |
141 | [AD5766_VOLTAGE_RANGE_M5V_to_5V] = {.min: -5, .max: 5}, |
142 | [AD5766_VOLTAGE_RANGE_M10V_to_10V] = {.min: -10, .max: 10}, |
143 | }; |
144 | |
145 | static int __ad5766_spi_read(struct ad5766_state *st, u8 dac, int *val) |
146 | { |
147 | int ret; |
148 | struct spi_transfer xfers[] = { |
149 | { |
150 | .tx_buf = &st->data[0].d32, |
151 | .bits_per_word = 8, |
152 | .len = 3, |
153 | .cs_change = 1, |
154 | }, { |
155 | .tx_buf = &st->data[1].d32, |
156 | .rx_buf = &st->data[2].d32, |
157 | .bits_per_word = 8, |
158 | .len = 3, |
159 | }, |
160 | }; |
161 | |
162 | st->data[0].d32 = AD5766_CMD_READBACK_REG(dac); |
163 | st->data[1].d32 = AD5766_CMD_NOP_MUX_OUT; |
164 | |
165 | ret = spi_sync_transfer(spi: st->spi, xfers, ARRAY_SIZE(xfers)); |
166 | if (ret) |
167 | return ret; |
168 | |
169 | *val = st->data[2].w16[1]; |
170 | |
171 | return ret; |
172 | } |
173 | |
174 | static int __ad5766_spi_write(struct ad5766_state *st, u8 command, u16 data) |
175 | { |
176 | st->data[0].b8[0] = command; |
177 | put_unaligned_be16(val: data, p: &st->data[0].b8[1]); |
178 | |
179 | return spi_write(spi: st->spi, buf: &st->data[0].b8[0], len: 3); |
180 | } |
181 | |
182 | static int ad5766_read(struct iio_dev *indio_dev, u8 dac, int *val) |
183 | { |
184 | struct ad5766_state *st = iio_priv(indio_dev); |
185 | int ret; |
186 | |
187 | mutex_lock(&st->lock); |
188 | ret = __ad5766_spi_read(st, dac, val); |
189 | mutex_unlock(lock: &st->lock); |
190 | |
191 | return ret; |
192 | } |
193 | |
194 | static int ad5766_write(struct iio_dev *indio_dev, u8 dac, u16 data) |
195 | { |
196 | struct ad5766_state *st = iio_priv(indio_dev); |
197 | int ret; |
198 | |
199 | mutex_lock(&st->lock); |
200 | ret = __ad5766_spi_write(st, AD5766_CMD_WR_DAC_REG(dac), data); |
201 | mutex_unlock(lock: &st->lock); |
202 | |
203 | return ret; |
204 | } |
205 | |
206 | static int ad5766_reset(struct ad5766_state *st) |
207 | { |
208 | int ret; |
209 | |
210 | if (st->gpio_reset) { |
211 | gpiod_set_value_cansleep(desc: st->gpio_reset, value: 1); |
212 | ndelay(100); /* t_reset >= 100ns */ |
213 | gpiod_set_value_cansleep(desc: st->gpio_reset, value: 0); |
214 | } else { |
215 | ret = __ad5766_spi_write(st, AD5766_CMD_SW_FULL_RESET, |
216 | AD5766_FULL_RESET_CODE); |
217 | if (ret < 0) |
218 | return ret; |
219 | } |
220 | |
221 | /* |
222 | * Minimum time between a reset and the subsequent successful write is |
223 | * typically 25 ns |
224 | */ |
225 | ndelay(25); |
226 | |
227 | return 0; |
228 | } |
229 | |
230 | static int ad5766_read_raw(struct iio_dev *indio_dev, |
231 | struct iio_chan_spec const *chan, |
232 | int *val, |
233 | int *val2, |
234 | long m) |
235 | { |
236 | struct ad5766_state *st = iio_priv(indio_dev); |
237 | int ret; |
238 | |
239 | switch (m) { |
240 | case IIO_CHAN_INFO_RAW: |
241 | ret = ad5766_read(indio_dev, dac: chan->address, val); |
242 | if (ret) |
243 | return ret; |
244 | |
245 | return IIO_VAL_INT; |
246 | case IIO_CHAN_INFO_OFFSET: |
247 | *val = ad5766_span_tbl[st->crt_range].min; |
248 | |
249 | return IIO_VAL_INT; |
250 | case IIO_CHAN_INFO_SCALE: |
251 | *val = ad5766_span_tbl[st->crt_range].max - |
252 | ad5766_span_tbl[st->crt_range].min; |
253 | *val2 = st->chip_info->channels[0].scan_type.realbits; |
254 | |
255 | return IIO_VAL_FRACTIONAL_LOG2; |
256 | default: |
257 | return -EINVAL; |
258 | } |
259 | } |
260 | |
261 | static int ad5766_write_raw(struct iio_dev *indio_dev, |
262 | struct iio_chan_spec const *chan, |
263 | int val, |
264 | int val2, |
265 | long info) |
266 | { |
267 | switch (info) { |
268 | case IIO_CHAN_INFO_RAW: |
269 | { |
270 | const int max_val = GENMASK(chan->scan_type.realbits - 1, 0); |
271 | |
272 | if (val > max_val || val < 0) |
273 | return -EINVAL; |
274 | val <<= chan->scan_type.shift; |
275 | return ad5766_write(indio_dev, dac: chan->address, data: val); |
276 | } |
277 | default: |
278 | return -EINVAL; |
279 | } |
280 | } |
281 | |
282 | static const struct iio_info ad5766_info = { |
283 | .read_raw = ad5766_read_raw, |
284 | .write_raw = ad5766_write_raw, |
285 | }; |
286 | |
287 | static int ad5766_get_dither_source(struct iio_dev *dev, |
288 | const struct iio_chan_spec *chan) |
289 | { |
290 | struct ad5766_state *st = iio_priv(indio_dev: dev); |
291 | u32 source; |
292 | |
293 | source = st->dither_source & AD5766_DITHER_SOURCE_MASK(chan->channel); |
294 | source = source >> (chan->channel * 2); |
295 | source -= 1; |
296 | |
297 | return source; |
298 | } |
299 | |
300 | static int ad5766_set_dither_source(struct iio_dev *dev, |
301 | const struct iio_chan_spec *chan, |
302 | unsigned int source) |
303 | { |
304 | struct ad5766_state *st = iio_priv(indio_dev: dev); |
305 | uint16_t val; |
306 | int ret; |
307 | |
308 | st->dither_source &= ~AD5766_DITHER_SOURCE_MASK(chan->channel); |
309 | st->dither_source |= AD5766_DITHER_SOURCE(chan->channel, source); |
310 | |
311 | val = FIELD_GET(AD5766_LOWER_WORD_SPI_MASK, st->dither_source); |
312 | ret = ad5766_write(indio_dev: dev, AD5766_CMD_DITHER_SIG_1, data: val); |
313 | if (ret) |
314 | return ret; |
315 | |
316 | val = FIELD_GET(AD5766_UPPER_WORD_SPI_MASK, st->dither_source); |
317 | |
318 | return ad5766_write(indio_dev: dev, AD5766_CMD_DITHER_SIG_2, data: val); |
319 | } |
320 | |
321 | static int ad5766_get_dither_scale(struct iio_dev *dev, |
322 | const struct iio_chan_spec *chan) |
323 | { |
324 | struct ad5766_state *st = iio_priv(indio_dev: dev); |
325 | u32 scale; |
326 | |
327 | scale = st->dither_scale & AD5766_DITHER_SCALE_MASK(chan->channel); |
328 | |
329 | return (scale >> (chan->channel * 2)); |
330 | } |
331 | |
332 | static int ad5766_set_dither_scale(struct iio_dev *dev, |
333 | const struct iio_chan_spec *chan, |
334 | unsigned int scale) |
335 | { |
336 | int ret; |
337 | struct ad5766_state *st = iio_priv(indio_dev: dev); |
338 | uint16_t val; |
339 | |
340 | st->dither_scale &= ~AD5766_DITHER_SCALE_MASK(chan->channel); |
341 | st->dither_scale |= AD5766_DITHER_SCALE(chan->channel, scale); |
342 | |
343 | val = FIELD_GET(AD5766_LOWER_WORD_SPI_MASK, st->dither_scale); |
344 | ret = ad5766_write(indio_dev: dev, AD5766_CMD_DITHER_SCALE_1, data: val); |
345 | if (ret) |
346 | return ret; |
347 | val = FIELD_GET(AD5766_UPPER_WORD_SPI_MASK, st->dither_scale); |
348 | |
349 | return ad5766_write(indio_dev: dev, AD5766_CMD_DITHER_SCALE_2, data: val); |
350 | } |
351 | |
352 | static const struct iio_enum ad5766_dither_scale_enum = { |
353 | .items = ad5766_dither_scales, |
354 | .num_items = ARRAY_SIZE(ad5766_dither_scales), |
355 | .set = ad5766_set_dither_scale, |
356 | .get = ad5766_get_dither_scale, |
357 | }; |
358 | |
359 | static ssize_t ad5766_read_ext(struct iio_dev *indio_dev, |
360 | uintptr_t private, |
361 | const struct iio_chan_spec *chan, |
362 | char *buf) |
363 | { |
364 | struct ad5766_state *st = iio_priv(indio_dev); |
365 | |
366 | switch (private) { |
367 | case AD5766_DITHER_ENABLE: |
368 | return sprintf(buf, fmt: "%u\n" , |
369 | !(st->dither_enable & BIT(chan->channel))); |
370 | break; |
371 | case AD5766_DITHER_INVERT: |
372 | return sprintf(buf, fmt: "%u\n" , |
373 | !!(st->dither_invert & BIT(chan->channel))); |
374 | break; |
375 | case AD5766_DITHER_SOURCE: |
376 | return sprintf(buf, fmt: "%d\n" , |
377 | ad5766_get_dither_source(dev: indio_dev, chan)); |
378 | default: |
379 | return -EINVAL; |
380 | } |
381 | } |
382 | |
383 | static ssize_t ad5766_write_ext(struct iio_dev *indio_dev, |
384 | uintptr_t private, |
385 | const struct iio_chan_spec *chan, |
386 | const char *buf, size_t len) |
387 | { |
388 | struct ad5766_state *st = iio_priv(indio_dev); |
389 | bool readin; |
390 | int ret; |
391 | |
392 | ret = kstrtobool(s: buf, res: &readin); |
393 | if (ret) |
394 | return ret; |
395 | |
396 | switch (private) { |
397 | case AD5766_DITHER_ENABLE: |
398 | st->dither_enable &= ~AD5766_DITHER_ENABLE_MASK(chan->channel); |
399 | st->dither_enable |= AD5766_DITHER_ENABLE(chan->channel, |
400 | readin); |
401 | ret = ad5766_write(indio_dev, AD5766_CMD_WR_PWR_DITHER, |
402 | data: st->dither_enable); |
403 | break; |
404 | case AD5766_DITHER_INVERT: |
405 | st->dither_invert &= ~AD5766_DITHER_INVERT_MASK(chan->channel); |
406 | st->dither_invert |= AD5766_DITHER_INVERT(chan->channel, |
407 | readin); |
408 | ret = ad5766_write(indio_dev, AD5766_CMD_INV_DITHER, |
409 | data: st->dither_invert); |
410 | break; |
411 | case AD5766_DITHER_SOURCE: |
412 | ret = ad5766_set_dither_source(dev: indio_dev, chan, source: readin); |
413 | break; |
414 | default: |
415 | return -EINVAL; |
416 | } |
417 | |
418 | return ret ? ret : len; |
419 | } |
420 | |
421 | #define _AD5766_CHAN_EXT_INFO(_name, _what, _shared) { \ |
422 | .name = _name, \ |
423 | .read = ad5766_read_ext, \ |
424 | .write = ad5766_write_ext, \ |
425 | .private = _what, \ |
426 | .shared = _shared, \ |
427 | } |
428 | |
429 | static const struct iio_chan_spec_ext_info ad5766_ext_info[] = { |
430 | |
431 | _AD5766_CHAN_EXT_INFO("dither_enable" , AD5766_DITHER_ENABLE, |
432 | IIO_SEPARATE), |
433 | _AD5766_CHAN_EXT_INFO("dither_invert" , AD5766_DITHER_INVERT, |
434 | IIO_SEPARATE), |
435 | _AD5766_CHAN_EXT_INFO("dither_source" , AD5766_DITHER_SOURCE, |
436 | IIO_SEPARATE), |
437 | IIO_ENUM("dither_scale" , IIO_SEPARATE, &ad5766_dither_scale_enum), |
438 | IIO_ENUM_AVAILABLE("dither_scale" , IIO_SEPARATE, |
439 | &ad5766_dither_scale_enum), |
440 | {} |
441 | }; |
442 | |
443 | #define AD576x_CHANNEL(_chan, _bits) { \ |
444 | .type = IIO_VOLTAGE, \ |
445 | .indexed = 1, \ |
446 | .output = 1, \ |
447 | .channel = (_chan), \ |
448 | .address = (_chan), \ |
449 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ |
450 | .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | \ |
451 | BIT(IIO_CHAN_INFO_SCALE), \ |
452 | .scan_index = (_chan), \ |
453 | .scan_type = { \ |
454 | .sign = 'u', \ |
455 | .realbits = (_bits), \ |
456 | .storagebits = 16, \ |
457 | .shift = 16 - (_bits), \ |
458 | }, \ |
459 | .ext_info = ad5766_ext_info, \ |
460 | } |
461 | |
462 | #define DECLARE_AD576x_CHANNELS(_name, _bits) \ |
463 | const struct iio_chan_spec _name[] = { \ |
464 | AD576x_CHANNEL(0, (_bits)), \ |
465 | AD576x_CHANNEL(1, (_bits)), \ |
466 | AD576x_CHANNEL(2, (_bits)), \ |
467 | AD576x_CHANNEL(3, (_bits)), \ |
468 | AD576x_CHANNEL(4, (_bits)), \ |
469 | AD576x_CHANNEL(5, (_bits)), \ |
470 | AD576x_CHANNEL(6, (_bits)), \ |
471 | AD576x_CHANNEL(7, (_bits)), \ |
472 | AD576x_CHANNEL(8, (_bits)), \ |
473 | AD576x_CHANNEL(9, (_bits)), \ |
474 | AD576x_CHANNEL(10, (_bits)), \ |
475 | AD576x_CHANNEL(11, (_bits)), \ |
476 | AD576x_CHANNEL(12, (_bits)), \ |
477 | AD576x_CHANNEL(13, (_bits)), \ |
478 | AD576x_CHANNEL(14, (_bits)), \ |
479 | AD576x_CHANNEL(15, (_bits)), \ |
480 | } |
481 | |
482 | static DECLARE_AD576x_CHANNELS(ad5766_channels, 16); |
483 | static DECLARE_AD576x_CHANNELS(ad5767_channels, 12); |
484 | |
485 | static const struct ad5766_chip_info ad5766_chip_infos[] = { |
486 | [ID_AD5766] = { |
487 | .num_channels = ARRAY_SIZE(ad5766_channels), |
488 | .channels = ad5766_channels, |
489 | }, |
490 | [ID_AD5767] = { |
491 | .num_channels = ARRAY_SIZE(ad5767_channels), |
492 | .channels = ad5767_channels, |
493 | }, |
494 | }; |
495 | |
496 | static int ad5766_get_output_range(struct ad5766_state *st) |
497 | { |
498 | int i, ret, min, max, tmp[2]; |
499 | |
500 | ret = device_property_read_u32_array(dev: &st->spi->dev, |
501 | propname: "output-range-microvolts" , |
502 | val: tmp, nval: 2); |
503 | if (ret) |
504 | return ret; |
505 | |
506 | min = tmp[0] / 1000000; |
507 | max = tmp[1] / 1000000; |
508 | for (i = 0; i < ARRAY_SIZE(ad5766_span_tbl); i++) { |
509 | if (ad5766_span_tbl[i].min != min || |
510 | ad5766_span_tbl[i].max != max) |
511 | continue; |
512 | |
513 | st->crt_range = i; |
514 | |
515 | return 0; |
516 | } |
517 | |
518 | return -EINVAL; |
519 | } |
520 | |
521 | static int ad5766_default_setup(struct ad5766_state *st) |
522 | { |
523 | uint16_t val; |
524 | int ret, i; |
525 | |
526 | /* Always issue a reset before writing to the span register. */ |
527 | ret = ad5766_reset(st); |
528 | if (ret) |
529 | return ret; |
530 | |
531 | ret = ad5766_get_output_range(st); |
532 | if (ret) |
533 | return ret; |
534 | |
535 | /* Dither power down */ |
536 | st->dither_enable = GENMASK(15, 0); |
537 | ret = __ad5766_spi_write(st, AD5766_CMD_WR_PWR_DITHER, |
538 | data: st->dither_enable); |
539 | if (ret) |
540 | return ret; |
541 | |
542 | st->dither_source = 0; |
543 | for (i = 0; i < ARRAY_SIZE(ad5766_channels); i++) |
544 | st->dither_source |= AD5766_DITHER_SOURCE(i, 0); |
545 | val = FIELD_GET(AD5766_LOWER_WORD_SPI_MASK, st->dither_source); |
546 | ret = __ad5766_spi_write(st, AD5766_CMD_DITHER_SIG_1, data: val); |
547 | if (ret) |
548 | return ret; |
549 | |
550 | val = FIELD_GET(AD5766_UPPER_WORD_SPI_MASK, st->dither_source); |
551 | ret = __ad5766_spi_write(st, AD5766_CMD_DITHER_SIG_2, data: val); |
552 | if (ret) |
553 | return ret; |
554 | |
555 | st->dither_scale = 0; |
556 | val = FIELD_GET(AD5766_LOWER_WORD_SPI_MASK, st->dither_scale); |
557 | ret = __ad5766_spi_write(st, AD5766_CMD_DITHER_SCALE_1, data: val); |
558 | if (ret) |
559 | return ret; |
560 | |
561 | val = FIELD_GET(AD5766_UPPER_WORD_SPI_MASK, st->dither_scale); |
562 | ret = __ad5766_spi_write(st, AD5766_CMD_DITHER_SCALE_2, data: val); |
563 | if (ret) |
564 | return ret; |
565 | |
566 | st->dither_invert = 0; |
567 | ret = __ad5766_spi_write(st, AD5766_CMD_INV_DITHER, data: st->dither_invert); |
568 | if (ret) |
569 | return ret; |
570 | |
571 | return __ad5766_spi_write(st, AD5766_CMD_SPAN_REG, data: st->crt_range); |
572 | } |
573 | |
574 | static irqreturn_t ad5766_trigger_handler(int irq, void *p) |
575 | { |
576 | struct iio_poll_func *pf = p; |
577 | struct iio_dev *indio_dev = pf->indio_dev; |
578 | struct iio_buffer *buffer = indio_dev->buffer; |
579 | struct ad5766_state *st = iio_priv(indio_dev); |
580 | int ret, ch, i; |
581 | u16 data[ARRAY_SIZE(ad5766_channels)]; |
582 | |
583 | ret = iio_pop_from_buffer(buffer, data); |
584 | if (ret) |
585 | goto done; |
586 | |
587 | i = 0; |
588 | mutex_lock(&st->lock); |
589 | for_each_set_bit(ch, indio_dev->active_scan_mask, |
590 | st->chip_info->num_channels - 1) |
591 | __ad5766_spi_write(st, AD5766_CMD_WR_IN_REG(ch), data: data[i++]); |
592 | |
593 | __ad5766_spi_write(st, AD5766_CMD_SW_LDAC, |
594 | data: *indio_dev->active_scan_mask); |
595 | mutex_unlock(lock: &st->lock); |
596 | |
597 | done: |
598 | iio_trigger_notify_done(trig: indio_dev->trig); |
599 | |
600 | return IRQ_HANDLED; |
601 | } |
602 | |
603 | static int ad5766_probe(struct spi_device *spi) |
604 | { |
605 | enum ad5766_type type; |
606 | struct iio_dev *indio_dev; |
607 | struct ad5766_state *st; |
608 | int ret; |
609 | |
610 | indio_dev = devm_iio_device_alloc(parent: &spi->dev, sizeof_priv: sizeof(*st)); |
611 | if (!indio_dev) |
612 | return -ENOMEM; |
613 | |
614 | st = iio_priv(indio_dev); |
615 | mutex_init(&st->lock); |
616 | |
617 | st->spi = spi; |
618 | type = spi_get_device_id(sdev: spi)->driver_data; |
619 | st->chip_info = &ad5766_chip_infos[type]; |
620 | |
621 | indio_dev->channels = st->chip_info->channels; |
622 | indio_dev->num_channels = st->chip_info->num_channels; |
623 | indio_dev->info = &ad5766_info; |
624 | indio_dev->name = spi_get_device_id(sdev: spi)->name; |
625 | indio_dev->modes = INDIO_DIRECT_MODE; |
626 | |
627 | st->gpio_reset = devm_gpiod_get_optional(dev: &st->spi->dev, con_id: "reset" , |
628 | flags: GPIOD_OUT_LOW); |
629 | if (IS_ERR(ptr: st->gpio_reset)) |
630 | return PTR_ERR(ptr: st->gpio_reset); |
631 | |
632 | ret = ad5766_default_setup(st); |
633 | if (ret) |
634 | return ret; |
635 | |
636 | /* Configure trigger buffer */ |
637 | ret = devm_iio_triggered_buffer_setup_ext(dev: &spi->dev, indio_dev, NULL, |
638 | thread: ad5766_trigger_handler, |
639 | direction: IIO_BUFFER_DIRECTION_OUT, |
640 | NULL, |
641 | NULL); |
642 | if (ret) |
643 | return ret; |
644 | |
645 | return devm_iio_device_register(&spi->dev, indio_dev); |
646 | } |
647 | |
648 | static const struct of_device_id ad5766_dt_match[] = { |
649 | { .compatible = "adi,ad5766" }, |
650 | { .compatible = "adi,ad5767" }, |
651 | {} |
652 | }; |
653 | MODULE_DEVICE_TABLE(of, ad5766_dt_match); |
654 | |
655 | static const struct spi_device_id ad5766_spi_ids[] = { |
656 | { "ad5766" , ID_AD5766 }, |
657 | { "ad5767" , ID_AD5767 }, |
658 | {} |
659 | }; |
660 | MODULE_DEVICE_TABLE(spi, ad5766_spi_ids); |
661 | |
662 | static struct spi_driver ad5766_driver = { |
663 | .driver = { |
664 | .name = "ad5766" , |
665 | .of_match_table = ad5766_dt_match, |
666 | }, |
667 | .probe = ad5766_probe, |
668 | .id_table = ad5766_spi_ids, |
669 | }; |
670 | module_spi_driver(ad5766_driver); |
671 | |
672 | MODULE_AUTHOR("Denis-Gabriel Gheorghescu <denis.gheorghescu@analog.com>" ); |
673 | MODULE_DESCRIPTION("Analog Devices AD5766/AD5767 DACs" ); |
674 | MODULE_LICENSE("GPL v2" ); |
675 | |