1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2015 Endless Mobile, Inc.
4 * Author: Carlo Caione <carlo@endlessm.com>
5 * Copyright (c) 2016 BayLibre, SAS.
6 * Author: Jerome Brunet <jbrunet@baylibre.com>
7 */
8
9#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11#include <linux/io.h>
12#include <linux/module.h>
13#include <linux/irq.h>
14#include <linux/irqdomain.h>
15#include <linux/irqchip.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18
19#define MAX_NUM_CHANNEL 64
20#define MAX_INPUT_MUX 256
21
22#define REG_EDGE_POL 0x00
23#define REG_PIN_03_SEL 0x04
24#define REG_PIN_47_SEL 0x08
25#define REG_FILTER_SEL 0x0c
26
27/* use for A1 like chips */
28#define REG_PIN_A1_SEL 0x04
29
30/*
31 * Note: The S905X3 datasheet reports that BOTH_EDGE is controlled by
32 * bits 24 to 31. Tests on the actual HW show that these bits are
33 * stuck at 0. Bits 8 to 15 are responsive and have the expected
34 * effect.
35 */
36#define REG_EDGE_POL_EDGE(params, x) BIT((params)->edge_single_offset + (x))
37#define REG_EDGE_POL_LOW(params, x) BIT((params)->pol_low_offset + (x))
38#define REG_BOTH_EDGE(params, x) BIT((params)->edge_both_offset + (x))
39#define REG_EDGE_POL_MASK(params, x) ( \
40 REG_EDGE_POL_EDGE(params, x) | \
41 REG_EDGE_POL_LOW(params, x) | \
42 REG_BOTH_EDGE(params, x))
43#define REG_PIN_SEL_SHIFT(x) (((x) % 4) * 8)
44#define REG_FILTER_SEL_SHIFT(x) ((x) * 4)
45
46struct meson_gpio_irq_controller;
47static void meson8_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl,
48 unsigned int channel, unsigned long hwirq);
49static void meson_gpio_irq_init_dummy(struct meson_gpio_irq_controller *ctl);
50static void meson_a1_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl,
51 unsigned int channel,
52 unsigned long hwirq);
53static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl);
54static int meson8_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
55 unsigned int type, u32 *channel_hwirq);
56static int meson_s4_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
57 unsigned int type, u32 *channel_hwirq);
58
59struct irq_ctl_ops {
60 void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl,
61 unsigned int channel, unsigned long hwirq);
62 void (*gpio_irq_init)(struct meson_gpio_irq_controller *ctl);
63 int (*gpio_irq_set_type)(struct meson_gpio_irq_controller *ctl,
64 unsigned int type, u32 *channel_hwirq);
65};
66
67struct meson_gpio_irq_params {
68 unsigned int nr_hwirq;
69 unsigned int nr_channels;
70 bool support_edge_both;
71 unsigned int edge_both_offset;
72 unsigned int edge_single_offset;
73 unsigned int edge_pol_reg;
74 unsigned int pol_low_offset;
75 unsigned int pin_sel_mask;
76 struct irq_ctl_ops ops;
77};
78
79#define INIT_MESON_COMMON(irqs, init, sel, type) \
80 .nr_hwirq = irqs, \
81 .ops = { \
82 .gpio_irq_init = init, \
83 .gpio_irq_sel_pin = sel, \
84 .gpio_irq_set_type = type, \
85 },
86
87#define INIT_MESON8_COMMON_DATA(irqs) \
88 INIT_MESON_COMMON(irqs, meson_gpio_irq_init_dummy, \
89 meson8_gpio_irq_sel_pin, \
90 meson8_gpio_irq_set_type) \
91 .edge_single_offset = 0, \
92 .pol_low_offset = 16, \
93 .pin_sel_mask = 0xff, \
94 .nr_channels = 8, \
95
96#define INIT_MESON_A1_COMMON_DATA(irqs) \
97 INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \
98 meson_a1_gpio_irq_sel_pin, \
99 meson8_gpio_irq_set_type) \
100 .support_edge_both = true, \
101 .edge_both_offset = 16, \
102 .edge_single_offset = 8, \
103 .pol_low_offset = 0, \
104 .pin_sel_mask = 0x7f, \
105 .nr_channels = 8, \
106
107#define INIT_MESON_A4_AO_COMMON_DATA(irqs) \
108 INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \
109 meson_a1_gpio_irq_sel_pin, \
110 meson_s4_gpio_irq_set_type) \
111 .support_edge_both = true, \
112 .edge_both_offset = 0, \
113 .edge_single_offset = 12, \
114 .edge_pol_reg = 0x8, \
115 .pol_low_offset = 0, \
116 .pin_sel_mask = 0xff, \
117 .nr_channels = 2, \
118
119#define INIT_MESON_S4_COMMON_DATA(irqs) \
120 INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \
121 meson_a1_gpio_irq_sel_pin, \
122 meson_s4_gpio_irq_set_type) \
123 .support_edge_both = true, \
124 .edge_both_offset = 0, \
125 .edge_single_offset = 12, \
126 .edge_pol_reg = 0x1c, \
127 .pol_low_offset = 0, \
128 .pin_sel_mask = 0xff, \
129 .nr_channels = 12, \
130
131static const struct meson_gpio_irq_params meson8_params = {
132 INIT_MESON8_COMMON_DATA(134)
133};
134
135static const struct meson_gpio_irq_params meson8b_params = {
136 INIT_MESON8_COMMON_DATA(119)
137};
138
139static const struct meson_gpio_irq_params gxbb_params = {
140 INIT_MESON8_COMMON_DATA(133)
141};
142
143static const struct meson_gpio_irq_params gxl_params = {
144 INIT_MESON8_COMMON_DATA(110)
145};
146
147static const struct meson_gpio_irq_params axg_params = {
148 INIT_MESON8_COMMON_DATA(100)
149};
150
151static const struct meson_gpio_irq_params sm1_params = {
152 INIT_MESON8_COMMON_DATA(100)
153 .support_edge_both = true,
154 .edge_both_offset = 8,
155};
156
157static const struct meson_gpio_irq_params a1_params = {
158 INIT_MESON_A1_COMMON_DATA(62)
159};
160
161static const struct meson_gpio_irq_params a4_params = {
162 INIT_MESON_S4_COMMON_DATA(81)
163};
164
165static const struct meson_gpio_irq_params a4_ao_params = {
166 INIT_MESON_A4_AO_COMMON_DATA(8)
167};
168
169static const struct meson_gpio_irq_params a5_params = {
170 INIT_MESON_S4_COMMON_DATA(99)
171};
172
173static const struct meson_gpio_irq_params s4_params = {
174 INIT_MESON_S4_COMMON_DATA(82)
175};
176
177static const struct meson_gpio_irq_params c3_params = {
178 INIT_MESON_S4_COMMON_DATA(55)
179};
180
181static const struct meson_gpio_irq_params t7_params = {
182 INIT_MESON_S4_COMMON_DATA(157)
183};
184
185static const struct of_device_id meson_irq_gpio_matches[] __maybe_unused = {
186 { .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params },
187 { .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params },
188 { .compatible = "amlogic,meson-gxbb-gpio-intc", .data = &gxbb_params },
189 { .compatible = "amlogic,meson-gxl-gpio-intc", .data = &gxl_params },
190 { .compatible = "amlogic,meson-axg-gpio-intc", .data = &axg_params },
191 { .compatible = "amlogic,meson-g12a-gpio-intc", .data = &axg_params },
192 { .compatible = "amlogic,meson-sm1-gpio-intc", .data = &sm1_params },
193 { .compatible = "amlogic,meson-a1-gpio-intc", .data = &a1_params },
194 { .compatible = "amlogic,meson-s4-gpio-intc", .data = &s4_params },
195 { .compatible = "amlogic,a4-gpio-ao-intc", .data = &a4_ao_params },
196 { .compatible = "amlogic,a4-gpio-intc", .data = &a4_params },
197 { .compatible = "amlogic,a5-gpio-intc", .data = &a5_params },
198 { .compatible = "amlogic,c3-gpio-intc", .data = &c3_params },
199 { .compatible = "amlogic,t7-gpio-intc", .data = &t7_params },
200 { }
201};
202
203struct meson_gpio_irq_controller {
204 const struct meson_gpio_irq_params *params;
205 void __iomem *base;
206 u32 channel_irqs[MAX_NUM_CHANNEL];
207 DECLARE_BITMAP(channel_map, MAX_NUM_CHANNEL);
208 raw_spinlock_t lock;
209};
210
211static void meson_gpio_irq_update_bits(struct meson_gpio_irq_controller *ctl,
212 unsigned int reg, u32 mask, u32 val)
213{
214 unsigned long flags;
215 u32 tmp;
216
217 raw_spin_lock_irqsave(&ctl->lock, flags);
218
219 tmp = readl_relaxed(ctl->base + reg);
220 tmp &= ~mask;
221 tmp |= val;
222 writel_relaxed(tmp, ctl->base + reg);
223
224 raw_spin_unlock_irqrestore(&ctl->lock, flags);
225}
226
227static void meson_gpio_irq_init_dummy(struct meson_gpio_irq_controller *ctl)
228{
229}
230
231static void meson8_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl,
232 unsigned int channel, unsigned long hwirq)
233{
234 unsigned int reg_offset;
235 unsigned int bit_offset;
236
237 reg_offset = (channel < 4) ? REG_PIN_03_SEL : REG_PIN_47_SEL;
238 bit_offset = REG_PIN_SEL_SHIFT(channel);
239
240 meson_gpio_irq_update_bits(ctl, reg: reg_offset,
241 mask: ctl->params->pin_sel_mask << bit_offset,
242 val: hwirq << bit_offset);
243}
244
245static void meson_a1_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl,
246 unsigned int channel,
247 unsigned long hwirq)
248{
249 unsigned int reg_offset;
250 unsigned int bit_offset;
251
252 bit_offset = ((channel % 2) == 0) ? 0 : 16;
253 reg_offset = REG_PIN_A1_SEL + ((channel / 2) << 2);
254
255 meson_gpio_irq_update_bits(ctl, reg: reg_offset,
256 mask: ctl->params->pin_sel_mask << bit_offset,
257 val: hwirq << bit_offset);
258}
259
260/* For a1 or later chips like a1 there is a switch to enable/disable irq */
261static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl)
262{
263 meson_gpio_irq_update_bits(ctl, REG_EDGE_POL, BIT(31), BIT(31));
264}
265
266static int
267meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl,
268 unsigned long hwirq,
269 u32 **channel_hwirq)
270{
271 unsigned long flags;
272 unsigned int idx;
273
274 raw_spin_lock_irqsave(&ctl->lock, flags);
275
276 /* Find a free channel */
277 idx = find_first_zero_bit(addr: ctl->channel_map, size: ctl->params->nr_channels);
278 if (idx >= ctl->params->nr_channels) {
279 raw_spin_unlock_irqrestore(&ctl->lock, flags);
280 pr_err("No channel available\n");
281 return -ENOSPC;
282 }
283
284 /* Mark the channel as used */
285 set_bit(nr: idx, addr: ctl->channel_map);
286
287 raw_spin_unlock_irqrestore(&ctl->lock, flags);
288
289 /*
290 * Setup the mux of the channel to route the signal of the pad
291 * to the appropriate input of the GIC
292 */
293 ctl->params->ops.gpio_irq_sel_pin(ctl, idx, hwirq);
294
295 /*
296 * Get the hwirq number assigned to this channel through
297 * a pointer the channel_irq table. The added benefit of this
298 * method is that we can also retrieve the channel index with
299 * it, using the table base.
300 */
301 *channel_hwirq = &(ctl->channel_irqs[idx]);
302
303 pr_debug("hwirq %lu assigned to channel %d - irq %u\n",
304 hwirq, idx, **channel_hwirq);
305
306 return 0;
307}
308
309static unsigned int
310meson_gpio_irq_get_channel_idx(struct meson_gpio_irq_controller *ctl,
311 u32 *channel_hwirq)
312{
313 return channel_hwirq - ctl->channel_irqs;
314}
315
316static void
317meson_gpio_irq_release_channel(struct meson_gpio_irq_controller *ctl,
318 u32 *channel_hwirq)
319{
320 unsigned int idx;
321
322 idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
323 clear_bit(nr: idx, addr: ctl->channel_map);
324}
325
326static int meson8_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
327 unsigned int type, u32 *channel_hwirq)
328{
329 const struct meson_gpio_irq_params *params = ctl->params;
330 unsigned int idx;
331 u32 val = 0;
332
333 idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
334
335 /*
336 * The controller has a filter block to operate in either LEVEL or
337 * EDGE mode, then signal is sent to the GIC. To enable LEVEL_LOW and
338 * EDGE_FALLING support (which the GIC does not support), the filter
339 * block is also able to invert the input signal it gets before
340 * providing it to the GIC.
341 */
342 type &= IRQ_TYPE_SENSE_MASK;
343
344 /*
345 * New controller support EDGE_BOTH trigger. This setting takes
346 * precedence over the other edge/polarity settings
347 */
348 if (type == IRQ_TYPE_EDGE_BOTH) {
349 if (!params->support_edge_both)
350 return -EINVAL;
351
352 val |= REG_BOTH_EDGE(params, idx);
353 } else {
354 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
355 val |= REG_EDGE_POL_EDGE(params, idx);
356
357 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))
358 val |= REG_EDGE_POL_LOW(params, idx);
359 }
360
361 meson_gpio_irq_update_bits(ctl, REG_EDGE_POL,
362 REG_EDGE_POL_MASK(params, idx), val);
363
364 return 0;
365}
366
367/*
368 * gpio irq relative registers for s4
369 * -PADCTRL_GPIO_IRQ_CTRL0
370 * bit[31]: enable/disable all the irq lines
371 * bit[12-23]: single edge trigger
372 * bit[0-11]: polarity trigger
373 *
374 * -PADCTRL_GPIO_IRQ_CTRL[X]
375 * bit[0-16]: 7 bits to choose gpio source for irq line 2*[X] - 2
376 * bit[16-22]:7 bits to choose gpio source for irq line 2*[X] - 1
377 * where X = 1-6
378 *
379 * -PADCTRL_GPIO_IRQ_CTRL[7]
380 * bit[0-11]: both edge trigger
381 */
382static int meson_s4_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
383 unsigned int type, u32 *channel_hwirq)
384{
385 const struct meson_gpio_irq_params *params = ctl->params;
386 unsigned int idx;
387 u32 val = 0;
388
389 idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
390
391 type &= IRQ_TYPE_SENSE_MASK;
392
393 meson_gpio_irq_update_bits(ctl, reg: params->edge_pol_reg, BIT(idx), val: 0);
394
395 if (type == IRQ_TYPE_EDGE_BOTH) {
396 val = BIT(ctl->params->edge_both_offset + idx);
397 meson_gpio_irq_update_bits(ctl, reg: params->edge_pol_reg, mask: val, val);
398 return 0;
399 }
400
401 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))
402 val |= BIT(ctl->params->pol_low_offset + idx);
403
404 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
405 val |= BIT(ctl->params->edge_single_offset + idx);
406
407 meson_gpio_irq_update_bits(ctl, reg: params->edge_pol_reg,
408 BIT(idx) | BIT(12 + idx), val);
409 return 0;
410};
411
412static unsigned int meson_gpio_irq_type_output(unsigned int type)
413{
414 unsigned int sense = type & IRQ_TYPE_SENSE_MASK;
415
416 type &= ~IRQ_TYPE_SENSE_MASK;
417
418 /*
419 * The polarity of the signal provided to the GIC should always
420 * be high.
421 */
422 if (sense & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
423 type |= IRQ_TYPE_LEVEL_HIGH;
424 else
425 type |= IRQ_TYPE_EDGE_RISING;
426
427 return type;
428}
429
430static int meson_gpio_irq_set_type(struct irq_data *data, unsigned int type)
431{
432 struct meson_gpio_irq_controller *ctl = data->domain->host_data;
433 u32 *channel_hwirq = irq_data_get_irq_chip_data(d: data);
434 int ret;
435
436 ret = ctl->params->ops.gpio_irq_set_type(ctl, type, channel_hwirq);
437 if (ret)
438 return ret;
439
440 return irq_chip_set_type_parent(data,
441 type: meson_gpio_irq_type_output(type));
442}
443
444static struct irq_chip meson_gpio_irq_chip = {
445 .name = "meson-gpio-irqchip",
446 .irq_mask = irq_chip_mask_parent,
447 .irq_unmask = irq_chip_unmask_parent,
448 .irq_eoi = irq_chip_eoi_parent,
449 .irq_set_type = meson_gpio_irq_set_type,
450 .irq_retrigger = irq_chip_retrigger_hierarchy,
451#ifdef CONFIG_SMP
452 .irq_set_affinity = irq_chip_set_affinity_parent,
453#endif
454 .flags = IRQCHIP_SET_TYPE_MASKED,
455};
456
457static int meson_gpio_irq_domain_translate(struct irq_domain *domain,
458 struct irq_fwspec *fwspec,
459 unsigned long *hwirq,
460 unsigned int *type)
461{
462 if (is_of_node(fwnode: fwspec->fwnode) && fwspec->param_count == 2) {
463 *hwirq = fwspec->param[0];
464 *type = fwspec->param[1];
465 return 0;
466 }
467
468 return -EINVAL;
469}
470
471static int meson_gpio_irq_allocate_gic_irq(struct irq_domain *domain,
472 unsigned int virq,
473 u32 hwirq,
474 unsigned int type)
475{
476 struct irq_fwspec fwspec;
477
478 fwspec.fwnode = domain->parent->fwnode;
479 fwspec.param_count = 3;
480 fwspec.param[0] = 0; /* SPI */
481 fwspec.param[1] = hwirq;
482 fwspec.param[2] = meson_gpio_irq_type_output(type);
483
484 return irq_domain_alloc_irqs_parent(domain, irq_base: virq, nr_irqs: 1, arg: &fwspec);
485}
486
487static int meson_gpio_irq_domain_alloc(struct irq_domain *domain,
488 unsigned int virq,
489 unsigned int nr_irqs,
490 void *data)
491{
492 struct irq_fwspec *fwspec = data;
493 struct meson_gpio_irq_controller *ctl = domain->host_data;
494 unsigned long hwirq;
495 u32 *channel_hwirq;
496 unsigned int type;
497 int ret;
498
499 if (WARN_ON(nr_irqs != 1))
500 return -EINVAL;
501
502 ret = meson_gpio_irq_domain_translate(domain, fwspec, hwirq: &hwirq, type: &type);
503 if (ret)
504 return ret;
505
506 ret = meson_gpio_irq_request_channel(ctl, hwirq, channel_hwirq: &channel_hwirq);
507 if (ret)
508 return ret;
509
510 ret = meson_gpio_irq_allocate_gic_irq(domain, virq,
511 hwirq: *channel_hwirq, type);
512 if (ret < 0) {
513 pr_err("failed to allocate gic irq %u\n", *channel_hwirq);
514 meson_gpio_irq_release_channel(ctl, channel_hwirq);
515 return ret;
516 }
517
518 irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
519 chip: &meson_gpio_irq_chip, chip_data: channel_hwirq);
520
521 return 0;
522}
523
524static void meson_gpio_irq_domain_free(struct irq_domain *domain,
525 unsigned int virq,
526 unsigned int nr_irqs)
527{
528 struct meson_gpio_irq_controller *ctl = domain->host_data;
529 struct irq_data *irq_data;
530 u32 *channel_hwirq;
531
532 if (WARN_ON(nr_irqs != 1))
533 return;
534
535 irq_domain_free_irqs_parent(domain, irq_base: virq, nr_irqs: 1);
536
537 irq_data = irq_domain_get_irq_data(domain, virq);
538 channel_hwirq = irq_data_get_irq_chip_data(d: irq_data);
539
540 meson_gpio_irq_release_channel(ctl, channel_hwirq);
541}
542
543static const struct irq_domain_ops meson_gpio_irq_domain_ops = {
544 .alloc = meson_gpio_irq_domain_alloc,
545 .free = meson_gpio_irq_domain_free,
546 .translate = meson_gpio_irq_domain_translate,
547};
548
549static int meson_gpio_irq_parse_dt(struct device_node *node, struct meson_gpio_irq_controller *ctl)
550{
551 const struct of_device_id *match;
552 int ret;
553
554 match = of_match_node(matches: meson_irq_gpio_matches, node);
555 if (!match)
556 return -ENODEV;
557
558 ctl->params = match->data;
559
560 ret = of_property_read_variable_u32_array(np: node,
561 propname: "amlogic,channel-interrupts",
562 out_values: ctl->channel_irqs,
563 sz_min: ctl->params->nr_channels,
564 sz_max: ctl->params->nr_channels);
565 if (ret < 0) {
566 pr_err("can't get %d channel interrupts\n", ctl->params->nr_channels);
567 return ret;
568 }
569
570 ctl->params->ops.gpio_irq_init(ctl);
571
572 return 0;
573}
574
575static int meson_gpio_irq_of_init(struct device_node *node, struct device_node *parent)
576{
577 struct irq_domain *domain, *parent_domain;
578 struct meson_gpio_irq_controller *ctl;
579 int ret;
580
581 if (!parent) {
582 pr_err("missing parent interrupt node\n");
583 return -ENODEV;
584 }
585
586 parent_domain = irq_find_host(node: parent);
587 if (!parent_domain) {
588 pr_err("unable to obtain parent domain\n");
589 return -ENXIO;
590 }
591
592 ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
593 if (!ctl)
594 return -ENOMEM;
595
596 raw_spin_lock_init(&ctl->lock);
597
598 ctl->base = of_iomap(node, index: 0);
599 if (!ctl->base) {
600 ret = -ENOMEM;
601 goto free_ctl;
602 }
603
604 ret = meson_gpio_irq_parse_dt(node, ctl);
605 if (ret)
606 goto free_channel_irqs;
607
608 domain = irq_domain_create_hierarchy(parent: parent_domain, flags: 0,
609 size: ctl->params->nr_hwirq,
610 of_fwnode_handle(node),
611 ops: &meson_gpio_irq_domain_ops,
612 host_data: ctl);
613 if (!domain) {
614 pr_err("failed to add domain\n");
615 ret = -ENODEV;
616 goto free_channel_irqs;
617 }
618
619 pr_info("%d to %d gpio interrupt mux initialized\n",
620 ctl->params->nr_hwirq, ctl->params->nr_channels);
621
622 return 0;
623
624free_channel_irqs:
625 iounmap(addr: ctl->base);
626free_ctl:
627 kfree(objp: ctl);
628
629 return ret;
630}
631
632IRQCHIP_PLATFORM_DRIVER_BEGIN(meson_gpio_intc)
633IRQCHIP_MATCH("amlogic,meson-gpio-intc", meson_gpio_irq_of_init)
634IRQCHIP_PLATFORM_DRIVER_END(meson_gpio_intc)
635
636MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
637MODULE_DESCRIPTION("Meson GPIO Interrupt Multiplexer driver");
638MODULE_LICENSE("GPL v2");
639MODULE_ALIAS("platform:meson-gpio-intc");
640

source code of linux/drivers/irqchip/irq-meson-gpio.c