1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public |
3 | * License. See the file "COPYING" in the main directory of this archive |
4 | * for more details. |
5 | * |
6 | * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org) |
7 | * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. |
8 | */ |
9 | |
10 | #define pr_fmt(fmt) "irq-mips-gic: " fmt |
11 | |
12 | #include <linux/bitfield.h> |
13 | #include <linux/bitmap.h> |
14 | #include <linux/clocksource.h> |
15 | #include <linux/cpuhotplug.h> |
16 | #include <linux/init.h> |
17 | #include <linux/interrupt.h> |
18 | #include <linux/irq.h> |
19 | #include <linux/irqchip.h> |
20 | #include <linux/irqdomain.h> |
21 | #include <linux/of_address.h> |
22 | #include <linux/percpu.h> |
23 | #include <linux/sched.h> |
24 | #include <linux/smp.h> |
25 | |
26 | #include <asm/mips-cps.h> |
27 | #include <asm/setup.h> |
28 | #include <asm/traps.h> |
29 | |
30 | #include <dt-bindings/interrupt-controller/mips-gic.h> |
31 | |
32 | #define GIC_MAX_INTRS 256 |
33 | #define GIC_MAX_LONGS BITS_TO_LONGS(GIC_MAX_INTRS) |
34 | |
35 | /* Add 2 to convert GIC CPU pin to core interrupt */ |
36 | #define GIC_CPU_PIN_OFFSET 2 |
37 | |
38 | /* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */ |
39 | #define GIC_PIN_TO_VEC_OFFSET 1 |
40 | |
41 | /* Convert between local/shared IRQ number and GIC HW IRQ number. */ |
42 | #define GIC_LOCAL_HWIRQ_BASE 0 |
43 | #define GIC_LOCAL_TO_HWIRQ(x) (GIC_LOCAL_HWIRQ_BASE + (x)) |
44 | #define GIC_HWIRQ_TO_LOCAL(x) ((x) - GIC_LOCAL_HWIRQ_BASE) |
45 | #define GIC_SHARED_HWIRQ_BASE GIC_NUM_LOCAL_INTRS |
46 | #define GIC_SHARED_TO_HWIRQ(x) (GIC_SHARED_HWIRQ_BASE + (x)) |
47 | #define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE) |
48 | |
49 | void __iomem *mips_gic_base; |
50 | |
51 | static DEFINE_PER_CPU_READ_MOSTLY(unsigned long[GIC_MAX_LONGS], pcpu_masks); |
52 | |
53 | static DEFINE_RAW_SPINLOCK(gic_lock); |
54 | static struct irq_domain *gic_irq_domain; |
55 | static int gic_shared_intrs; |
56 | static unsigned int gic_cpu_pin; |
57 | static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller; |
58 | |
59 | #ifdef CONFIG_GENERIC_IRQ_IPI |
60 | static DECLARE_BITMAP(ipi_resrv, GIC_MAX_INTRS); |
61 | static DECLARE_BITMAP(ipi_available, GIC_MAX_INTRS); |
62 | #endif /* CONFIG_GENERIC_IRQ_IPI */ |
63 | |
64 | static struct gic_all_vpes_chip_data { |
65 | u32 map; |
66 | bool mask; |
67 | } gic_all_vpes_chip_data[GIC_NUM_LOCAL_INTRS]; |
68 | |
69 | static void gic_clear_pcpu_masks(unsigned int intr) |
70 | { |
71 | unsigned int i; |
72 | |
73 | /* Clear the interrupt's bit in all pcpu_masks */ |
74 | for_each_possible_cpu(i) |
75 | clear_bit(nr: intr, per_cpu_ptr(pcpu_masks, i)); |
76 | } |
77 | |
78 | static bool gic_local_irq_is_routable(int intr) |
79 | { |
80 | u32 vpe_ctl; |
81 | |
82 | /* All local interrupts are routable in EIC mode. */ |
83 | if (cpu_has_veic) |
84 | return true; |
85 | |
86 | vpe_ctl = read_gic_vl_ctl(); |
87 | switch (intr) { |
88 | case GIC_LOCAL_INT_TIMER: |
89 | return vpe_ctl & GIC_VX_CTL_TIMER_ROUTABLE; |
90 | case GIC_LOCAL_INT_PERFCTR: |
91 | return vpe_ctl & GIC_VX_CTL_PERFCNT_ROUTABLE; |
92 | case GIC_LOCAL_INT_FDC: |
93 | return vpe_ctl & GIC_VX_CTL_FDC_ROUTABLE; |
94 | case GIC_LOCAL_INT_SWINT0: |
95 | case GIC_LOCAL_INT_SWINT1: |
96 | return vpe_ctl & GIC_VX_CTL_SWINT_ROUTABLE; |
97 | default: |
98 | return true; |
99 | } |
100 | } |
101 | |
102 | static void gic_bind_eic_interrupt(int irq, int set) |
103 | { |
104 | /* Convert irq vector # to hw int # */ |
105 | irq -= GIC_PIN_TO_VEC_OFFSET; |
106 | |
107 | /* Set irq to use shadow set */ |
108 | write_gic_vl_eic_shadow_set(irq, set); |
109 | } |
110 | |
111 | static void gic_send_ipi(struct irq_data *d, unsigned int cpu) |
112 | { |
113 | irq_hw_number_t hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(d)); |
114 | |
115 | write_gic_wedge(GIC_WEDGE_RW | hwirq); |
116 | } |
117 | |
118 | int gic_get_c0_compare_int(void) |
119 | { |
120 | if (!gic_local_irq_is_routable(intr: GIC_LOCAL_INT_TIMER)) |
121 | return MIPS_CPU_IRQ_BASE + cp0_compare_irq; |
122 | return irq_create_mapping(gic_irq_domain, |
123 | GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_TIMER)); |
124 | } |
125 | |
126 | int gic_get_c0_perfcount_int(void) |
127 | { |
128 | if (!gic_local_irq_is_routable(intr: GIC_LOCAL_INT_PERFCTR)) { |
129 | /* Is the performance counter shared with the timer? */ |
130 | if (cp0_perfcount_irq < 0) |
131 | return -1; |
132 | return MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; |
133 | } |
134 | return irq_create_mapping(gic_irq_domain, |
135 | GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_PERFCTR)); |
136 | } |
137 | |
138 | int gic_get_c0_fdc_int(void) |
139 | { |
140 | if (!gic_local_irq_is_routable(intr: GIC_LOCAL_INT_FDC)) { |
141 | /* Is the FDC IRQ even present? */ |
142 | if (cp0_fdc_irq < 0) |
143 | return -1; |
144 | return MIPS_CPU_IRQ_BASE + cp0_fdc_irq; |
145 | } |
146 | |
147 | return irq_create_mapping(gic_irq_domain, |
148 | GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_FDC)); |
149 | } |
150 | |
151 | static void gic_handle_shared_int(bool chained) |
152 | { |
153 | unsigned int intr; |
154 | unsigned long *pcpu_mask; |
155 | DECLARE_BITMAP(pending, GIC_MAX_INTRS); |
156 | |
157 | /* Get per-cpu bitmaps */ |
158 | pcpu_mask = this_cpu_ptr(pcpu_masks); |
159 | |
160 | if (mips_cm_is64) |
161 | __ioread64_copy(pending, addr_gic_pend(), |
162 | DIV_ROUND_UP(gic_shared_intrs, 64)); |
163 | else |
164 | __ioread32_copy(to: pending, from: addr_gic_pend(), |
165 | DIV_ROUND_UP(gic_shared_intrs, 32)); |
166 | |
167 | bitmap_and(dst: pending, src1: pending, src2: pcpu_mask, nbits: gic_shared_intrs); |
168 | |
169 | for_each_set_bit(intr, pending, gic_shared_intrs) { |
170 | if (chained) |
171 | generic_handle_domain_irq(gic_irq_domain, |
172 | GIC_SHARED_TO_HWIRQ(intr)); |
173 | else |
174 | do_domain_IRQ(gic_irq_domain, |
175 | GIC_SHARED_TO_HWIRQ(intr)); |
176 | } |
177 | } |
178 | |
179 | static void gic_mask_irq(struct irq_data *d) |
180 | { |
181 | unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq); |
182 | |
183 | write_gic_rmask(intr); |
184 | gic_clear_pcpu_masks(intr); |
185 | } |
186 | |
187 | static void gic_unmask_irq(struct irq_data *d) |
188 | { |
189 | unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq); |
190 | unsigned int cpu; |
191 | |
192 | write_gic_smask(intr); |
193 | |
194 | gic_clear_pcpu_masks(intr); |
195 | cpu = cpumask_first(srcp: irq_data_get_effective_affinity_mask(d)); |
196 | set_bit(nr: intr, per_cpu_ptr(pcpu_masks, cpu)); |
197 | } |
198 | |
199 | static void gic_ack_irq(struct irq_data *d) |
200 | { |
201 | unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); |
202 | |
203 | write_gic_wedge(irq); |
204 | } |
205 | |
206 | static int gic_set_type(struct irq_data *d, unsigned int type) |
207 | { |
208 | unsigned int irq, pol, trig, dual; |
209 | unsigned long flags; |
210 | |
211 | irq = GIC_HWIRQ_TO_SHARED(d->hwirq); |
212 | |
213 | raw_spin_lock_irqsave(&gic_lock, flags); |
214 | switch (type & IRQ_TYPE_SENSE_MASK) { |
215 | case IRQ_TYPE_EDGE_FALLING: |
216 | pol = GIC_POL_FALLING_EDGE; |
217 | trig = GIC_TRIG_EDGE; |
218 | dual = GIC_DUAL_SINGLE; |
219 | break; |
220 | case IRQ_TYPE_EDGE_RISING: |
221 | pol = GIC_POL_RISING_EDGE; |
222 | trig = GIC_TRIG_EDGE; |
223 | dual = GIC_DUAL_SINGLE; |
224 | break; |
225 | case IRQ_TYPE_EDGE_BOTH: |
226 | pol = 0; /* Doesn't matter */ |
227 | trig = GIC_TRIG_EDGE; |
228 | dual = GIC_DUAL_DUAL; |
229 | break; |
230 | case IRQ_TYPE_LEVEL_LOW: |
231 | pol = GIC_POL_ACTIVE_LOW; |
232 | trig = GIC_TRIG_LEVEL; |
233 | dual = GIC_DUAL_SINGLE; |
234 | break; |
235 | case IRQ_TYPE_LEVEL_HIGH: |
236 | default: |
237 | pol = GIC_POL_ACTIVE_HIGH; |
238 | trig = GIC_TRIG_LEVEL; |
239 | dual = GIC_DUAL_SINGLE; |
240 | break; |
241 | } |
242 | |
243 | change_gic_pol(irq, pol); |
244 | change_gic_trig(irq, trig); |
245 | change_gic_dual(irq, dual); |
246 | |
247 | if (trig == GIC_TRIG_EDGE) |
248 | irq_set_chip_handler_name_locked(data: d, chip: &gic_edge_irq_controller, |
249 | handler: handle_edge_irq, NULL); |
250 | else |
251 | irq_set_chip_handler_name_locked(data: d, chip: &gic_level_irq_controller, |
252 | handler: handle_level_irq, NULL); |
253 | raw_spin_unlock_irqrestore(&gic_lock, flags); |
254 | |
255 | return 0; |
256 | } |
257 | |
258 | #ifdef CONFIG_SMP |
259 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, |
260 | bool force) |
261 | { |
262 | unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); |
263 | unsigned long flags; |
264 | unsigned int cpu; |
265 | |
266 | cpu = cpumask_first_and(srcp1: cpumask, cpu_online_mask); |
267 | if (cpu >= NR_CPUS) |
268 | return -EINVAL; |
269 | |
270 | /* Assumption : cpumask refers to a single CPU */ |
271 | raw_spin_lock_irqsave(&gic_lock, flags); |
272 | |
273 | /* Re-route this IRQ */ |
274 | write_gic_map_vp(irq, BIT(mips_cm_vp_id(cpu))); |
275 | |
276 | /* Update the pcpu_masks */ |
277 | gic_clear_pcpu_masks(intr: irq); |
278 | if (read_gic_mask(irq)) |
279 | set_bit(nr: irq, per_cpu_ptr(pcpu_masks, cpu)); |
280 | |
281 | irq_data_update_effective_affinity(d, cpumask_of(cpu)); |
282 | raw_spin_unlock_irqrestore(&gic_lock, flags); |
283 | |
284 | return IRQ_SET_MASK_OK; |
285 | } |
286 | #endif |
287 | |
288 | static struct irq_chip gic_level_irq_controller = { |
289 | .name = "MIPS GIC" , |
290 | .irq_mask = gic_mask_irq, |
291 | .irq_unmask = gic_unmask_irq, |
292 | .irq_set_type = gic_set_type, |
293 | #ifdef CONFIG_SMP |
294 | .irq_set_affinity = gic_set_affinity, |
295 | #endif |
296 | }; |
297 | |
298 | static struct irq_chip gic_edge_irq_controller = { |
299 | .name = "MIPS GIC" , |
300 | .irq_ack = gic_ack_irq, |
301 | .irq_mask = gic_mask_irq, |
302 | .irq_unmask = gic_unmask_irq, |
303 | .irq_set_type = gic_set_type, |
304 | #ifdef CONFIG_SMP |
305 | .irq_set_affinity = gic_set_affinity, |
306 | #endif |
307 | .ipi_send_single = gic_send_ipi, |
308 | }; |
309 | |
310 | static void gic_handle_local_int(bool chained) |
311 | { |
312 | unsigned long pending, masked; |
313 | unsigned int intr; |
314 | |
315 | pending = read_gic_vl_pend(); |
316 | masked = read_gic_vl_mask(); |
317 | |
318 | bitmap_and(&pending, &pending, &masked, GIC_NUM_LOCAL_INTRS); |
319 | |
320 | for_each_set_bit(intr, &pending, GIC_NUM_LOCAL_INTRS) { |
321 | if (chained) |
322 | generic_handle_domain_irq(gic_irq_domain, |
323 | GIC_LOCAL_TO_HWIRQ(intr)); |
324 | else |
325 | do_domain_IRQ(gic_irq_domain, |
326 | GIC_LOCAL_TO_HWIRQ(intr)); |
327 | } |
328 | } |
329 | |
330 | static void gic_mask_local_irq(struct irq_data *d) |
331 | { |
332 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); |
333 | |
334 | write_gic_vl_rmask(BIT(intr)); |
335 | } |
336 | |
337 | static void gic_unmask_local_irq(struct irq_data *d) |
338 | { |
339 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); |
340 | |
341 | write_gic_vl_smask(BIT(intr)); |
342 | } |
343 | |
344 | static struct irq_chip gic_local_irq_controller = { |
345 | .name = "MIPS GIC Local" , |
346 | .irq_mask = gic_mask_local_irq, |
347 | .irq_unmask = gic_unmask_local_irq, |
348 | }; |
349 | |
350 | static void gic_mask_local_irq_all_vpes(struct irq_data *d) |
351 | { |
352 | struct gic_all_vpes_chip_data *cd; |
353 | unsigned long flags; |
354 | int intr, cpu; |
355 | |
356 | intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); |
357 | cd = irq_data_get_irq_chip_data(d); |
358 | cd->mask = false; |
359 | |
360 | raw_spin_lock_irqsave(&gic_lock, flags); |
361 | for_each_online_cpu(cpu) { |
362 | write_gic_vl_other(mips_cm_vp_id(cpu)); |
363 | write_gic_vo_rmask(BIT(intr)); |
364 | } |
365 | raw_spin_unlock_irqrestore(&gic_lock, flags); |
366 | } |
367 | |
368 | static void gic_unmask_local_irq_all_vpes(struct irq_data *d) |
369 | { |
370 | struct gic_all_vpes_chip_data *cd; |
371 | unsigned long flags; |
372 | int intr, cpu; |
373 | |
374 | intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); |
375 | cd = irq_data_get_irq_chip_data(d); |
376 | cd->mask = true; |
377 | |
378 | raw_spin_lock_irqsave(&gic_lock, flags); |
379 | for_each_online_cpu(cpu) { |
380 | write_gic_vl_other(mips_cm_vp_id(cpu)); |
381 | write_gic_vo_smask(BIT(intr)); |
382 | } |
383 | raw_spin_unlock_irqrestore(&gic_lock, flags); |
384 | } |
385 | |
386 | static void gic_all_vpes_irq_cpu_online(void) |
387 | { |
388 | static const unsigned int local_intrs[] = { |
389 | GIC_LOCAL_INT_TIMER, |
390 | GIC_LOCAL_INT_PERFCTR, |
391 | GIC_LOCAL_INT_FDC, |
392 | }; |
393 | unsigned long flags; |
394 | int i; |
395 | |
396 | raw_spin_lock_irqsave(&gic_lock, flags); |
397 | |
398 | for (i = 0; i < ARRAY_SIZE(local_intrs); i++) { |
399 | unsigned int intr = local_intrs[i]; |
400 | struct gic_all_vpes_chip_data *cd; |
401 | |
402 | if (!gic_local_irq_is_routable(intr)) |
403 | continue; |
404 | cd = &gic_all_vpes_chip_data[intr]; |
405 | write_gic_vl_map(mips_gic_vx_map_reg(intr), cd->map); |
406 | if (cd->mask) |
407 | write_gic_vl_smask(BIT(intr)); |
408 | } |
409 | |
410 | raw_spin_unlock_irqrestore(&gic_lock, flags); |
411 | } |
412 | |
413 | static struct irq_chip gic_all_vpes_local_irq_controller = { |
414 | .name = "MIPS GIC Local" , |
415 | .irq_mask = gic_mask_local_irq_all_vpes, |
416 | .irq_unmask = gic_unmask_local_irq_all_vpes, |
417 | }; |
418 | |
419 | static void __gic_irq_dispatch(void) |
420 | { |
421 | gic_handle_local_int(chained: false); |
422 | gic_handle_shared_int(chained: false); |
423 | } |
424 | |
425 | static void gic_irq_dispatch(struct irq_desc *desc) |
426 | { |
427 | gic_handle_local_int(chained: true); |
428 | gic_handle_shared_int(chained: true); |
429 | } |
430 | |
431 | static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq, |
432 | irq_hw_number_t hw, unsigned int cpu) |
433 | { |
434 | int intr = GIC_HWIRQ_TO_SHARED(hw); |
435 | struct irq_data *data; |
436 | unsigned long flags; |
437 | |
438 | data = irq_get_irq_data(irq: virq); |
439 | |
440 | raw_spin_lock_irqsave(&gic_lock, flags); |
441 | write_gic_map_pin(intr, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin); |
442 | write_gic_map_vp(intr, BIT(mips_cm_vp_id(cpu))); |
443 | irq_data_update_effective_affinity(d: data, cpumask_of(cpu)); |
444 | raw_spin_unlock_irqrestore(&gic_lock, flags); |
445 | |
446 | return 0; |
447 | } |
448 | |
449 | static int gic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr, |
450 | const u32 *intspec, unsigned int intsize, |
451 | irq_hw_number_t *out_hwirq, |
452 | unsigned int *out_type) |
453 | { |
454 | if (intsize != 3) |
455 | return -EINVAL; |
456 | |
457 | if (intspec[0] == GIC_SHARED) |
458 | *out_hwirq = GIC_SHARED_TO_HWIRQ(intspec[1]); |
459 | else if (intspec[0] == GIC_LOCAL) |
460 | *out_hwirq = GIC_LOCAL_TO_HWIRQ(intspec[1]); |
461 | else |
462 | return -EINVAL; |
463 | *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; |
464 | |
465 | return 0; |
466 | } |
467 | |
468 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq, |
469 | irq_hw_number_t hwirq) |
470 | { |
471 | struct gic_all_vpes_chip_data *cd; |
472 | unsigned long flags; |
473 | unsigned int intr; |
474 | int err, cpu; |
475 | u32 map; |
476 | |
477 | if (hwirq >= GIC_SHARED_HWIRQ_BASE) { |
478 | #ifdef CONFIG_GENERIC_IRQ_IPI |
479 | /* verify that shared irqs don't conflict with an IPI irq */ |
480 | if (test_bit(GIC_HWIRQ_TO_SHARED(hwirq), ipi_resrv)) |
481 | return -EBUSY; |
482 | #endif /* CONFIG_GENERIC_IRQ_IPI */ |
483 | |
484 | err = irq_domain_set_hwirq_and_chip(domain: d, virq, hwirq, |
485 | chip: &gic_level_irq_controller, |
486 | NULL); |
487 | if (err) |
488 | return err; |
489 | |
490 | irqd_set_single_target(d: irq_desc_get_irq_data(desc: irq_to_desc(irq: virq))); |
491 | return gic_shared_irq_domain_map(d, virq, hw: hwirq, cpu: 0); |
492 | } |
493 | |
494 | intr = GIC_HWIRQ_TO_LOCAL(hwirq); |
495 | map = GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin; |
496 | |
497 | /* |
498 | * If adding support for more per-cpu interrupts, keep the |
499 | * array in gic_all_vpes_irq_cpu_online() in sync. |
500 | */ |
501 | switch (intr) { |
502 | case GIC_LOCAL_INT_TIMER: |
503 | case GIC_LOCAL_INT_PERFCTR: |
504 | case GIC_LOCAL_INT_FDC: |
505 | /* |
506 | * HACK: These are all really percpu interrupts, but |
507 | * the rest of the MIPS kernel code does not use the |
508 | * percpu IRQ API for them. |
509 | */ |
510 | cd = &gic_all_vpes_chip_data[intr]; |
511 | cd->map = map; |
512 | err = irq_domain_set_hwirq_and_chip(domain: d, virq, hwirq, |
513 | chip: &gic_all_vpes_local_irq_controller, |
514 | chip_data: cd); |
515 | if (err) |
516 | return err; |
517 | |
518 | irq_set_handler(irq: virq, handle: handle_percpu_irq); |
519 | break; |
520 | |
521 | default: |
522 | err = irq_domain_set_hwirq_and_chip(domain: d, virq, hwirq, |
523 | chip: &gic_local_irq_controller, |
524 | NULL); |
525 | if (err) |
526 | return err; |
527 | |
528 | irq_set_handler(irq: virq, handle: handle_percpu_devid_irq); |
529 | irq_set_percpu_devid(irq: virq); |
530 | break; |
531 | } |
532 | |
533 | if (!gic_local_irq_is_routable(intr)) |
534 | return -EPERM; |
535 | |
536 | raw_spin_lock_irqsave(&gic_lock, flags); |
537 | for_each_online_cpu(cpu) { |
538 | write_gic_vl_other(mips_cm_vp_id(cpu)); |
539 | write_gic_vo_map(mips_gic_vx_map_reg(intr), map); |
540 | } |
541 | raw_spin_unlock_irqrestore(&gic_lock, flags); |
542 | |
543 | return 0; |
544 | } |
545 | |
546 | static int gic_irq_domain_alloc(struct irq_domain *d, unsigned int virq, |
547 | unsigned int nr_irqs, void *arg) |
548 | { |
549 | struct irq_fwspec *fwspec = arg; |
550 | irq_hw_number_t hwirq; |
551 | |
552 | if (fwspec->param[0] == GIC_SHARED) |
553 | hwirq = GIC_SHARED_TO_HWIRQ(fwspec->param[1]); |
554 | else |
555 | hwirq = GIC_LOCAL_TO_HWIRQ(fwspec->param[1]); |
556 | |
557 | return gic_irq_domain_map(d, virq, hwirq); |
558 | } |
559 | |
560 | static void gic_irq_domain_free(struct irq_domain *d, unsigned int virq, |
561 | unsigned int nr_irqs) |
562 | { |
563 | } |
564 | |
565 | static const struct irq_domain_ops gic_irq_domain_ops = { |
566 | .xlate = gic_irq_domain_xlate, |
567 | .alloc = gic_irq_domain_alloc, |
568 | .free = gic_irq_domain_free, |
569 | .map = gic_irq_domain_map, |
570 | }; |
571 | |
572 | #ifdef CONFIG_GENERIC_IRQ_IPI |
573 | |
574 | static int gic_ipi_domain_xlate(struct irq_domain *d, struct device_node *ctrlr, |
575 | const u32 *intspec, unsigned int intsize, |
576 | irq_hw_number_t *out_hwirq, |
577 | unsigned int *out_type) |
578 | { |
579 | /* |
580 | * There's nothing to translate here. hwirq is dynamically allocated and |
581 | * the irq type is always edge triggered. |
582 | * */ |
583 | *out_hwirq = 0; |
584 | *out_type = IRQ_TYPE_EDGE_RISING; |
585 | |
586 | return 0; |
587 | } |
588 | |
589 | static int gic_ipi_domain_alloc(struct irq_domain *d, unsigned int virq, |
590 | unsigned int nr_irqs, void *arg) |
591 | { |
592 | struct cpumask *ipimask = arg; |
593 | irq_hw_number_t hwirq, base_hwirq; |
594 | int cpu, ret, i; |
595 | |
596 | base_hwirq = find_first_bit(ipi_available, gic_shared_intrs); |
597 | if (base_hwirq == gic_shared_intrs) |
598 | return -ENOMEM; |
599 | |
600 | /* check that we have enough space */ |
601 | for (i = base_hwirq; i < nr_irqs; i++) { |
602 | if (!test_bit(i, ipi_available)) |
603 | return -EBUSY; |
604 | } |
605 | bitmap_clear(ipi_available, base_hwirq, nr_irqs); |
606 | |
607 | /* map the hwirq for each cpu consecutively */ |
608 | i = 0; |
609 | for_each_cpu(cpu, ipimask) { |
610 | hwirq = GIC_SHARED_TO_HWIRQ(base_hwirq + i); |
611 | |
612 | ret = irq_domain_set_hwirq_and_chip(d, virq + i, hwirq, |
613 | &gic_edge_irq_controller, |
614 | NULL); |
615 | if (ret) |
616 | goto error; |
617 | |
618 | ret = irq_domain_set_hwirq_and_chip(d->parent, virq + i, hwirq, |
619 | &gic_edge_irq_controller, |
620 | NULL); |
621 | if (ret) |
622 | goto error; |
623 | |
624 | ret = irq_set_irq_type(virq + i, IRQ_TYPE_EDGE_RISING); |
625 | if (ret) |
626 | goto error; |
627 | |
628 | ret = gic_shared_irq_domain_map(d, virq + i, hwirq, cpu); |
629 | if (ret) |
630 | goto error; |
631 | |
632 | i++; |
633 | } |
634 | |
635 | return 0; |
636 | error: |
637 | bitmap_set(ipi_available, base_hwirq, nr_irqs); |
638 | return ret; |
639 | } |
640 | |
641 | static void gic_ipi_domain_free(struct irq_domain *d, unsigned int virq, |
642 | unsigned int nr_irqs) |
643 | { |
644 | irq_hw_number_t base_hwirq; |
645 | struct irq_data *data; |
646 | |
647 | data = irq_get_irq_data(virq); |
648 | if (!data) |
649 | return; |
650 | |
651 | base_hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(data)); |
652 | bitmap_set(ipi_available, base_hwirq, nr_irqs); |
653 | } |
654 | |
655 | static int gic_ipi_domain_match(struct irq_domain *d, struct device_node *node, |
656 | enum irq_domain_bus_token bus_token) |
657 | { |
658 | bool is_ipi; |
659 | |
660 | switch (bus_token) { |
661 | case DOMAIN_BUS_IPI: |
662 | is_ipi = d->bus_token == bus_token; |
663 | return (!node || to_of_node(d->fwnode) == node) && is_ipi; |
664 | break; |
665 | default: |
666 | return 0; |
667 | } |
668 | } |
669 | |
670 | static const struct irq_domain_ops gic_ipi_domain_ops = { |
671 | .xlate = gic_ipi_domain_xlate, |
672 | .alloc = gic_ipi_domain_alloc, |
673 | .free = gic_ipi_domain_free, |
674 | .match = gic_ipi_domain_match, |
675 | }; |
676 | |
677 | static int gic_register_ipi_domain(struct device_node *node) |
678 | { |
679 | struct irq_domain *gic_ipi_domain; |
680 | unsigned int v[2], num_ipis; |
681 | |
682 | gic_ipi_domain = irq_domain_add_hierarchy(gic_irq_domain, |
683 | IRQ_DOMAIN_FLAG_IPI_PER_CPU, |
684 | GIC_NUM_LOCAL_INTRS + gic_shared_intrs, |
685 | node, &gic_ipi_domain_ops, NULL); |
686 | if (!gic_ipi_domain) { |
687 | pr_err("Failed to add IPI domain" ); |
688 | return -ENXIO; |
689 | } |
690 | |
691 | irq_domain_update_bus_token(gic_ipi_domain, DOMAIN_BUS_IPI); |
692 | |
693 | if (node && |
694 | !of_property_read_u32_array(node, "mti,reserved-ipi-vectors" , v, 2)) { |
695 | bitmap_set(ipi_resrv, v[0], v[1]); |
696 | } else { |
697 | /* |
698 | * Reserve 2 interrupts per possible CPU/VP for use as IPIs, |
699 | * meeting the requirements of arch/mips SMP. |
700 | */ |
701 | num_ipis = 2 * num_possible_cpus(); |
702 | bitmap_set(ipi_resrv, gic_shared_intrs - num_ipis, num_ipis); |
703 | } |
704 | |
705 | bitmap_copy(ipi_available, ipi_resrv, GIC_MAX_INTRS); |
706 | |
707 | return 0; |
708 | } |
709 | |
710 | #else /* !CONFIG_GENERIC_IRQ_IPI */ |
711 | |
712 | static inline int gic_register_ipi_domain(struct device_node *node) |
713 | { |
714 | return 0; |
715 | } |
716 | |
717 | #endif /* !CONFIG_GENERIC_IRQ_IPI */ |
718 | |
719 | static int gic_cpu_startup(unsigned int cpu) |
720 | { |
721 | /* Enable or disable EIC */ |
722 | change_gic_vl_ctl(GIC_VX_CTL_EIC, |
723 | cpu_has_veic ? GIC_VX_CTL_EIC : 0); |
724 | |
725 | /* Clear all local IRQ masks (ie. disable all local interrupts) */ |
726 | write_gic_vl_rmask(~0); |
727 | |
728 | /* Enable desired interrupts */ |
729 | gic_all_vpes_irq_cpu_online(); |
730 | |
731 | return 0; |
732 | } |
733 | |
734 | static int __init gic_of_init(struct device_node *node, |
735 | struct device_node *parent) |
736 | { |
737 | unsigned int cpu_vec, i, gicconfig; |
738 | unsigned long reserved; |
739 | phys_addr_t gic_base; |
740 | struct resource res; |
741 | size_t gic_len; |
742 | int ret; |
743 | |
744 | /* Find the first available CPU vector. */ |
745 | i = 0; |
746 | reserved = (C_SW0 | C_SW1) >> __ffs(C_SW0); |
747 | while (!of_property_read_u32_index(np: node, propname: "mti,reserved-cpu-vectors" , |
748 | index: i++, out_value: &cpu_vec)) |
749 | reserved |= BIT(cpu_vec); |
750 | |
751 | cpu_vec = find_first_zero_bit(&reserved, hweight_long(ST0_IM)); |
752 | if (cpu_vec == hweight_long(ST0_IM)) { |
753 | pr_err("No CPU vectors available\n" ); |
754 | return -ENODEV; |
755 | } |
756 | |
757 | if (of_address_to_resource(dev: node, index: 0, r: &res)) { |
758 | /* |
759 | * Probe the CM for the GIC base address if not specified |
760 | * in the device-tree. |
761 | */ |
762 | if (mips_cm_present()) { |
763 | gic_base = read_gcr_gic_base() & |
764 | ~CM_GCR_GIC_BASE_GICEN; |
765 | gic_len = 0x20000; |
766 | pr_warn("Using inherited base address %pa\n" , |
767 | &gic_base); |
768 | } else { |
769 | pr_err("Failed to get memory range\n" ); |
770 | return -ENODEV; |
771 | } |
772 | } else { |
773 | gic_base = res.start; |
774 | gic_len = resource_size(res: &res); |
775 | } |
776 | |
777 | if (mips_cm_present()) { |
778 | write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN); |
779 | /* Ensure GIC region is enabled before trying to access it */ |
780 | __sync(); |
781 | } |
782 | |
783 | mips_gic_base = ioremap(offset: gic_base, size: gic_len); |
784 | if (!mips_gic_base) { |
785 | pr_err("Failed to ioremap gic_base\n" ); |
786 | return -ENOMEM; |
787 | } |
788 | |
789 | gicconfig = read_gic_config(); |
790 | gic_shared_intrs = FIELD_GET(GIC_CONFIG_NUMINTERRUPTS, gicconfig); |
791 | gic_shared_intrs = (gic_shared_intrs + 1) * 8; |
792 | |
793 | if (cpu_has_veic) { |
794 | /* Always use vector 1 in EIC mode */ |
795 | gic_cpu_pin = 0; |
796 | set_vi_handler(gic_cpu_pin + GIC_PIN_TO_VEC_OFFSET, |
797 | __gic_irq_dispatch); |
798 | } else { |
799 | gic_cpu_pin = cpu_vec - GIC_CPU_PIN_OFFSET; |
800 | irq_set_chained_handler(MIPS_CPU_IRQ_BASE + cpu_vec, |
801 | gic_irq_dispatch); |
802 | } |
803 | |
804 | gic_irq_domain = irq_domain_add_simple(node, GIC_NUM_LOCAL_INTRS + |
805 | gic_shared_intrs, 0, |
806 | &gic_irq_domain_ops, NULL); |
807 | if (!gic_irq_domain) { |
808 | pr_err("Failed to add IRQ domain" ); |
809 | return -ENXIO; |
810 | } |
811 | |
812 | ret = gic_register_ipi_domain(node); |
813 | if (ret) |
814 | return ret; |
815 | |
816 | board_bind_eic_interrupt = &gic_bind_eic_interrupt; |
817 | |
818 | /* Setup defaults */ |
819 | for (i = 0; i < gic_shared_intrs; i++) { |
820 | change_gic_pol(i, GIC_POL_ACTIVE_HIGH); |
821 | change_gic_trig(i, GIC_TRIG_LEVEL); |
822 | write_gic_rmask(i); |
823 | } |
824 | |
825 | return cpuhp_setup_state(state: CPUHP_AP_IRQ_MIPS_GIC_STARTING, |
826 | name: "irqchip/mips/gic:starting" , |
827 | startup: gic_cpu_startup, NULL); |
828 | } |
829 | IRQCHIP_DECLARE(mips_gic, "mti,gic" , gic_of_init); |
830 | |