1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/bitfield.h>
7#include <linux/interrupt.h>
8#include <linux/irq.h>
9#include <linux/irqdomain.h>
10#include <linux/mailbox_controller.h>
11#include <linux/module.h>
12#include <linux/platform_device.h>
13
14#include <dt-bindings/mailbox/qcom-ipcc.h>
15
16/* IPCC Register offsets */
17#define IPCC_REG_CONFIG 0x08
18#define IPCC_REG_SEND_ID 0x0c
19#define IPCC_REG_RECV_ID 0x10
20#define IPCC_REG_RECV_SIGNAL_ENABLE 0x14
21#define IPCC_REG_RECV_SIGNAL_DISABLE 0x18
22#define IPCC_REG_RECV_SIGNAL_CLEAR 0x1c
23#define IPCC_REG_CLIENT_CLEAR 0x38
24
25#define IPCC_CLEAR_ON_RECV_RD BIT(0)
26#define IPCC_SIGNAL_ID_MASK GENMASK(15, 0)
27#define IPCC_CLIENT_ID_MASK GENMASK(31, 16)
28
29#define IPCC_NO_PENDING_IRQ GENMASK(31, 0)
30
31/**
32 * struct qcom_ipcc_chan_info - Per-mailbox-channel info
33 * @client_id: The client-id to which the interrupt has to be triggered
34 * @signal_id: The signal-id to which the interrupt has to be triggered
35 */
36struct qcom_ipcc_chan_info {
37 u16 client_id;
38 u16 signal_id;
39};
40
41/**
42 * struct qcom_ipcc - Holder for the mailbox driver
43 * @dev: Device associated with this instance
44 * @base: Base address of the IPCC frame associated to APSS
45 * @irq_domain: The irq_domain associated with this instance
46 * @chans: The mailbox channels array
47 * @mchan: The per-mailbox channel info array
48 * @mbox: The mailbox controller
49 * @num_chans: Number of @chans elements
50 * @irq: Summary irq
51 */
52struct qcom_ipcc {
53 struct device *dev;
54 void __iomem *base;
55 struct irq_domain *irq_domain;
56 struct mbox_chan *chans;
57 struct qcom_ipcc_chan_info *mchan;
58 struct mbox_controller mbox;
59 int num_chans;
60 int irq;
61};
62
63static inline struct qcom_ipcc *to_qcom_ipcc(struct mbox_controller *mbox)
64{
65 return container_of(mbox, struct qcom_ipcc, mbox);
66}
67
68static inline u32 qcom_ipcc_get_hwirq(u16 client_id, u16 signal_id)
69{
70 return FIELD_PREP(IPCC_CLIENT_ID_MASK, client_id) |
71 FIELD_PREP(IPCC_SIGNAL_ID_MASK, signal_id);
72}
73
74static irqreturn_t qcom_ipcc_irq_fn(int irq, void *data)
75{
76 struct qcom_ipcc *ipcc = data;
77 u32 hwirq;
78 int virq;
79
80 for (;;) {
81 hwirq = readl(addr: ipcc->base + IPCC_REG_RECV_ID);
82 if (hwirq == IPCC_NO_PENDING_IRQ)
83 break;
84
85 virq = irq_find_mapping(domain: ipcc->irq_domain, hwirq);
86 writel(val: hwirq, addr: ipcc->base + IPCC_REG_RECV_SIGNAL_CLEAR);
87 generic_handle_irq(irq: virq);
88 }
89
90 return IRQ_HANDLED;
91}
92
93static void qcom_ipcc_mask_irq(struct irq_data *irqd)
94{
95 struct qcom_ipcc *ipcc = irq_data_get_irq_chip_data(d: irqd);
96 irq_hw_number_t hwirq = irqd_to_hwirq(d: irqd);
97
98 writel(val: hwirq, addr: ipcc->base + IPCC_REG_RECV_SIGNAL_DISABLE);
99}
100
101static void qcom_ipcc_unmask_irq(struct irq_data *irqd)
102{
103 struct qcom_ipcc *ipcc = irq_data_get_irq_chip_data(d: irqd);
104 irq_hw_number_t hwirq = irqd_to_hwirq(d: irqd);
105
106 writel(val: hwirq, addr: ipcc->base + IPCC_REG_RECV_SIGNAL_ENABLE);
107}
108
109static struct irq_chip qcom_ipcc_irq_chip = {
110 .name = "ipcc",
111 .irq_mask = qcom_ipcc_mask_irq,
112 .irq_unmask = qcom_ipcc_unmask_irq,
113 .flags = IRQCHIP_SKIP_SET_WAKE,
114};
115
116static int qcom_ipcc_domain_map(struct irq_domain *d, unsigned int irq,
117 irq_hw_number_t hw)
118{
119 struct qcom_ipcc *ipcc = d->host_data;
120
121 irq_set_chip_and_handler(irq, chip: &qcom_ipcc_irq_chip, handle: handle_level_irq);
122 irq_set_chip_data(irq, data: ipcc);
123 irq_set_noprobe(irq);
124
125 return 0;
126}
127
128static int qcom_ipcc_domain_xlate(struct irq_domain *d,
129 struct device_node *node, const u32 *intspec,
130 unsigned int intsize,
131 unsigned long *out_hwirq,
132 unsigned int *out_type)
133{
134 if (intsize != 3)
135 return -EINVAL;
136
137 *out_hwirq = qcom_ipcc_get_hwirq(client_id: intspec[0], signal_id: intspec[1]);
138 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
139
140 return 0;
141}
142
143static const struct irq_domain_ops qcom_ipcc_irq_ops = {
144 .map = qcom_ipcc_domain_map,
145 .xlate = qcom_ipcc_domain_xlate,
146};
147
148static int qcom_ipcc_mbox_send_data(struct mbox_chan *chan, void *data)
149{
150 struct qcom_ipcc *ipcc = to_qcom_ipcc(mbox: chan->mbox);
151 struct qcom_ipcc_chan_info *mchan = chan->con_priv;
152 u32 hwirq;
153
154 hwirq = qcom_ipcc_get_hwirq(client_id: mchan->client_id, signal_id: mchan->signal_id);
155 writel(val: hwirq, addr: ipcc->base + IPCC_REG_SEND_ID);
156
157 return 0;
158}
159
160static void qcom_ipcc_mbox_shutdown(struct mbox_chan *chan)
161{
162 chan->con_priv = NULL;
163}
164
165static struct mbox_chan *qcom_ipcc_mbox_xlate(struct mbox_controller *mbox,
166 const struct of_phandle_args *ph)
167{
168 struct qcom_ipcc *ipcc = to_qcom_ipcc(mbox);
169 struct qcom_ipcc_chan_info *mchan;
170 struct mbox_chan *chan;
171 struct device *dev;
172 int chan_id;
173
174 dev = ipcc->dev;
175
176 if (ph->args_count != 2)
177 return ERR_PTR(error: -EINVAL);
178
179 for (chan_id = 0; chan_id < mbox->num_chans; chan_id++) {
180 chan = &ipcc->chans[chan_id];
181 mchan = chan->con_priv;
182
183 if (!mchan)
184 break;
185 else if (mchan->client_id == ph->args[0] &&
186 mchan->signal_id == ph->args[1])
187 return ERR_PTR(error: -EBUSY);
188 }
189
190 if (chan_id >= mbox->num_chans)
191 return ERR_PTR(error: -EBUSY);
192
193 mchan = devm_kzalloc(dev, size: sizeof(*mchan), GFP_KERNEL);
194 if (!mchan)
195 return ERR_PTR(error: -ENOMEM);
196
197 mchan->client_id = ph->args[0];
198 mchan->signal_id = ph->args[1];
199 chan->con_priv = mchan;
200
201 return chan;
202}
203
204static const struct mbox_chan_ops ipcc_mbox_chan_ops = {
205 .send_data = qcom_ipcc_mbox_send_data,
206 .shutdown = qcom_ipcc_mbox_shutdown,
207};
208
209static int qcom_ipcc_setup_mbox(struct qcom_ipcc *ipcc,
210 struct device_node *controller_dn)
211{
212 struct of_phandle_args curr_ph;
213 struct device_node *client_dn;
214 struct mbox_controller *mbox;
215 struct device *dev = ipcc->dev;
216 int i, j, ret;
217
218 /*
219 * Find out the number of clients interested in this mailbox
220 * and create channels accordingly.
221 */
222 ipcc->num_chans = 0;
223 for_each_node_with_property(client_dn, "mboxes") {
224 if (!of_device_is_available(device: client_dn))
225 continue;
226 i = of_count_phandle_with_args(np: client_dn,
227 list_name: "mboxes", cells_name: "#mbox-cells");
228 for (j = 0; j < i; j++) {
229 ret = of_parse_phandle_with_args(np: client_dn, list_name: "mboxes",
230 cells_name: "#mbox-cells", index: j, out_args: &curr_ph);
231 of_node_put(node: curr_ph.np);
232 if (!ret && curr_ph.np == controller_dn)
233 ipcc->num_chans++;
234 }
235 }
236
237 /* If no clients are found, skip registering as a mbox controller */
238 if (!ipcc->num_chans)
239 return 0;
240
241 ipcc->chans = devm_kcalloc(dev, n: ipcc->num_chans,
242 size: sizeof(struct mbox_chan), GFP_KERNEL);
243 if (!ipcc->chans)
244 return -ENOMEM;
245
246 mbox = &ipcc->mbox;
247 mbox->dev = dev;
248 mbox->num_chans = ipcc->num_chans;
249 mbox->chans = ipcc->chans;
250 mbox->ops = &ipcc_mbox_chan_ops;
251 mbox->of_xlate = qcom_ipcc_mbox_xlate;
252 mbox->txdone_irq = false;
253 mbox->txdone_poll = false;
254
255 return devm_mbox_controller_register(dev, mbox);
256}
257
258static int qcom_ipcc_pm_resume(struct device *dev)
259{
260 struct qcom_ipcc *ipcc = dev_get_drvdata(dev);
261 u32 hwirq;
262 int virq;
263
264 hwirq = readl(addr: ipcc->base + IPCC_REG_RECV_ID);
265 if (hwirq == IPCC_NO_PENDING_IRQ)
266 return 0;
267
268 virq = irq_find_mapping(domain: ipcc->irq_domain, hwirq);
269
270 dev_dbg(dev, "virq: %d triggered client-id: %ld; signal-id: %ld\n", virq,
271 FIELD_GET(IPCC_CLIENT_ID_MASK, hwirq), FIELD_GET(IPCC_SIGNAL_ID_MASK, hwirq));
272
273 return 0;
274}
275
276static int qcom_ipcc_probe(struct platform_device *pdev)
277{
278 struct qcom_ipcc *ipcc;
279 u32 config_value;
280 static int id;
281 char *name;
282 int ret;
283
284 ipcc = devm_kzalloc(dev: &pdev->dev, size: sizeof(*ipcc), GFP_KERNEL);
285 if (!ipcc)
286 return -ENOMEM;
287
288 ipcc->dev = &pdev->dev;
289
290 ipcc->base = devm_platform_ioremap_resource(pdev, index: 0);
291 if (IS_ERR(ptr: ipcc->base))
292 return PTR_ERR(ptr: ipcc->base);
293
294 /*
295 * It is possible that boot firmware is using the same IPCC instance
296 * as of the HLOS and it has kept CLEAR_ON_RECV_RD set which basically
297 * means Interrupt pending registers are cleared when RECV_ID is read.
298 * The register automatically updates to the next pending interrupt/client
299 * status based on priority.
300 */
301 config_value = readl(addr: ipcc->base + IPCC_REG_CONFIG);
302 if (config_value & IPCC_CLEAR_ON_RECV_RD) {
303 config_value &= ~(IPCC_CLEAR_ON_RECV_RD);
304 writel(val: config_value, addr: ipcc->base + IPCC_REG_CONFIG);
305 }
306
307 ipcc->irq = platform_get_irq(pdev, 0);
308 if (ipcc->irq < 0)
309 return ipcc->irq;
310
311 name = devm_kasprintf(dev: &pdev->dev, GFP_KERNEL, fmt: "ipcc_%d", id++);
312 if (!name)
313 return -ENOMEM;
314
315 ipcc->irq_domain = irq_domain_create_tree(of_fwnode_handle(pdev->dev.of_node),
316 ops: &qcom_ipcc_irq_ops, host_data: ipcc);
317 if (!ipcc->irq_domain)
318 return -ENOMEM;
319
320 ret = qcom_ipcc_setup_mbox(ipcc, controller_dn: pdev->dev.of_node);
321 if (ret)
322 goto err_mbox;
323
324 ret = devm_request_irq(dev: &pdev->dev, irq: ipcc->irq, handler: qcom_ipcc_irq_fn,
325 IRQF_TRIGGER_HIGH | IRQF_NO_SUSPEND |
326 IRQF_NO_THREAD, devname: name, dev_id: ipcc);
327 if (ret < 0) {
328 dev_err(&pdev->dev, "Failed to register the irq: %d\n", ret);
329 goto err_req_irq;
330 }
331
332 platform_set_drvdata(pdev, data: ipcc);
333
334 return 0;
335
336err_req_irq:
337 if (ipcc->num_chans)
338 mbox_controller_unregister(mbox: &ipcc->mbox);
339err_mbox:
340 irq_domain_remove(domain: ipcc->irq_domain);
341
342 return ret;
343}
344
345static void qcom_ipcc_remove(struct platform_device *pdev)
346{
347 struct qcom_ipcc *ipcc = platform_get_drvdata(pdev);
348
349 disable_irq_wake(irq: ipcc->irq);
350 irq_domain_remove(domain: ipcc->irq_domain);
351}
352
353static const struct of_device_id qcom_ipcc_of_match[] = {
354 { .compatible = "qcom,ipcc"},
355 {}
356};
357MODULE_DEVICE_TABLE(of, qcom_ipcc_of_match);
358
359static const struct dev_pm_ops qcom_ipcc_dev_pm_ops = {
360 NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, qcom_ipcc_pm_resume)
361};
362
363static struct platform_driver qcom_ipcc_driver = {
364 .probe = qcom_ipcc_probe,
365 .remove = qcom_ipcc_remove,
366 .driver = {
367 .name = "qcom-ipcc",
368 .of_match_table = qcom_ipcc_of_match,
369 .suppress_bind_attrs = true,
370 .pm = pm_sleep_ptr(&qcom_ipcc_dev_pm_ops),
371 },
372};
373
374static int __init qcom_ipcc_init(void)
375{
376 return platform_driver_register(&qcom_ipcc_driver);
377}
378arch_initcall(qcom_ipcc_init);
379
380MODULE_AUTHOR("Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>");
381MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
382MODULE_DESCRIPTION("Qualcomm Technologies, Inc. IPCC driver");
383MODULE_LICENSE("GPL v2");
384

source code of linux/drivers/mailbox/qcom-ipcc.c