1	// SPDX-License-Identifier: GPL-2.0-only
2	/*
3	* Samsung LSI S5C73M3 8M pixel camera driver
4	*
5	* Copyright (C) 2012, Samsung Electronics, Co., Ltd.
6	* Sylwester Nawrocki <s.nawrocki@samsung.com>
7	* Andrzej Hajda <a.hajda@samsung.com>
8	*/
9
10	#include <linux/clk.h>
11	#include <linux/delay.h>
12	#include <linux/firmware.h>
13	#include <linux/gpio/consumer.h>
14	#include <linux/i2c.h>
15	#include <linux/init.h>
16	#include <linux/media.h>
17	#include <linux/module.h>
18	#include <linux/of_graph.h>
19	#include <linux/regulator/consumer.h>
20	#include <linux/sizes.h>
21	#include <linux/slab.h>
22	#include <linux/spi/spi.h>
23	#include <linux/videodev2.h>
24	#include <media/media-entity.h>
25	#include <media/v4l2-ctrls.h>
26	#include <media/v4l2-device.h>
27	#include <media/v4l2-subdev.h>
28	#include <media/v4l2-mediabus.h>
29	#include <media/v4l2-fwnode.h>
30
31	#include "s5c73m3.h"
32
33	int s5c73m3_dbg;
34	module_param_named(debug, s5c73m3_dbg, int, 0644);
35
36	static int boot_from_rom = 1;
37	module_param(boot_from_rom, int, 0644);
38
39	static int update_fw;
40	module_param(update_fw, int, 0644);
41
42	#define S5C73M3_EMBEDDED_DATA_MAXLEN SZ_4K
43	#define S5C73M3_MIPI_DATA_LANES 4
44	#define S5C73M3_CLK_NAME "cis_extclk"
45
46	static const char * const s5c73m3_supply_names[S5C73M3_MAX_SUPPLIES] = {
47	"vdd-int", /* Digital Core supply (1.2V), CAM_ISP_CORE_1.2V */
48	"vdda", /* Analog Core supply (1.2V), CAM_SENSOR_CORE_1.2V */
49	"vdd-reg", /* Regulator input supply (2.8V), CAM_SENSOR_A2.8V */
50	"vddio-host", /* Digital Host I/O power supply (1.8V...2.8V),
51	CAM_ISP_SENSOR_1.8V */
52	"vddio-cis", /* Digital CIS I/O power (1.2V...1.8V),
53	CAM_ISP_MIPI_1.2V */
54	"vdd-af", /* Lens, CAM_AF_2.8V */
55	};
56
57	static const struct s5c73m3_frame_size s5c73m3_isp_resolutions[] = {
58	{ 320, 240, COMM_CHG_MODE_YUV_320_240 },
59	{ 352, 288, COMM_CHG_MODE_YUV_352_288 },
60	{ 640, 480, COMM_CHG_MODE_YUV_640_480 },
61	{ 880, 720, COMM_CHG_MODE_YUV_880_720 },
62	{ 960, 720, COMM_CHG_MODE_YUV_960_720 },
63	{ 1008, 672, COMM_CHG_MODE_YUV_1008_672 },
64	{ 1184, 666, COMM_CHG_MODE_YUV_1184_666 },
65	{ 1280, 720, COMM_CHG_MODE_YUV_1280_720 },
66	{ 1536, 864, COMM_CHG_MODE_YUV_1536_864 },
67	{ 1600, 1200, COMM_CHG_MODE_YUV_1600_1200 },
68	{ 1632, 1224, COMM_CHG_MODE_YUV_1632_1224 },
69	{ 1920, 1080, COMM_CHG_MODE_YUV_1920_1080 },
70	{ 1920, 1440, COMM_CHG_MODE_YUV_1920_1440 },
71	{ 2304, 1296, COMM_CHG_MODE_YUV_2304_1296 },
72	{ 3264, 2448, COMM_CHG_MODE_YUV_3264_2448 },
73	};
74
75	static const struct s5c73m3_frame_size s5c73m3_jpeg_resolutions[] = {
76	{ 640, 480, COMM_CHG_MODE_JPEG_640_480 },
77	{ 800, 450, COMM_CHG_MODE_JPEG_800_450 },
78	{ 800, 600, COMM_CHG_MODE_JPEG_800_600 },
79	{ 1024, 768, COMM_CHG_MODE_JPEG_1024_768 },
80	{ 1280, 720, COMM_CHG_MODE_JPEG_1280_720 },
81	{ 1280, 960, COMM_CHG_MODE_JPEG_1280_960 },
82	{ 1600, 900, COMM_CHG_MODE_JPEG_1600_900 },
83	{ 1600, 1200, COMM_CHG_MODE_JPEG_1600_1200 },
84	{ 2048, 1152, COMM_CHG_MODE_JPEG_2048_1152 },
85	{ 2048, 1536, COMM_CHG_MODE_JPEG_2048_1536 },
86	{ 2560, 1440, COMM_CHG_MODE_JPEG_2560_1440 },
87	{ 2560, 1920, COMM_CHG_MODE_JPEG_2560_1920 },
88	{ 3264, 1836, COMM_CHG_MODE_JPEG_3264_1836 },
89	{ 3264, 2176, COMM_CHG_MODE_JPEG_3264_2176 },
90	{ 3264, 2448, COMM_CHG_MODE_JPEG_3264_2448 },
91	};
92
93	static const struct s5c73m3_frame_size * const s5c73m3_resolutions[] = {
94	[RES_ISP] = s5c73m3_isp_resolutions,
95	[RES_JPEG] = s5c73m3_jpeg_resolutions
96	};
97
98	static const int s5c73m3_resolutions_len[] = {
99	[RES_ISP] = ARRAY_SIZE(s5c73m3_isp_resolutions),
100	[RES_JPEG] = ARRAY_SIZE(s5c73m3_jpeg_resolutions)
101	};
102
103	static const struct s5c73m3_interval s5c73m3_intervals[] = {
104	{ COMM_FRAME_RATE_FIXED_7FPS, {142857, 1000000}, {3264, 2448} },
105	{ COMM_FRAME_RATE_FIXED_15FPS, {66667, 1000000}, {3264, 2448} },
106	{ COMM_FRAME_RATE_FIXED_20FPS, {50000, 1000000}, {2304, 1296} },
107	{ COMM_FRAME_RATE_FIXED_30FPS, {33333, 1000000}, {2304, 1296} },
108	};
109
110	#define S5C73M3_DEFAULT_FRAME_INTERVAL 3 /* 30 fps */
111
112	static void s5c73m3_fill_mbus_fmt(struct v4l2_mbus_framefmt *mf,
113	const struct s5c73m3_frame_size *fs,
114	u32 code)
115	{
116	mf->width = fs->width;
117	mf->height = fs->height;
118	mf->code = code;
119	mf->colorspace = V4L2_COLORSPACE_JPEG;
120	mf->field = V4L2_FIELD_NONE;
121	}
122
123	static int s5c73m3_i2c_write(struct i2c_client *client, u16 addr, u16 data)
124	{
125	u8 buf[4] = { addr >> 8, addr & 0xff, data >> 8, data & 0xff };
126
127	int ret = i2c_master_send(client, buf, count: sizeof(buf));
128
129	v4l_dbg(4, s5c73m3_dbg, client, "%s: addr 0x%04x, data 0x%04x\n",
130	__func__, addr, data);
131
132	if (ret == 4)
133	return 0;
134
135	return ret < 0 ? ret : -EREMOTEIO;
136	}
137
138	static int s5c73m3_i2c_read(struct i2c_client *client, u16 addr, u16 *data)
139	{
140	int ret;
141	u8 rbuf[2], wbuf[2] = { addr >> 8, addr & 0xff };
142	struct i2c_msg msg[2] = {
143	{
144	.addr = client->addr,
145	.flags = 0,
146	.len = sizeof(wbuf),
147	.buf = wbuf
148	}, {
149	.addr = client->addr,
150	.flags = I2C_M_RD,
151	.len = sizeof(rbuf),
152	.buf = rbuf
153	}
154	};
155	/*
156	* Issue repeated START after writing 2 address bytes and
157	* just one STOP only after reading the data bytes.
158	*/
159	ret = i2c_transfer(adap: client->adapter, msgs: msg, num: 2);
160	if (ret == 2) {
161	*data = be16_to_cpup(p: (__be16 *)rbuf);
162	v4l2_dbg(4, s5c73m3_dbg, client,
163	"%s: addr: 0x%04x, data: 0x%04x\n",
164	__func__, addr, *data);
165	return 0;
166	}
167
168	v4l2_err(client, "I2C read failed: addr: %04x, (%d)\n", addr, ret);
169
170	return ret >= 0 ? -EREMOTEIO : ret;
171	}
172
173	int s5c73m3_write(struct s5c73m3 *state, u32 addr, u16 data)
174	{
175	struct i2c_client *client = state->i2c_client;
176	int ret;
177
178	if ((addr ^ state->i2c_write_address) & 0xffff0000) {
179	ret = s5c73m3_i2c_write(client, REG_CMDWR_ADDRH, data: addr >> 16);
180	if (ret < 0) {
181	state->i2c_write_address = 0;
182	return ret;
183	}
184	}
185
186	if ((addr ^ state->i2c_write_address) & 0xffff) {
187	ret = s5c73m3_i2c_write(client, REG_CMDWR_ADDRL, data: addr & 0xffff);
188	if (ret < 0) {
189	state->i2c_write_address = 0;
190	return ret;
191	}
192	}
193
194	state->i2c_write_address = addr;
195
196	ret = s5c73m3_i2c_write(client, REG_CMDBUF_ADDR, data);
197	if (ret < 0)
198	return ret;
199
200	state->i2c_write_address += 2;
201
202	return ret;
203	}
204
205	int s5c73m3_read(struct s5c73m3 *state, u32 addr, u16 *data)
206	{
207	struct i2c_client *client = state->i2c_client;
208	int ret;
209
210	if ((addr ^ state->i2c_read_address) & 0xffff0000) {
211	ret = s5c73m3_i2c_write(client, REG_CMDRD_ADDRH, data: addr >> 16);
212	if (ret < 0) {
213	state->i2c_read_address = 0;
214	return ret;
215	}
216	}
217
218	if ((addr ^ state->i2c_read_address) & 0xffff) {
219	ret = s5c73m3_i2c_write(client, REG_CMDRD_ADDRL, data: addr & 0xffff);
220	if (ret < 0) {
221	state->i2c_read_address = 0;
222	return ret;
223	}
224	}
225
226	state->i2c_read_address = addr;
227
228	ret = s5c73m3_i2c_read(client, REG_CMDBUF_ADDR, data);
229	if (ret < 0)
230	return ret;
231
232	state->i2c_read_address += 2;
233
234	return ret;
235	}
236
237	static int s5c73m3_check_status(struct s5c73m3 *state, unsigned int value)
238	{
239	unsigned long start = jiffies;
240	unsigned long end = start + msecs_to_jiffies(m: 2000);
241	int ret;
242	u16 status;
243	int count = 0;
244
245	do {
246	ret = s5c73m3_read(state, REG_STATUS, data: &status);
247	if (ret < 0 || status == value)
248	break;
249	usleep_range(min: 500, max: 1000);
250	++count;
251	} while (time_is_after_jiffies(end));
252
253	if (count > 0)
254	v4l2_dbg(1, s5c73m3_dbg, &state->sensor_sd,
255	"status check took %dms\n",
256	jiffies_to_msecs(jiffies - start));
257
258	if (ret == 0 && status != value) {
259	u16 i2c_status = 0;
260	u16 i2c_seq_status = 0;
261
262	s5c73m3_read(state, REG_I2C_STATUS, data: &i2c_status);
263	s5c73m3_read(state, REG_I2C_SEQ_STATUS, data: &i2c_seq_status);
264
265	v4l2_err(&state->sensor_sd,
266	"wrong status %#x, expected: %#x, i2c_status: %#x/%#x\n",
267	status, value, i2c_status, i2c_seq_status);
268
269	return -ETIMEDOUT;
270	}
271
272	return ret;
273	}
274
275	int s5c73m3_isp_command(struct s5c73m3 *state, u16 command, u16 data)
276	{
277	int ret;
278
279	ret = s5c73m3_check_status(state, REG_STATUS_ISP_COMMAND_COMPLETED);
280	if (ret < 0)
281	return ret;
282
283	ret = s5c73m3_write(state, addr: 0x00095000, data: command);
284	if (ret < 0)
285	return ret;
286
287	ret = s5c73m3_write(state, addr: 0x00095002, data);
288	if (ret < 0)
289	return ret;
290
291	return s5c73m3_write(state, REG_STATUS, data: 0x0001);
292	}
293
294	static int s5c73m3_isp_comm_result(struct s5c73m3 *state, u16 command,
295	u16 *data)
296	{
297	return s5c73m3_read(state, COMM_RESULT_OFFSET + command, data);
298	}
299
300	static int s5c73m3_set_af_softlanding(struct s5c73m3 *state)
301	{
302	unsigned long start = jiffies;
303	u16 af_softlanding;
304	int count = 0;
305	int ret;
306	const char *msg;
307
308	ret = s5c73m3_isp_command(state, COMM_AF_SOFTLANDING,
309	COMM_AF_SOFTLANDING_ON);
310	if (ret < 0) {
311	v4l2_info(&state->sensor_sd, "AF soft-landing failed\n");
312	return ret;
313	}
314
315	for (;;) {
316	ret = s5c73m3_isp_comm_result(state, COMM_AF_SOFTLANDING,
317	data: &af_softlanding);
318	if (ret < 0) {
319	msg = "failed";
320	break;
321	}
322	if (af_softlanding == COMM_AF_SOFTLANDING_RES_COMPLETE) {
323	msg = "succeeded";
324	break;
325	}
326	if (++count > 100) {
327	ret = -ETIME;
328	msg = "timed out";
329	break;
330	}
331	msleep(msecs: 25);
332	}
333
334	v4l2_info(&state->sensor_sd, "AF soft-landing %s after %dms\n",
335	msg, jiffies_to_msecs(jiffies - start));
336
337	return ret;
338	}
339
340	static int s5c73m3_load_fw(struct v4l2_subdev *sd)
341	{
342	struct s5c73m3 *state = sensor_sd_to_s5c73m3(sd);
343	struct i2c_client *client = state->i2c_client;
344	const struct firmware *fw;
345	int ret;
346	char fw_name[20];
347
348	snprintf(buf: fw_name, size: sizeof(fw_name), fmt: "SlimISP_%.2s.bin",
349	state->fw_file_version);
350	ret = request_firmware(fw: &fw, name: fw_name, device: &client->dev);
351	if (ret < 0) {
352	v4l2_err(sd, "Firmware request failed (%s)\n", fw_name);
353	return -EINVAL;
354	}
355
356	v4l2_info(sd, "Loading firmware (%s, %zu B)\n", fw_name, fw->size);
357
358	ret = s5c73m3_spi_write(state, addr: fw->data, len: fw->size, tx_size: 64);
359
360	if (ret >= 0)
361	state->isp_ready = 1;
362	else
363	v4l2_err(sd, "SPI write failed\n");
364
365	release_firmware(fw);
366
367	return ret;
368	}
369
370	static int s5c73m3_set_frame_size(struct s5c73m3 *state)
371	{
372	const struct s5c73m3_frame_size *prev_size =
373	state->sensor_pix_size[RES_ISP];
374	const struct s5c73m3_frame_size *cap_size =
375	state->sensor_pix_size[RES_JPEG];
376	unsigned int chg_mode;
377
378	v4l2_dbg(1, s5c73m3_dbg, &state->sensor_sd,
379	"Preview size: %dx%d, reg_val: 0x%x\n",
380	prev_size->width, prev_size->height, prev_size->reg_val);
381
382	chg_mode = prev_size->reg_val | COMM_CHG_MODE_NEW;
383
384	if (state->mbus_code == S5C73M3_JPEG_FMT) {
385	v4l2_dbg(1, s5c73m3_dbg, &state->sensor_sd,
386	"Capture size: %dx%d, reg_val: 0x%x\n",
387	cap_size->width, cap_size->height, cap_size->reg_val);
388	chg_mode |= cap_size->reg_val;
389	}
390
391	return s5c73m3_isp_command(state, COMM_CHG_MODE, data: chg_mode);
392	}
393
394	static int s5c73m3_set_frame_rate(struct s5c73m3 *state)
395	{
396	int ret;
397
398	if (state->ctrls.stabilization->val)
399	return 0;
400
401	if (WARN_ON(state->fiv == NULL))
402	return -EINVAL;
403
404	ret = s5c73m3_isp_command(state, COMM_FRAME_RATE, data: state->fiv->fps_reg);
405	if (!ret)
406	state->apply_fiv = 0;
407
408	return ret;
409	}
410
411	static int __s5c73m3_s_stream(struct s5c73m3 *state, struct v4l2_subdev *sd,
412	int on)
413	{
414	u16 mode;
415	int ret;
416
417	if (on && state->apply_fmt) {
418	if (state->mbus_code == S5C73M3_JPEG_FMT)
419	mode = COMM_IMG_OUTPUT_INTERLEAVED;
420	else
421	mode = COMM_IMG_OUTPUT_YUV;
422
423	ret = s5c73m3_isp_command(state, COMM_IMG_OUTPUT, data: mode);
424	if (!ret)
425	ret = s5c73m3_set_frame_size(state);
426	if (ret)
427	return ret;
428	state->apply_fmt = 0;
429	}
430
431	ret = s5c73m3_isp_command(state, COMM_SENSOR_STREAMING, data: !!on);
432	if (ret)
433	return ret;
434
435	state->streaming = !!on;
436
437	if (!on)
438	return 0;
439
440	if (state->apply_fiv) {
441	ret = s5c73m3_set_frame_rate(state);
442	if (ret < 0)
443	v4l2_err(sd, "Error setting frame rate(%d)\n", ret);
444	}
445
446	return s5c73m3_check_status(state, REG_STATUS_ISP_COMMAND_COMPLETED);
447	}
448
449	static int s5c73m3_oif_s_stream(struct v4l2_subdev *sd, int on)
450	{
451	struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
452	int ret;
453
454	mutex_lock(&state->lock);
455	ret = __s5c73m3_s_stream(state, sd, on);
456	mutex_unlock(lock: &state->lock);
457
458	return ret;
459	}
460
461	static int s5c73m3_system_status_wait(struct s5c73m3 *state, u32 value,
462	unsigned int delay, unsigned int steps)
463	{
464	u16 reg = 0;
465
466	while (steps-- > 0) {
467	int ret = s5c73m3_read(state, addr: 0x30100010, data: &reg);
468	if (ret < 0)
469	return ret;
470	if (reg == value)
471	return 0;
472	usleep_range(min: delay, max: delay + 25);
473	}
474	return -ETIMEDOUT;
475	}
476
477	static int s5c73m3_read_fw_version(struct s5c73m3 *state)
478	{
479	struct v4l2_subdev *sd = &state->sensor_sd;
480	int i, ret;
481	u16 data[2];
482	int offset;
483
484	offset = state->isp_ready ? 0x60 : 0;
485
486	for (i = 0; i < S5C73M3_SENSOR_FW_LEN / 2; i++) {
487	ret = s5c73m3_read(state, addr: offset + i * 2, data);
488	if (ret < 0)
489	return ret;
490	state->sensor_fw[i * 2] = (char)(*data & 0xff);
491	state->sensor_fw[i * 2 + 1] = (char)(*data >> 8);
492	}
493	state->sensor_fw[S5C73M3_SENSOR_FW_LEN] = '\0';
494
495
496	for (i = 0; i < S5C73M3_SENSOR_TYPE_LEN / 2; i++) {
497	ret = s5c73m3_read(state, addr: offset + 6 + i * 2, data);
498	if (ret < 0)
499	return ret;
500	state->sensor_type[i * 2] = (char)(*data & 0xff);
501	state->sensor_type[i * 2 + 1] = (char)(*data >> 8);
502	}
503	state->sensor_type[S5C73M3_SENSOR_TYPE_LEN] = '\0';
504
505	ret = s5c73m3_read(state, addr: offset + 0x14, data);
506	if (ret >= 0) {
507	ret = s5c73m3_read(state, addr: offset + 0x16, data: data + 1);
508	if (ret >= 0)
509	state->fw_size = data[0] + (data[1] << 16);
510	}
511
512	v4l2_info(sd, "Sensor type: %s, FW version: %s\n",
513	state->sensor_type, state->sensor_fw);
514	return ret;
515	}
516
517	static int s5c73m3_fw_update_from(struct s5c73m3 *state)
518	{
519	struct v4l2_subdev *sd = &state->sensor_sd;
520	u16 status = COMM_FW_UPDATE_NOT_READY;
521	int ret;
522	int count = 0;
523
524	v4l2_warn(sd, "Updating F-ROM firmware.\n");
525	do {
526	if (status == COMM_FW_UPDATE_NOT_READY) {
527	ret = s5c73m3_isp_command(state, COMM_FW_UPDATE, data: 0);
528	if (ret < 0)
529	return ret;
530	}
531
532	ret = s5c73m3_read(state, addr: 0x00095906, data: &status);
533	if (ret < 0)
534	return ret;
535	switch (status) {
536	case COMM_FW_UPDATE_FAIL:
537	v4l2_warn(sd, "Updating F-ROM firmware failed.\n");
538	return -EIO;
539	case COMM_FW_UPDATE_SUCCESS:
540	v4l2_warn(sd, "Updating F-ROM firmware finished.\n");
541	return 0;
542	}
543	++count;
544	msleep(msecs: 20);
545	} while (count < 500);
546
547	v4l2_warn(sd, "Updating F-ROM firmware timed-out.\n");
548	return -ETIMEDOUT;
549	}
550
551	static int s5c73m3_spi_boot(struct s5c73m3 *state, bool load_fw)
552	{
553	struct v4l2_subdev *sd = &state->sensor_sd;
554	int ret;
555
556	/* Run ARM MCU */
557	ret = s5c73m3_write(state, addr: 0x30000004, data: 0xffff);
558	if (ret < 0)
559	return ret;
560
561	usleep_range(min: 400, max: 500);
562
563	/* Check booting status */
564	ret = s5c73m3_system_status_wait(state, value: 0x0c, delay: 100, steps: 3);
565	if (ret < 0) {
566	v4l2_err(sd, "booting failed: %d\n", ret);
567	return ret;
568	}
569
570	/* P,M,S and Boot Mode */
571	ret = s5c73m3_write(state, addr: 0x30100014, data: 0x2146);
572	if (ret < 0)
573	return ret;
574
575	ret = s5c73m3_write(state, addr: 0x30100010, data: 0x210c);
576	if (ret < 0)
577	return ret;
578
579	usleep_range(min: 200, max: 250);
580
581	/* Check SPI status */
582	ret = s5c73m3_system_status_wait(state, value: 0x210d, delay: 100, steps: 300);
583	if (ret < 0)
584	v4l2_err(sd, "SPI not ready: %d\n", ret);
585
586	/* Firmware download over SPI */
587	if (load_fw)
588	s5c73m3_load_fw(sd);
589
590	/* MCU reset */
591	ret = s5c73m3_write(state, addr: 0x30000004, data: 0xfffd);
592	if (ret < 0)
593	return ret;
594
595	/* Remap */
596	ret = s5c73m3_write(state, addr: 0x301000a4, data: 0x0183);
597	if (ret < 0)
598	return ret;
599
600	/* MCU restart */
601	ret = s5c73m3_write(state, addr: 0x30000004, data: 0xffff);
602	if (ret < 0 || !load_fw)
603	return ret;
604
605	ret = s5c73m3_read_fw_version(state);
606	if (ret < 0)
607	return ret;
608
609	if (load_fw && update_fw) {
610	ret = s5c73m3_fw_update_from(state);
611	update_fw = 0;
612	}
613
614	return ret;
615	}
616
617	static int s5c73m3_set_timing_register_for_vdd(struct s5c73m3 *state)
618	{
619	static const u32 regs[][2] = {
620	{ 0x30100018, 0x0618 },
621	{ 0x3010001c, 0x10c1 },
622	{ 0x30100020, 0x249e }
623	};
624	int ret;
625	int i;
626
627	for (i = 0; i < ARRAY_SIZE(regs); i++) {
628	ret = s5c73m3_write(state, addr: regs[i][0], data: regs[i][1]);
629	if (ret < 0)
630	return ret;
631	}
632
633	return 0;
634	}
635
636	static void s5c73m3_set_fw_file_version(struct s5c73m3 *state)
637	{
638	switch (state->sensor_fw[0]) {
639	case 'G':
640	case 'O':
641	state->fw_file_version[0] = 'G';
642	break;
643	case 'S':
644	case 'Z':
645	state->fw_file_version[0] = 'Z';
646	break;
647	}
648
649	switch (state->sensor_fw[1]) {
650	case 'C'...'F':
651	state->fw_file_version[1] = state->sensor_fw[1];
652	break;
653	}
654	}
655
656	static int s5c73m3_get_fw_version(struct s5c73m3 *state)
657	{
658	struct v4l2_subdev *sd = &state->sensor_sd;
659	int ret;
660
661	/* Run ARM MCU */
662	ret = s5c73m3_write(state, addr: 0x30000004, data: 0xffff);
663	if (ret < 0)
664	return ret;
665	usleep_range(min: 400, max: 500);
666
667	/* Check booting status */
668	ret = s5c73m3_system_status_wait(state, value: 0x0c, delay: 100, steps: 3);
669	if (ret < 0) {
670
671	v4l2_err(sd, "%s: booting failed: %d\n", __func__, ret);
672	return ret;
673	}
674
675	/* Change I/O Driver Current in order to read from F-ROM */
676	ret = s5c73m3_write(state, addr: 0x30100120, data: 0x0820);
677	ret = s5c73m3_write(state, addr: 0x30100124, data: 0x0820);
678
679	/* Offset Setting */
680	ret = s5c73m3_write(state, addr: 0x00010418, data: 0x0008);
681
682	/* P,M,S and Boot Mode */
683	ret = s5c73m3_write(state, addr: 0x30100014, data: 0x2146);
684	if (ret < 0)
685	return ret;
686	ret = s5c73m3_write(state, addr: 0x30100010, data: 0x230c);
687	if (ret < 0)
688	return ret;
689
690	usleep_range(min: 200, max: 250);
691
692	/* Check SPI status */
693	ret = s5c73m3_system_status_wait(state, value: 0x230e, delay: 100, steps: 300);
694	if (ret < 0)
695	v4l2_err(sd, "SPI not ready: %d\n", ret);
696
697	/* ARM reset */
698	ret = s5c73m3_write(state, addr: 0x30000004, data: 0xfffd);
699	if (ret < 0)
700	return ret;
701
702	/* Remap */
703	ret = s5c73m3_write(state, addr: 0x301000a4, data: 0x0183);
704	if (ret < 0)
705	return ret;
706
707	s5c73m3_set_timing_register_for_vdd(state);
708
709	ret = s5c73m3_read_fw_version(state);
710
711	s5c73m3_set_fw_file_version(state);
712
713	return ret;
714	}
715
716	static int s5c73m3_rom_boot(struct s5c73m3 *state, bool load_fw)
717	{
718	static const u32 boot_regs[][2] = {
719	{ 0x3100010c, 0x0044 },
720	{ 0x31000108, 0x000d },
721	{ 0x31000304, 0x0001 },
722	{ 0x00010000, 0x5800 },
723	{ 0x00010002, 0x0002 },
724	{ 0x31000000, 0x0001 },
725	{ 0x30100014, 0x1b85 },
726	{ 0x30100010, 0x230c }
727	};
728	struct v4l2_subdev *sd = &state->sensor_sd;
729	int i, ret;
730
731	/* Run ARM MCU */
732	ret = s5c73m3_write(state, addr: 0x30000004, data: 0xffff);
733	if (ret < 0)
734	return ret;
735	usleep_range(min: 400, max: 450);
736
737	/* Check booting status */
738	ret = s5c73m3_system_status_wait(state, value: 0x0c, delay: 100, steps: 4);
739	if (ret < 0) {
740	v4l2_err(sd, "Booting failed: %d\n", ret);
741	return ret;
742	}
743
744	for (i = 0; i < ARRAY_SIZE(boot_regs); i++) {
745	ret = s5c73m3_write(state, addr: boot_regs[i][0], data: boot_regs[i][1]);
746	if (ret < 0)
747	return ret;
748	}
749	msleep(msecs: 200);
750
751	/* Check the binary read status */
752	ret = s5c73m3_system_status_wait(state, value: 0x230e, delay: 1000, steps: 150);
753	if (ret < 0) {
754	v4l2_err(sd, "Binary read failed: %d\n", ret);
755	return ret;
756	}
757
758	/* ARM reset */
759	ret = s5c73m3_write(state, addr: 0x30000004, data: 0xfffd);
760	if (ret < 0)
761	return ret;
762	/* Remap */
763	ret = s5c73m3_write(state, addr: 0x301000a4, data: 0x0183);
764	if (ret < 0)
765	return ret;
766	/* MCU re-start */
767	ret = s5c73m3_write(state, addr: 0x30000004, data: 0xffff);
768	if (ret < 0)
769	return ret;
770
771	state->isp_ready = 1;
772
773	return s5c73m3_read_fw_version(state);
774	}
775
776	static int s5c73m3_isp_init(struct s5c73m3 *state)
777	{
778	int ret;
779
780	state->i2c_read_address = 0;
781	state->i2c_write_address = 0;
782
783	ret = s5c73m3_i2c_write(client: state->i2c_client, AHB_MSB_ADDR_PTR, data: 0x3310);
784	if (ret < 0)
785	return ret;
786
787	if (boot_from_rom)
788	return s5c73m3_rom_boot(state, load_fw: true);
789	else
790	return s5c73m3_spi_boot(state, load_fw: true);
791	}
792
793	static const struct s5c73m3_frame_size *s5c73m3_find_frame_size(
794	struct v4l2_mbus_framefmt *fmt,
795	enum s5c73m3_resolution_types idx)
796	{
797	const struct s5c73m3_frame_size *fs;
798	const struct s5c73m3_frame_size *best_fs;
799	int best_dist = INT_MAX;
800	int i;
801
802	fs = s5c73m3_resolutions[idx];
803	best_fs = NULL;
804	for (i = 0; i < s5c73m3_resolutions_len[idx]; ++i) {
805	int dist = abs(fs->width - fmt->width) +
806	abs(fs->height - fmt->height);
807	if (dist < best_dist) {
808	best_dist = dist;
809	best_fs = fs;
810	}
811	++fs;
812	}
813
814	return best_fs;
815	}
816
817	static void s5c73m3_oif_try_format(struct s5c73m3 *state,
818	struct v4l2_subdev_state *sd_state,
819	struct v4l2_subdev_format *fmt,
820	const struct s5c73m3_frame_size **fs)
821	{
822	u32 code;
823
824	switch (fmt->pad) {
825	case OIF_ISP_PAD:
826	*fs = s5c73m3_find_frame_size(fmt: &fmt->format, idx: RES_ISP);
827	code = S5C73M3_ISP_FMT;
828	break;
829	case OIF_JPEG_PAD:
830	*fs = s5c73m3_find_frame_size(fmt: &fmt->format, idx: RES_JPEG);
831	code = S5C73M3_JPEG_FMT;
832	break;
833	case OIF_SOURCE_PAD:
834	default:
835	if (fmt->format.code == S5C73M3_JPEG_FMT)
836	code = S5C73M3_JPEG_FMT;
837	else
838	code = S5C73M3_ISP_FMT;
839
840	if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE)
841	*fs = state->oif_pix_size[RES_ISP];
842	else
843	*fs = s5c73m3_find_frame_size(v4l2_subdev_state_get_format(sd_state, OIF_ISP_PAD),
844	idx: RES_ISP);
845	break;
846	}
847
848	s5c73m3_fill_mbus_fmt(mf: &fmt->format, fs: *fs, code);
849	}
850
851	static void s5c73m3_try_format(struct s5c73m3 *state,
852	struct v4l2_subdev_state *sd_state,
853	struct v4l2_subdev_format *fmt,
854	const struct s5c73m3_frame_size **fs)
855	{
856	u32 code;
857
858	if (fmt->pad == S5C73M3_ISP_PAD) {
859	*fs = s5c73m3_find_frame_size(fmt: &fmt->format, idx: RES_ISP);
860	code = S5C73M3_ISP_FMT;
861	} else {
862	*fs = s5c73m3_find_frame_size(fmt: &fmt->format, idx: RES_JPEG);
863	code = S5C73M3_JPEG_FMT;
864	}
865
866	s5c73m3_fill_mbus_fmt(mf: &fmt->format, fs: *fs, code);
867	}
868
869	static int s5c73m3_oif_get_frame_interval(struct v4l2_subdev *sd,
870	struct v4l2_subdev_state *sd_state,
871	struct v4l2_subdev_frame_interval *fi)
872	{
873	struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
874
875	/*
876	* FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2
877	* subdev active state API.
878	*/
879	if (fi->which != V4L2_SUBDEV_FORMAT_ACTIVE)
880	return -EINVAL;
881
882	if (fi->pad != OIF_SOURCE_PAD)
883	return -EINVAL;
884
885	mutex_lock(&state->lock);
886	fi->interval = state->fiv->interval;
887	mutex_unlock(lock: &state->lock);
888
889	return 0;
890	}
891
892	static int __s5c73m3_set_frame_interval(struct s5c73m3 *state,
893	struct v4l2_subdev_frame_interval *fi)
894	{
895	const struct s5c73m3_frame_size *prev_size =
896	state->sensor_pix_size[RES_ISP];
897	const struct s5c73m3_interval *fiv = &s5c73m3_intervals[0];
898	unsigned int ret, min_err = UINT_MAX;
899	unsigned int i, fr_time;
900
901	if (fi->interval.denominator == 0)
902	return -EINVAL;
903
904	fr_time = fi->interval.numerator * 1000 / fi->interval.denominator;
905
906	for (i = 0; i < ARRAY_SIZE(s5c73m3_intervals); i++) {
907	const struct s5c73m3_interval *iv = &s5c73m3_intervals[i];
908
909	if (prev_size->width > iv->size.width ||
910	prev_size->height > iv->size.height)
911	continue;
912
913	ret = abs(iv->interval.numerator / 1000 - fr_time);
914	if (ret < min_err) {
915	fiv = iv;
916	min_err = ret;
917	}
918	}
919	state->fiv = fiv;
920
921	v4l2_dbg(1, s5c73m3_dbg, &state->sensor_sd,
922	"Changed frame interval to %u us\n", fiv->interval.numerator);
923	return 0;
924	}
925
926	static int s5c73m3_oif_set_frame_interval(struct v4l2_subdev *sd,
927	struct v4l2_subdev_state *sd_state,
928	struct v4l2_subdev_frame_interval *fi)
929	{
930	struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
931	int ret;
932
933	/*
934	* FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2
935	* subdev active state API.
936	*/
937	if (fi->which != V4L2_SUBDEV_FORMAT_ACTIVE)
938	return -EINVAL;
939
940	if (fi->pad != OIF_SOURCE_PAD)
941	return -EINVAL;
942
943	v4l2_dbg(1, s5c73m3_dbg, sd, "Setting %d/%d frame interval\n",
944	fi->interval.numerator, fi->interval.denominator);
945
946	mutex_lock(&state->lock);
947
948	ret = __s5c73m3_set_frame_interval(state, fi);
949	if (!ret) {
950	if (state->streaming)
951	ret = s5c73m3_set_frame_rate(state);
952	else
953	state->apply_fiv = 1;
954	}
955	mutex_unlock(lock: &state->lock);
956	return ret;
957	}
958
959	static int s5c73m3_oif_enum_frame_interval(struct v4l2_subdev *sd,
960	struct v4l2_subdev_state *sd_state,
961	struct v4l2_subdev_frame_interval_enum *fie)
962	{
963	struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
964	const struct s5c73m3_interval *fi;
965	int ret = 0;
966
967	if (fie->pad != OIF_SOURCE_PAD)
968	return -EINVAL;
969	if (fie->index >= ARRAY_SIZE(s5c73m3_intervals))
970	return -EINVAL;
971
972	mutex_lock(&state->lock);
973	fi = &s5c73m3_intervals[fie->index];
974	if (fie->width > fi->size.width || fie->height > fi->size.height)
975	ret = -EINVAL;
976	else
977	fie->interval = fi->interval;
978	mutex_unlock(lock: &state->lock);
979
980	return ret;
981	}
982
983	static int s5c73m3_oif_get_pad_code(int pad, int index)
984	{
985	if (pad == OIF_SOURCE_PAD) {
986	if (index > 1)
987	return -EINVAL;
988	return (index == 0) ? S5C73M3_ISP_FMT : S5C73M3_JPEG_FMT;
989	}
990
991	if (index > 0)
992	return -EINVAL;
993
994	return (pad == OIF_ISP_PAD) ? S5C73M3_ISP_FMT : S5C73M3_JPEG_FMT;
995	}
996
997	static int s5c73m3_get_fmt(struct v4l2_subdev *sd,
998	struct v4l2_subdev_state *sd_state,
999	struct v4l2_subdev_format *fmt)
1000	{
1001	struct s5c73m3 *state = sensor_sd_to_s5c73m3(sd);
1002	const struct s5c73m3_frame_size *fs;
1003	u32 code;
1004
1005	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1006	fmt->format = *v4l2_subdev_state_get_format(sd_state,
1007	fmt->pad);
1008	return 0;
1009	}
1010
1011	mutex_lock(&state->lock);
1012
1013	switch (fmt->pad) {
1014	case S5C73M3_ISP_PAD:
1015	code = S5C73M3_ISP_FMT;
1016	fs = state->sensor_pix_size[RES_ISP];
1017	break;
1018	case S5C73M3_JPEG_PAD:
1019	code = S5C73M3_JPEG_FMT;
1020	fs = state->sensor_pix_size[RES_JPEG];
1021	break;
1022	default:
1023	mutex_unlock(lock: &state->lock);
1024	return -EINVAL;
1025	}
1026	s5c73m3_fill_mbus_fmt(mf: &fmt->format, fs, code);
1027
1028	mutex_unlock(lock: &state->lock);
1029	return 0;
1030	}
1031
1032	static int s5c73m3_oif_get_fmt(struct v4l2_subdev *sd,
1033	struct v4l2_subdev_state *sd_state,
1034	struct v4l2_subdev_format *fmt)
1035	{
1036	struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
1037	const struct s5c73m3_frame_size *fs;
1038	u32 code;
1039
1040	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1041	fmt->format = *v4l2_subdev_state_get_format(sd_state,
1042	fmt->pad);
1043	return 0;
1044	}
1045
1046	mutex_lock(&state->lock);
1047
1048	switch (fmt->pad) {
1049	case OIF_ISP_PAD:
1050	code = S5C73M3_ISP_FMT;
1051	fs = state->oif_pix_size[RES_ISP];
1052	break;
1053	case OIF_JPEG_PAD:
1054	code = S5C73M3_JPEG_FMT;
1055	fs = state->oif_pix_size[RES_JPEG];
1056	break;
1057	case OIF_SOURCE_PAD:
1058	code = state->mbus_code;
1059	fs = state->oif_pix_size[RES_ISP];
1060	break;
1061	default:
1062	mutex_unlock(lock: &state->lock);
1063	return -EINVAL;
1064	}
1065	s5c73m3_fill_mbus_fmt(mf: &fmt->format, fs, code);
1066
1067	mutex_unlock(lock: &state->lock);
1068	return 0;
1069	}
1070
1071	static int s5c73m3_set_fmt(struct v4l2_subdev *sd,
1072	struct v4l2_subdev_state *sd_state,
1073	struct v4l2_subdev_format *fmt)
1074	{
1075	const struct s5c73m3_frame_size *frame_size = NULL;
1076	struct s5c73m3 *state = sensor_sd_to_s5c73m3(sd);
1077	struct v4l2_mbus_framefmt *mf;
1078	int ret = 0;
1079
1080	mutex_lock(&state->lock);
1081
1082	s5c73m3_try_format(state, sd_state, fmt, fs: &frame_size);
1083
1084	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1085	mf = v4l2_subdev_state_get_format(sd_state, fmt->pad);
1086	*mf = fmt->format;
1087	} else {
1088	switch (fmt->pad) {
1089	case S5C73M3_ISP_PAD:
1090	state->sensor_pix_size[RES_ISP] = frame_size;
1091	break;
1092	case S5C73M3_JPEG_PAD:
1093	state->sensor_pix_size[RES_JPEG] = frame_size;
1094	break;
1095	default:
1096	ret = -EBUSY;
1097	}
1098
1099	if (state->streaming)
1100	ret = -EBUSY;
1101	else
1102	state->apply_fmt = 1;
1103	}
1104
1105	mutex_unlock(lock: &state->lock);
1106
1107	return ret;
1108	}
1109
1110	static int s5c73m3_oif_set_fmt(struct v4l2_subdev *sd,
1111	struct v4l2_subdev_state *sd_state,
1112	struct v4l2_subdev_format *fmt)
1113	{
1114	const struct s5c73m3_frame_size *frame_size = NULL;
1115	struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
1116	struct v4l2_mbus_framefmt *mf;
1117	int ret = 0;
1118
1119	mutex_lock(&state->lock);
1120
1121	s5c73m3_oif_try_format(state, sd_state, fmt, fs: &frame_size);
1122
1123	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1124	mf = v4l2_subdev_state_get_format(sd_state, fmt->pad);
1125	*mf = fmt->format;
1126	if (fmt->pad == OIF_ISP_PAD) {
1127	mf = v4l2_subdev_state_get_format(sd_state,
1128	OIF_SOURCE_PAD);
1129	mf->width = fmt->format.width;
1130	mf->height = fmt->format.height;
1131	}
1132	} else {
1133	switch (fmt->pad) {
1134	case OIF_ISP_PAD:
1135	state->oif_pix_size[RES_ISP] = frame_size;
1136	break;
1137	case OIF_JPEG_PAD:
1138	state->oif_pix_size[RES_JPEG] = frame_size;
1139	break;
1140	case OIF_SOURCE_PAD:
1141	state->mbus_code = fmt->format.code;
1142	break;
1143	default:
1144	ret = -EBUSY;
1145	}
1146
1147	if (state->streaming)
1148	ret = -EBUSY;
1149	else
1150	state->apply_fmt = 1;
1151	}
1152
1153	mutex_unlock(lock: &state->lock);
1154
1155	return ret;
1156	}
1157
1158	static int s5c73m3_oif_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad,
1159	struct v4l2_mbus_frame_desc *fd)
1160	{
1161	struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
1162	int i;
1163
1164	if (pad != OIF_SOURCE_PAD || fd == NULL)
1165	return -EINVAL;
1166
1167	mutex_lock(&state->lock);
1168	fd->num_entries = 2;
1169	for (i = 0; i < fd->num_entries; i++)
1170	fd->entry[i] = state->frame_desc.entry[i];
1171	mutex_unlock(lock: &state->lock);
1172
1173	return 0;
1174	}
1175
1176	static int s5c73m3_oif_set_frame_desc(struct v4l2_subdev *sd, unsigned int pad,
1177	struct v4l2_mbus_frame_desc *fd)
1178	{
1179	struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
1180	struct v4l2_mbus_frame_desc *frame_desc = &state->frame_desc;
1181	int i;
1182
1183	if (pad != OIF_SOURCE_PAD || fd == NULL)
1184	return -EINVAL;
1185
1186	fd->entry[0].length = 10 * SZ_1M;
1187	fd->entry[1].length = max_t(u32, fd->entry[1].length,
1188	S5C73M3_EMBEDDED_DATA_MAXLEN);
1189	fd->num_entries = 2;
1190
1191	mutex_lock(&state->lock);
1192	for (i = 0; i < fd->num_entries; i++)
1193	frame_desc->entry[i] = fd->entry[i];
1194	mutex_unlock(lock: &state->lock);
1195
1196	return 0;
1197	}
1198
1199	static int s5c73m3_enum_mbus_code(struct v4l2_subdev *sd,
1200	struct v4l2_subdev_state *sd_state,
1201	struct v4l2_subdev_mbus_code_enum *code)
1202	{
1203	static const int codes[] = {
1204	[S5C73M3_ISP_PAD] = S5C73M3_ISP_FMT,
1205	[S5C73M3_JPEG_PAD] = S5C73M3_JPEG_FMT};
1206
1207	if (code->index > 0 || code->pad >= S5C73M3_NUM_PADS)
1208	return -EINVAL;
1209
1210	code->code = codes[code->pad];
1211
1212	return 0;
1213	}
1214
1215	static int s5c73m3_oif_enum_mbus_code(struct v4l2_subdev *sd,
1216	struct v4l2_subdev_state *sd_state,
1217	struct v4l2_subdev_mbus_code_enum *code)
1218	{
1219	int ret;
1220
1221	ret = s5c73m3_oif_get_pad_code(pad: code->pad, index: code->index);
1222	if (ret < 0)
1223	return ret;
1224
1225	code->code = ret;
1226
1227	return 0;
1228	}
1229
1230	static int s5c73m3_enum_frame_size(struct v4l2_subdev *sd,
1231	struct v4l2_subdev_state *sd_state,
1232	struct v4l2_subdev_frame_size_enum *fse)
1233	{
1234	int idx;
1235
1236	if (fse->pad == S5C73M3_ISP_PAD) {
1237	if (fse->code != S5C73M3_ISP_FMT)
1238	return -EINVAL;
1239	idx = RES_ISP;
1240	} else{
1241	if (fse->code != S5C73M3_JPEG_FMT)
1242	return -EINVAL;
1243	idx = RES_JPEG;
1244	}
1245
1246	if (fse->index >= s5c73m3_resolutions_len[idx])
1247	return -EINVAL;
1248
1249	fse->min_width = s5c73m3_resolutions[idx][fse->index].width;
1250	fse->max_width = fse->min_width;
1251	fse->max_height = s5c73m3_resolutions[idx][fse->index].height;
1252	fse->min_height = fse->max_height;
1253
1254	return 0;
1255	}
1256
1257	static int s5c73m3_oif_enum_frame_size(struct v4l2_subdev *sd,
1258	struct v4l2_subdev_state *sd_state,
1259	struct v4l2_subdev_frame_size_enum *fse)
1260	{
1261	struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
1262	int idx;
1263
1264	if (fse->pad == OIF_SOURCE_PAD) {
1265	if (fse->index > 0)
1266	return -EINVAL;
1267
1268	switch (fse->code) {
1269	case S5C73M3_JPEG_FMT:
1270	case S5C73M3_ISP_FMT: {
1271	unsigned w, h;
1272
1273	if (fse->which == V4L2_SUBDEV_FORMAT_TRY) {
1274	struct v4l2_mbus_framefmt *mf;
1275
1276	mf = v4l2_subdev_state_get_format(sd_state,
1277	OIF_ISP_PAD);
1278
1279	w = mf->width;
1280	h = mf->height;
1281	} else {
1282	const struct s5c73m3_frame_size *fs;
1283
1284	fs = state->oif_pix_size[RES_ISP];
1285	w = fs->width;
1286	h = fs->height;
1287	}
1288	fse->max_width = fse->min_width = w;
1289	fse->max_height = fse->min_height = h;
1290	return 0;
1291	}
1292	default:
1293	return -EINVAL;
1294	}
1295	}
1296
1297	if (fse->code != s5c73m3_oif_get_pad_code(pad: fse->pad, index: 0))
1298	return -EINVAL;
1299
1300	if (fse->pad == OIF_JPEG_PAD)
1301	idx = RES_JPEG;
1302	else
1303	idx = RES_ISP;
1304
1305	if (fse->index >= s5c73m3_resolutions_len[idx])
1306	return -EINVAL;
1307
1308	fse->min_width = s5c73m3_resolutions[idx][fse->index].width;
1309	fse->max_width = fse->min_width;
1310	fse->max_height = s5c73m3_resolutions[idx][fse->index].height;
1311	fse->min_height = fse->max_height;
1312
1313	return 0;
1314	}
1315
1316	static int s5c73m3_oif_log_status(struct v4l2_subdev *sd)
1317	{
1318	struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
1319
1320	v4l2_ctrl_handler_log_status(hdl: sd->ctrl_handler, prefix: sd->name);
1321
1322	v4l2_info(sd, "power: %d, apply_fmt: %d\n", state->power,
1323	state->apply_fmt);
1324
1325	return 0;
1326	}
1327
1328	static int s5c73m3_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1329	{
1330	struct v4l2_mbus_framefmt *mf;
1331
1332	mf = v4l2_subdev_state_get_format(fh->state, S5C73M3_ISP_PAD);
1333	s5c73m3_fill_mbus_fmt(mf, fs: &s5c73m3_isp_resolutions[1],
1334	S5C73M3_ISP_FMT);
1335
1336	mf = v4l2_subdev_state_get_format(fh->state, S5C73M3_JPEG_PAD);
1337	s5c73m3_fill_mbus_fmt(mf, fs: &s5c73m3_jpeg_resolutions[1],
1338	S5C73M3_JPEG_FMT);
1339
1340	return 0;
1341	}
1342
1343	static int s5c73m3_oif_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1344	{
1345	struct v4l2_mbus_framefmt *mf;
1346
1347	mf = v4l2_subdev_state_get_format(fh->state, OIF_ISP_PAD);
1348	s5c73m3_fill_mbus_fmt(mf, fs: &s5c73m3_isp_resolutions[1],
1349	S5C73M3_ISP_FMT);
1350
1351	mf = v4l2_subdev_state_get_format(fh->state, OIF_JPEG_PAD);
1352	s5c73m3_fill_mbus_fmt(mf, fs: &s5c73m3_jpeg_resolutions[1],
1353	S5C73M3_JPEG_FMT);
1354
1355	mf = v4l2_subdev_state_get_format(fh->state, OIF_SOURCE_PAD);
1356	s5c73m3_fill_mbus_fmt(mf, fs: &s5c73m3_isp_resolutions[1],
1357	S5C73M3_ISP_FMT);
1358	return 0;
1359	}
1360
1361	static int __s5c73m3_power_on(struct s5c73m3 *state)
1362	{
1363	int i, ret;
1364
1365	for (i = 0; i < S5C73M3_MAX_SUPPLIES; i++) {
1366	ret = regulator_enable(regulator: state->supplies[i].consumer);
1367	if (ret)
1368	goto err_reg_dis;
1369	}
1370
1371	ret = clk_set_rate(clk: state->clock, rate: state->mclk_frequency);
1372	if (ret < 0)
1373	goto err_reg_dis;
1374
1375	ret = clk_prepare_enable(clk: state->clock);
1376	if (ret < 0)
1377	goto err_reg_dis;
1378
1379	v4l2_dbg(1, s5c73m3_dbg, &state->oif_sd, "clock frequency: %ld\n",
1380	clk_get_rate(state->clock));
1381
1382	gpiod_set_value(desc: state->stby, value: 0);
1383	usleep_range(min: 100, max: 200);
1384	gpiod_set_value(desc: state->reset, value: 0);
1385	usleep_range(min: 50, max: 100);
1386
1387	return 0;
1388
1389	err_reg_dis:
1390	for (--i; i >= 0; i--)
1391	regulator_disable(regulator: state->supplies[i].consumer);
1392	return ret;
1393	}
1394
1395	static int __s5c73m3_power_off(struct s5c73m3 *state)
1396	{
1397	int i, ret;
1398
1399	gpiod_set_value(desc: state->reset, value: 1);
1400	usleep_range(min: 10, max: 50);
1401	gpiod_set_value(desc: state->stby, value: 1);
1402	usleep_range(min: 100, max: 200);
1403
1404	clk_disable_unprepare(clk: state->clock);
1405
1406	state->streaming = 0;
1407	state->isp_ready = 0;
1408
1409	for (i = S5C73M3_MAX_SUPPLIES - 1; i >= 0; i--) {
1410	ret = regulator_disable(regulator: state->supplies[i].consumer);
1411	if (ret)
1412	goto err;
1413	}
1414
1415	return 0;
1416	err:
1417	for (++i; i < S5C73M3_MAX_SUPPLIES; i++) {
1418	int r = regulator_enable(regulator: state->supplies[i].consumer);
1419	if (r < 0)
1420	v4l2_err(&state->oif_sd, "Failed to re-enable %s: %d\n",
1421	state->supplies[i].supply, r);
1422	}
1423
1424	clk_prepare_enable(clk: state->clock);
1425	return ret;
1426	}
1427
1428	static int s5c73m3_oif_set_power(struct v4l2_subdev *sd, int on)
1429	{
1430	struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
1431	int ret = 0;
1432
1433	mutex_lock(&state->lock);
1434
1435	if (on && !state->power) {
1436	ret = __s5c73m3_power_on(state);
1437	if (!ret)
1438	ret = s5c73m3_isp_init(state);
1439	if (!ret) {
1440	state->apply_fiv = 1;
1441	state->apply_fmt = 1;
1442	}
1443	} else if (state->power == !on) {
1444	ret = s5c73m3_set_af_softlanding(state);
1445	if (!ret)
1446	ret = __s5c73m3_power_off(state);
1447	else
1448	v4l2_err(sd, "Soft landing lens failed\n");
1449	}
1450	if (!ret)
1451	state->power += on ? 1 : -1;
1452
1453	v4l2_dbg(1, s5c73m3_dbg, sd, "%s: power: %d\n",
1454	__func__, state->power);
1455
1456	mutex_unlock(lock: &state->lock);
1457	return ret;
1458	}
1459
1460	static int s5c73m3_oif_registered(struct v4l2_subdev *sd)
1461	{
1462	struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
1463	int ret;
1464
1465	ret = v4l2_device_register_subdev(v4l2_dev: sd->v4l2_dev, sd: &state->sensor_sd);
1466	if (ret) {
1467	v4l2_err(sd->v4l2_dev, "Failed to register %s\n",
1468	state->oif_sd.name);
1469	return ret;
1470	}
1471
1472	ret = media_create_pad_link(source: &state->sensor_sd.entity,
1473	source_pad: S5C73M3_ISP_PAD, sink: &state->oif_sd.entity, sink_pad: OIF_ISP_PAD,
1474	MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED);
1475
1476	ret = media_create_pad_link(source: &state->sensor_sd.entity,
1477	source_pad: S5C73M3_JPEG_PAD, sink: &state->oif_sd.entity, sink_pad: OIF_JPEG_PAD,
1478	MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED);
1479
1480	return ret;
1481	}
1482
1483	static void s5c73m3_oif_unregistered(struct v4l2_subdev *sd)
1484	{
1485	struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
1486	v4l2_device_unregister_subdev(sd: &state->sensor_sd);
1487	}
1488
1489	static const struct v4l2_subdev_internal_ops s5c73m3_internal_ops = {
1490	.open = s5c73m3_open,
1491	};
1492
1493	static const struct v4l2_subdev_pad_ops s5c73m3_pad_ops = {
1494	.enum_mbus_code = s5c73m3_enum_mbus_code,
1495	.enum_frame_size = s5c73m3_enum_frame_size,
1496	.get_fmt = s5c73m3_get_fmt,
1497	.set_fmt = s5c73m3_set_fmt,
1498	};
1499
1500	static const struct v4l2_subdev_ops s5c73m3_subdev_ops = {
1501	.pad = &s5c73m3_pad_ops,
1502	};
1503
1504	static const struct v4l2_subdev_internal_ops oif_internal_ops = {
1505	.registered = s5c73m3_oif_registered,
1506	.unregistered = s5c73m3_oif_unregistered,
1507	.open = s5c73m3_oif_open,
1508	};
1509
1510	static const struct v4l2_subdev_pad_ops s5c73m3_oif_pad_ops = {
1511	.enum_mbus_code = s5c73m3_oif_enum_mbus_code,
1512	.enum_frame_size = s5c73m3_oif_enum_frame_size,
1513	.enum_frame_interval = s5c73m3_oif_enum_frame_interval,
1514	.get_fmt = s5c73m3_oif_get_fmt,
1515	.set_fmt = s5c73m3_oif_set_fmt,
1516	.get_frame_interval = s5c73m3_oif_get_frame_interval,
1517	.set_frame_interval = s5c73m3_oif_set_frame_interval,
1518	.get_frame_desc = s5c73m3_oif_get_frame_desc,
1519	.set_frame_desc = s5c73m3_oif_set_frame_desc,
1520	};
1521
1522	static const struct v4l2_subdev_core_ops s5c73m3_oif_core_ops = {
1523	.s_power = s5c73m3_oif_set_power,
1524	.log_status = s5c73m3_oif_log_status,
1525	};
1526
1527	static const struct v4l2_subdev_video_ops s5c73m3_oif_video_ops = {
1528	.s_stream = s5c73m3_oif_s_stream,
1529	};
1530
1531	static const struct v4l2_subdev_ops oif_subdev_ops = {
1532	.core = &s5c73m3_oif_core_ops,
1533	.pad = &s5c73m3_oif_pad_ops,
1534	.video = &s5c73m3_oif_video_ops,
1535	};
1536
1537	static int s5c73m3_get_dt_data(struct s5c73m3 *state)
1538	{
1539	struct device *dev = &state->i2c_client->dev;
1540	struct device_node *node = dev->of_node;
1541	struct device_node *node_ep;
1542	struct v4l2_fwnode_endpoint ep = { .bus_type = 0 };
1543	int ret;
1544
1545	if (!node)
1546	return -EINVAL;
1547
1548	state->clock = devm_clk_get(dev, S5C73M3_CLK_NAME);
1549	if (IS_ERR(ptr: state->clock))
1550	return PTR_ERR(ptr: state->clock);
1551
1552	if (of_property_read_u32(np: node, propname: "clock-frequency",
1553	out_value: &state->mclk_frequency)) {
1554	state->mclk_frequency = S5C73M3_DEFAULT_MCLK_FREQ;
1555	dev_info(dev, "using default %u Hz clock frequency\n",
1556	state->mclk_frequency);
1557	}
1558
1559	/* Request GPIO lines asserted */
1560	state->stby = devm_gpiod_get(dev, con_id: "standby", flags: GPIOD_OUT_HIGH);
1561	if (IS_ERR(ptr: state->stby))
1562	return dev_err_probe(dev, err: PTR_ERR(ptr: state->stby),
1563	fmt: "failed to request gpio S5C73M3_STBY\n");
1564	gpiod_set_consumer_name(desc: state->stby, name: "S5C73M3_STBY");
1565	state->reset = devm_gpiod_get(dev, con_id: "xshutdown", flags: GPIOD_OUT_HIGH);
1566	if (IS_ERR(ptr: state->reset))
1567	return dev_err_probe(dev, err: PTR_ERR(ptr: state->reset),
1568	fmt: "failed to request gpio S5C73M3_RST\n");
1569	gpiod_set_consumer_name(desc: state->reset, name: "S5C73M3_RST");
1570
1571	node_ep = of_graph_get_endpoint_by_regs(parent: node, port_reg: 0, reg: -1);
1572	if (!node_ep) {
1573	dev_warn(dev, "no endpoint defined for node: %pOF\n", node);
1574	return 0;
1575	}
1576
1577	ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(node_ep), vep: &ep);
1578	of_node_put(node: node_ep);
1579	if (ret)
1580	return ret;
1581
1582	if (ep.bus_type != V4L2_MBUS_CSI2_DPHY) {
1583	dev_err(dev, "unsupported bus type\n");
1584	return -EINVAL;
1585	}
1586	/*
1587	* Number of MIPI CSI-2 data lanes is currently not configurable,
1588	* always a default value of 4 lanes is used.
1589	*/
1590	if (ep.bus.mipi_csi2.num_data_lanes != S5C73M3_MIPI_DATA_LANES)
1591	dev_info(dev, "falling back to 4 MIPI CSI-2 data lanes\n");
1592
1593	return 0;
1594	}
1595
1596	static int s5c73m3_probe(struct i2c_client *client)
1597	{
1598	struct device *dev = &client->dev;
1599	struct v4l2_subdev *sd;
1600	struct v4l2_subdev *oif_sd;
1601	struct s5c73m3 *state;
1602	int ret, i;
1603
1604	state = devm_kzalloc(dev, size: sizeof(*state), GFP_KERNEL);
1605	if (!state)
1606	return -ENOMEM;
1607
1608	state->i2c_client = client;
1609	ret = s5c73m3_get_dt_data(state);
1610	if (ret < 0)
1611	return ret;
1612
1613	mutex_init(&state->lock);
1614	sd = &state->sensor_sd;
1615	oif_sd = &state->oif_sd;
1616
1617	v4l2_subdev_init(sd, ops: &s5c73m3_subdev_ops);
1618	sd->owner = client->dev.driver->owner;
1619	v4l2_set_subdevdata(sd, p: state);
1620	strscpy(sd->name, "S5C73M3", sizeof(sd->name));
1621
1622	sd->internal_ops = &s5c73m3_internal_ops;
1623	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1624
1625	state->sensor_pads[S5C73M3_JPEG_PAD].flags = MEDIA_PAD_FL_SOURCE;
1626	state->sensor_pads[S5C73M3_ISP_PAD].flags = MEDIA_PAD_FL_SOURCE;
1627	sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1628
1629	ret = media_entity_pads_init(entity: &sd->entity, num_pads: S5C73M3_NUM_PADS,
1630	pads: state->sensor_pads);
1631	if (ret < 0)
1632	return ret;
1633
1634	v4l2_i2c_subdev_init(sd: oif_sd, client, ops: &oif_subdev_ops);
1635	/* Static name; NEVER use in new drivers! */
1636	strscpy(oif_sd->name, "S5C73M3-OIF", sizeof(oif_sd->name));
1637
1638	oif_sd->internal_ops = &oif_internal_ops;
1639	oif_sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1640
1641	state->oif_pads[OIF_ISP_PAD].flags = MEDIA_PAD_FL_SINK;
1642	state->oif_pads[OIF_JPEG_PAD].flags = MEDIA_PAD_FL_SINK;
1643	state->oif_pads[OIF_SOURCE_PAD].flags = MEDIA_PAD_FL_SOURCE;
1644	oif_sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_SCALER;
1645
1646	ret = media_entity_pads_init(entity: &oif_sd->entity, num_pads: OIF_NUM_PADS,
1647	pads: state->oif_pads);
1648	if (ret < 0)
1649	return ret;
1650
1651	for (i = 0; i < S5C73M3_MAX_SUPPLIES; i++)
1652	state->supplies[i].supply = s5c73m3_supply_names[i];
1653
1654	ret = devm_regulator_bulk_get(dev, S5C73M3_MAX_SUPPLIES,
1655	consumers: state->supplies);
1656	if (ret) {
1657	dev_err(dev, "failed to get regulators\n");
1658	goto out_err;
1659	}
1660
1661	ret = s5c73m3_init_controls(state);
1662	if (ret)
1663	goto out_err;
1664
1665	state->sensor_pix_size[RES_ISP] = &s5c73m3_isp_resolutions[1];
1666	state->sensor_pix_size[RES_JPEG] = &s5c73m3_jpeg_resolutions[1];
1667	state->oif_pix_size[RES_ISP] = state->sensor_pix_size[RES_ISP];
1668	state->oif_pix_size[RES_JPEG] = state->sensor_pix_size[RES_JPEG];
1669
1670	state->mbus_code = S5C73M3_ISP_FMT;
1671
1672	state->fiv = &s5c73m3_intervals[S5C73M3_DEFAULT_FRAME_INTERVAL];
1673
1674	state->fw_file_version[0] = 'G';
1675	state->fw_file_version[1] = 'C';
1676
1677	ret = s5c73m3_register_spi_driver(state);
1678	if (ret < 0)
1679	goto out_err;
1680
1681	oif_sd->dev = dev;
1682
1683	ret = __s5c73m3_power_on(state);
1684	if (ret < 0)
1685	goto out_err1;
1686
1687	ret = s5c73m3_get_fw_version(state);
1688	__s5c73m3_power_off(state);
1689
1690	if (ret < 0) {
1691	dev_err(dev, "Device detection failed: %d\n", ret);
1692	goto out_err1;
1693	}
1694
1695	ret = v4l2_async_register_subdev(sd: oif_sd);
1696	if (ret < 0)
1697	goto out_err1;
1698
1699	v4l2_info(sd, "%s: completed successfully\n", __func__);
1700	return 0;
1701
1702	out_err1:
1703	s5c73m3_unregister_spi_driver(state);
1704	out_err:
1705	media_entity_cleanup(entity: &sd->entity);
1706	return ret;
1707	}
1708
1709	static void s5c73m3_remove(struct i2c_client *client)
1710	{
1711	struct v4l2_subdev *oif_sd = i2c_get_clientdata(client);
1712	struct s5c73m3 *state = oif_sd_to_s5c73m3(sd: oif_sd);
1713	struct v4l2_subdev *sensor_sd = &state->sensor_sd;
1714
1715	v4l2_async_unregister_subdev(sd: oif_sd);
1716
1717	v4l2_ctrl_handler_free(hdl: oif_sd->ctrl_handler);
1718	media_entity_cleanup(entity: &oif_sd->entity);
1719
1720	v4l2_device_unregister_subdev(sd: sensor_sd);
1721	media_entity_cleanup(entity: &sensor_sd->entity);
1722
1723	s5c73m3_unregister_spi_driver(state);
1724	}
1725
1726	static const struct i2c_device_id s5c73m3_id[] = {
1727	{ DRIVER_NAME, 0 },
1728	{ }
1729	};
1730	MODULE_DEVICE_TABLE(i2c, s5c73m3_id);
1731
1732	#ifdef CONFIG_OF
1733	static const struct of_device_id s5c73m3_of_match[] = {
1734	{ .compatible = "samsung,s5c73m3" },
1735	{ }
1736	};
1737	MODULE_DEVICE_TABLE(of, s5c73m3_of_match);
1738	#endif
1739
1740	static struct i2c_driver s5c73m3_i2c_driver = {
1741	.driver = {
1742	.of_match_table = of_match_ptr(s5c73m3_of_match),
1743	.name = DRIVER_NAME,
1744	},
1745	.probe = s5c73m3_probe,
1746	.remove = s5c73m3_remove,
1747	.id_table = s5c73m3_id,
1748	};
1749
1750	module_i2c_driver(s5c73m3_i2c_driver);
1751
1752	MODULE_DESCRIPTION("Samsung S5C73M3 camera driver");
1753	MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
1754	MODULE_LICENSE("GPL");
1755