1	// SPDX-License-Identifier: GPL-2.0
2	/*
3	* Copyright (C) 2018 Gateworks Corporation
4	*/
5	#include <linux/delay.h>
6	#include <linux/hdmi.h>
7	#include <linux/i2c.h>
8	#include <linux/init.h>
9	#include <linux/interrupt.h>
10	#include <linux/kernel.h>
11	#include <linux/module.h>
12	#include <linux/of_graph.h>
13	#include <linux/platform_device.h>
14	#include <linux/regulator/consumer.h>
15	#include <linux/types.h>
16	#include <linux/v4l2-dv-timings.h>
17	#include <linux/videodev2.h>
18
19	#include <media/v4l2-ctrls.h>
20	#include <media/v4l2-device.h>
21	#include <media/v4l2-dv-timings.h>
22	#include <media/v4l2-event.h>
23	#include <media/v4l2-fwnode.h>
24	#include <media/i2c/tda1997x.h>
25
26	#include <sound/core.h>
27	#include <sound/pcm.h>
28	#include <sound/pcm_params.h>
29	#include <sound/soc.h>
30
31	#include <dt-bindings/media/tda1997x.h>
32
33	#include "tda1997x_regs.h"
34
35	#define TDA1997X_MBUS_CODES 5
36
37	/* debug level */
38	static int debug;
39	module_param(debug, int, 0644);
40	MODULE_PARM_DESC(debug, "debug level (0-2)");
41
42	/* Audio formats */
43	static const char * const audtype_names[] = {
44	"PCM", /* PCM Samples */
45	"HBR", /* High Bit Rate Audio */
46	"OBA", /* One-Bit Audio */
47	"DST" /* Direct Stream Transfer */
48	};
49
50	/* Audio output port formats */
51	enum audfmt_types {
52	AUDFMT_TYPE_DISABLED = 0,
53	AUDFMT_TYPE_I2S,
54	AUDFMT_TYPE_SPDIF,
55	};
56	static const char * const audfmt_names[] = {
57	"Disabled",
58	"I2S",
59	"SPDIF",
60	};
61
62	/* Video input formats */
63	static const char * const hdmi_colorspace_names[] = {
64	"RGB", "YUV422", "YUV444", "YUV420", "", "", "", "",
65	};
66	static const char * const hdmi_colorimetry_names[] = {
67	"", "ITU601", "ITU709", "Extended",
68	};
69	static const char * const v4l2_quantization_names[] = {
70	"Default",
71	"Full Range (0-255)",
72	"Limited Range (16-235)",
73	};
74
75	/* Video output port formats */
76	static const char * const vidfmt_names[] = {
77	"RGB444/YUV444", /* RGB/YUV444 16bit data bus, 8bpp */
78	"YUV422 semi-planar", /* YUV422 16bit data base, 8bpp */
79	"YUV422 CCIR656", /* BT656 (YUV 8bpp 2 clock per pixel) */
80	"Invalid",
81	};
82
83	/*
84	* Colorspace conversion matrices
85	*/
86	struct color_matrix_coefs {
87	const char *name;
88	/* Input offsets */
89	s16 offint1;
90	s16 offint2;
91	s16 offint3;
92	/* Coeficients */
93	s16 p11coef;
94	s16 p12coef;
95	s16 p13coef;
96	s16 p21coef;
97	s16 p22coef;
98	s16 p23coef;
99	s16 p31coef;
100	s16 p32coef;
101	s16 p33coef;
102	/* Output offsets */
103	s16 offout1;
104	s16 offout2;
105	s16 offout3;
106	};
107
108	enum {
109	ITU709_RGBFULL,
110	ITU601_RGBFULL,
111	RGBLIMITED_RGBFULL,
112	RGBLIMITED_ITU601,
113	RGBLIMITED_ITU709,
114	RGBFULL_ITU601,
115	RGBFULL_ITU709,
116	};
117
118	/* NB: 4096 is 1.0 using fixed point numbers */
119	static const struct color_matrix_coefs conv_matrix[] = {
120	{
121	"YUV709 -> RGB full",
122	-256, -2048, -2048,
123	4769, -2183, -873,
124	4769, 7343, 0,
125	4769, 0, 8652,
126	0, 0, 0,
127	},
128	{
129	"YUV601 -> RGB full",
130	-256, -2048, -2048,
131	4769, -3330, -1602,
132	4769, 6538, 0,
133	4769, 0, 8264,
134	256, 256, 256,
135	},
136	{
137	"RGB limited -> RGB full",
138	-256, -256, -256,
139	0, 4769, 0,
140	0, 0, 4769,
141	4769, 0, 0,
142	0, 0, 0,
143	},
144	{
145	"RGB limited -> ITU601",
146	-256, -256, -256,
147	2404, 1225, 467,
148	-1754, 2095, -341,
149	-1388, -707, 2095,
150	256, 2048, 2048,
151	},
152	{
153	"RGB limited -> ITU709",
154	-256, -256, -256,
155	2918, 867, 295,
156	-1894, 2087, -190,
157	-1607, -477, 2087,
158	256, 2048, 2048,
159	},
160	{
161	"RGB full -> ITU601",
162	0, 0, 0,
163	2065, 1052, 401,
164	-1506, 1799, -293,
165	-1192, -607, 1799,
166	256, 2048, 2048,
167	},
168	{
169	"RGB full -> ITU709",
170	0, 0, 0,
171	2506, 745, 253,
172	-1627, 1792, -163,
173	-1380, -410, 1792,
174	256, 2048, 2048,
175	},
176	};
177
178	static const struct v4l2_dv_timings_cap tda1997x_dv_timings_cap = {
179	.type = V4L2_DV_BT_656_1120,
180	/* keep this initialization for compatibility with GCC < 4.4.6 */
181	.reserved = { 0 },
182
183	V4L2_INIT_BT_TIMINGS(
184	640, 1920, /* min/max width */
185	350, 1200, /* min/max height */
186	13000000, 165000000, /* min/max pixelclock */
187	/* standards */
188	V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
189	V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
190	/* capabilities */
191	V4L2_DV_BT_CAP_INTERLACED | V4L2_DV_BT_CAP_PROGRESSIVE |
192	V4L2_DV_BT_CAP_REDUCED_BLANKING |
193	V4L2_DV_BT_CAP_CUSTOM
194	)
195	};
196
197	/* regulator supplies */
198	static const char * const tda1997x_supply_name[] = {
199	"DOVDD", /* Digital I/O supply */
200	"DVDD", /* Digital Core supply */
201	"AVDD", /* Analog supply */
202	};
203
204	#define TDA1997X_NUM_SUPPLIES ARRAY_SIZE(tda1997x_supply_name)
205
206	enum tda1997x_type {
207	TDA19971,
208	TDA19973,
209	};
210
211	enum tda1997x_hdmi_pads {
212	TDA1997X_PAD_SOURCE,
213	TDA1997X_NUM_PADS,
214	};
215
216	struct tda1997x_chip_info {
217	enum tda1997x_type type;
218	const char *name;
219	};
220
221	struct tda1997x_state {
222	const struct tda1997x_chip_info *info;
223	struct tda1997x_platform_data pdata;
224	struct i2c_client *client;
225	struct i2c_client *client_cec;
226	struct v4l2_subdev sd;
227	struct regulator_bulk_data supplies[TDA1997X_NUM_SUPPLIES];
228	struct media_pad pads[TDA1997X_NUM_PADS];
229	struct mutex lock;
230	struct mutex page_lock;
231	char page;
232
233	/* detected info from chip */
234	int chip_revision;
235	char port_30bit;
236	char output_2p5;
237	char tmdsb_clk;
238	char tmdsb_soc;
239
240	/* status info */
241	char hdmi_status;
242	char mptrw_in_progress;
243	char activity_status;
244	char input_detect[2];
245
246	/* video */
247	struct hdmi_avi_infoframe avi_infoframe;
248	struct v4l2_hdmi_colorimetry colorimetry;
249	u32 rgb_quantization_range;
250	struct v4l2_dv_timings timings;
251	int fps;
252	const struct color_matrix_coefs *conv;
253	u32 mbus_codes[TDA1997X_MBUS_CODES]; /* available modes */
254	u32 mbus_code; /* current mode */
255	u8 vid_fmt;
256
257	/* controls */
258	struct v4l2_ctrl_handler hdl;
259	struct v4l2_ctrl *detect_tx_5v_ctrl;
260	struct v4l2_ctrl *rgb_quantization_range_ctrl;
261
262	/* audio */
263	u8 audio_ch_alloc;
264	int audio_samplerate;
265	int audio_channels;
266	int audio_samplesize;
267	int audio_type;
268	struct mutex audio_lock;
269	struct snd_pcm_substream *audio_stream;
270
271	/* EDID */
272	struct {
273	u8 edid[256];
274	u32 present;
275	unsigned int blocks;
276	} edid;
277	struct delayed_work delayed_work_enable_hpd;
278	};
279
280	static const struct v4l2_event tda1997x_ev_fmt = {
281	.type = V4L2_EVENT_SOURCE_CHANGE,
282	.u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
283	};
284
285	static const struct tda1997x_chip_info tda1997x_chip_info[] = {
286	[TDA19971] = {
287	.type = TDA19971,
288	.name = "tda19971",
289	},
290	[TDA19973] = {
291	.type = TDA19973,
292	.name = "tda19973",
293	},
294	};
295
296	static inline struct tda1997x_state *to_state(struct v4l2_subdev *sd)
297	{
298	return container_of(sd, struct tda1997x_state, sd);
299	}
300
301	static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
302	{
303	return &container_of(ctrl->handler, struct tda1997x_state, hdl)->sd;
304	}
305
306	static int tda1997x_cec_read(struct v4l2_subdev *sd, u8 reg)
307	{
308	struct tda1997x_state *state = to_state(sd);
309	int val;
310
311	val = i2c_smbus_read_byte_data(client: state->client_cec, command: reg);
312	if (val < 0) {
313	v4l_err(state->client, "read reg error: reg=%2x\n", reg);
314	val = -1;
315	}
316
317	return val;
318	}
319
320	static int tda1997x_cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
321	{
322	struct tda1997x_state *state = to_state(sd);
323	int ret = 0;
324
325	ret = i2c_smbus_write_byte_data(client: state->client_cec, command: reg, value: val);
326	if (ret < 0) {
327	v4l_err(state->client, "write reg error:reg=%2x,val=%2x\n",
328	reg, val);
329	ret = -1;
330	}
331
332	return ret;
333	}
334
335	/* -----------------------------------------------------------------------------
336	* I2C transfer
337	*/
338
339	static int tda1997x_setpage(struct v4l2_subdev *sd, u8 page)
340	{
341	struct tda1997x_state *state = to_state(sd);
342	int ret;
343
344	if (state->page != page) {
345	ret = i2c_smbus_write_byte_data(client: state->client,
346	REG_CURPAGE_00H, value: page);
347	if (ret < 0) {
348	v4l_err(state->client,
349	"write reg error:reg=%2x,val=%2x\n",
350	REG_CURPAGE_00H, page);
351	return ret;
352	}
353	state->page = page;
354	}
355	return 0;
356	}
357
358	static inline int io_read(struct v4l2_subdev *sd, u16 reg)
359	{
360	struct tda1997x_state *state = to_state(sd);
361	int val;
362
363	mutex_lock(&state->page_lock);
364	if (tda1997x_setpage(sd, page: reg >> 8)) {
365	val = -1;
366	goto out;
367	}
368
369	val = i2c_smbus_read_byte_data(client: state->client, command: reg&0xff);
370	if (val < 0) {
371	v4l_err(state->client, "read reg error: reg=%2x\n", reg & 0xff);
372	val = -1;
373	goto out;
374	}
375
376	out:
377	mutex_unlock(lock: &state->page_lock);
378	return val;
379	}
380
381	static inline long io_read16(struct v4l2_subdev *sd, u16 reg)
382	{
383	int val;
384	long lval = 0;
385
386	val = io_read(sd, reg);
387	if (val < 0)
388	return val;
389	lval |= (val << 8);
390	val = io_read(sd, reg: reg + 1);
391	if (val < 0)
392	return val;
393	lval |= val;
394
395	return lval;
396	}
397
398	static inline long io_read24(struct v4l2_subdev *sd, u16 reg)
399	{
400	int val;
401	long lval = 0;
402
403	val = io_read(sd, reg);
404	if (val < 0)
405	return val;
406	lval |= (val << 16);
407	val = io_read(sd, reg: reg + 1);
408	if (val < 0)
409	return val;
410	lval |= (val << 8);
411	val = io_read(sd, reg: reg + 2);
412	if (val < 0)
413	return val;
414	lval |= val;
415
416	return lval;
417	}
418
419	static unsigned int io_readn(struct v4l2_subdev *sd, u16 reg, u8 len, u8 *data)
420	{
421	int i;
422	int sz = 0;
423	int val;
424
425	for (i = 0; i < len; i++) {
426	val = io_read(sd, reg: reg + i);
427	if (val < 0)
428	break;
429	data[i] = val;
430	sz++;
431	}
432
433	return sz;
434	}
435
436	static int io_write(struct v4l2_subdev *sd, u16 reg, u8 val)
437	{
438	struct tda1997x_state *state = to_state(sd);
439	s32 ret = 0;
440
441	mutex_lock(&state->page_lock);
442	if (tda1997x_setpage(sd, page: reg >> 8)) {
443	ret = -1;
444	goto out;
445	}
446
447	ret = i2c_smbus_write_byte_data(client: state->client, command: reg & 0xff, value: val);
448	if (ret < 0) {
449	v4l_err(state->client, "write reg error:reg=%2x,val=%2x\n",
450	reg&0xff, val);
451	ret = -1;
452	goto out;
453	}
454
455	out:
456	mutex_unlock(lock: &state->page_lock);
457	return ret;
458	}
459
460	static int io_write16(struct v4l2_subdev *sd, u16 reg, u16 val)
461	{
462	int ret;
463
464	ret = io_write(sd, reg, val: (val >> 8) & 0xff);
465	if (ret < 0)
466	return ret;
467	ret = io_write(sd, reg: reg + 1, val: val & 0xff);
468	if (ret < 0)
469	return ret;
470	return 0;
471	}
472
473	static int io_write24(struct v4l2_subdev *sd, u16 reg, u32 val)
474	{
475	int ret;
476
477	ret = io_write(sd, reg, val: (val >> 16) & 0xff);
478	if (ret < 0)
479	return ret;
480	ret = io_write(sd, reg: reg + 1, val: (val >> 8) & 0xff);
481	if (ret < 0)
482	return ret;
483	ret = io_write(sd, reg: reg + 2, val: val & 0xff);
484	if (ret < 0)
485	return ret;
486	return 0;
487	}
488
489	/* -----------------------------------------------------------------------------
490	* Hotplug
491	*/
492
493	enum hpd_mode {
494	HPD_LOW_BP, /* HPD low and pulse of at least 100ms */
495	HPD_LOW_OTHER, /* HPD low and pulse of at least 100ms */
496	HPD_HIGH_BP, /* HIGH */
497	HPD_HIGH_OTHER,
498	HPD_PULSE, /* HPD low pulse */
499	};
500
501	/* manual HPD (Hot Plug Detect) control */
502	static int tda1997x_manual_hpd(struct v4l2_subdev *sd, enum hpd_mode mode)
503	{
504	u8 hpd_auto, hpd_pwr, hpd_man;
505
506	hpd_auto = io_read(sd, REG_HPD_AUTO_CTRL);
507	hpd_pwr = io_read(sd, REG_HPD_POWER);
508	hpd_man = io_read(sd, REG_HPD_MAN_CTRL);
509
510	/* mask out unused bits */
511	hpd_man &= (HPD_MAN_CTRL_HPD_PULSE |
512	HPD_MAN_CTRL_5VEN |
513	HPD_MAN_CTRL_HPD_B |
514	HPD_MAN_CTRL_HPD_A);
515
516	switch (mode) {
517	/* HPD low and pulse of at least 100ms */
518	case HPD_LOW_BP:
519	/* hpd_bp=0 */
520	hpd_pwr &= ~HPD_POWER_BP_MASK;
521	/* disable HPD_A and HPD_B */
522	hpd_man &= ~(HPD_MAN_CTRL_HPD_A | HPD_MAN_CTRL_HPD_B);
523	io_write(sd, REG_HPD_POWER, val: hpd_pwr);
524	io_write(sd, REG_HPD_MAN_CTRL, val: hpd_man);
525	break;
526	/* HPD high */
527	case HPD_HIGH_BP:
528	/* hpd_bp=1 */
529	hpd_pwr &= ~HPD_POWER_BP_MASK;
530	hpd_pwr |= 1 << HPD_POWER_BP_SHIFT;
531	io_write(sd, REG_HPD_POWER, val: hpd_pwr);
532	break;
533	/* HPD low and pulse of at least 100ms */
534	case HPD_LOW_OTHER:
535	/* disable HPD_A and HPD_B */
536	hpd_man &= ~(HPD_MAN_CTRL_HPD_A | HPD_MAN_CTRL_HPD_B);
537	/* hp_other=0 */
538	hpd_auto &= ~HPD_AUTO_HP_OTHER;
539	io_write(sd, REG_HPD_AUTO_CTRL, val: hpd_auto);
540	io_write(sd, REG_HPD_MAN_CTRL, val: hpd_man);
541	break;
542	/* HPD high */
543	case HPD_HIGH_OTHER:
544	hpd_auto |= HPD_AUTO_HP_OTHER;
545	io_write(sd, REG_HPD_AUTO_CTRL, val: hpd_auto);
546	break;
547	/* HPD low pulse */
548	case HPD_PULSE:
549	/* disable HPD_A and HPD_B */
550	hpd_man &= ~(HPD_MAN_CTRL_HPD_A | HPD_MAN_CTRL_HPD_B);
551	io_write(sd, REG_HPD_MAN_CTRL, val: hpd_man);
552	break;
553	}
554
555	return 0;
556	}
557
558	static void tda1997x_delayed_work_enable_hpd(struct work_struct *work)
559	{
560	struct delayed_work *dwork = to_delayed_work(work);
561	struct tda1997x_state *state = container_of(dwork,
562	struct tda1997x_state,
563	delayed_work_enable_hpd);
564	struct v4l2_subdev *sd = &state->sd;
565
566	v4l2_dbg(2, debug, sd, "%s\n", __func__);
567
568	/* Set HPD high */
569	tda1997x_manual_hpd(sd, mode: HPD_HIGH_OTHER);
570	tda1997x_manual_hpd(sd, mode: HPD_HIGH_BP);
571
572	state->edid.present = 1;
573	}
574
575	static void tda1997x_disable_edid(struct v4l2_subdev *sd)
576	{
577	struct tda1997x_state *state = to_state(sd);
578
579	v4l2_dbg(1, debug, sd, "%s\n", __func__);
580	cancel_delayed_work_sync(dwork: &state->delayed_work_enable_hpd);
581
582	/* Set HPD low */
583	tda1997x_manual_hpd(sd, mode: HPD_LOW_BP);
584	}
585
586	static void tda1997x_enable_edid(struct v4l2_subdev *sd)
587	{
588	struct tda1997x_state *state = to_state(sd);
589
590	v4l2_dbg(1, debug, sd, "%s\n", __func__);
591
592	/* Enable hotplug after 100ms */
593	schedule_delayed_work(dwork: &state->delayed_work_enable_hpd, HZ / 10);
594	}
595
596	/* -----------------------------------------------------------------------------
597	* Signal Control
598	*/
599
600	/*
601	* configure vid_fmt based on mbus_code
602	*/
603	static int
604	tda1997x_setup_format(struct tda1997x_state *state, u32 code)
605	{
606	v4l_dbg(1, debug, state->client, "%s code=0x%x\n", __func__, code);
607	switch (code) {
608	case MEDIA_BUS_FMT_RGB121212_1X36:
609	case MEDIA_BUS_FMT_RGB888_1X24:
610	case MEDIA_BUS_FMT_YUV12_1X36:
611	case MEDIA_BUS_FMT_YUV8_1X24:
612	state->vid_fmt = OF_FMT_444;
613	break;
614	case MEDIA_BUS_FMT_UYVY12_1X24:
615	case MEDIA_BUS_FMT_UYVY10_1X20:
616	case MEDIA_BUS_FMT_UYVY8_1X16:
617	state->vid_fmt = OF_FMT_422_SMPT;
618	break;
619	case MEDIA_BUS_FMT_UYVY12_2X12:
620	case MEDIA_BUS_FMT_UYVY10_2X10:
621	case MEDIA_BUS_FMT_UYVY8_2X8:
622	state->vid_fmt = OF_FMT_422_CCIR;
623	break;
624	default:
625	v4l_err(state->client, "incompatible format (0x%x)\n", code);
626	return -EINVAL;
627	}
628	v4l_dbg(1, debug, state->client, "%s code=0x%x fmt=%s\n", __func__,
629	code, vidfmt_names[state->vid_fmt]);
630	state->mbus_code = code;
631
632	return 0;
633	}
634
635	/*
636	* The color conversion matrix will convert between the colorimetry of the
637	* HDMI input to the desired output format RGB|YUV. RGB output is to be
638	* full-range and YUV is to be limited range.
639	*
640	* RGB full-range uses values from 0 to 255 which is recommended on a monitor
641	* and RGB Limited uses values from 16 to 236 (16=black, 235=white) which is
642	* typically recommended on a TV.
643	*/
644	static void
645	tda1997x_configure_csc(struct v4l2_subdev *sd)
646	{
647	struct tda1997x_state *state = to_state(sd);
648	struct hdmi_avi_infoframe *avi = &state->avi_infoframe;
649	struct v4l2_hdmi_colorimetry *c = &state->colorimetry;
650	/* Blanking code values depend on output colorspace (RGB or YUV) */
651	struct blanking_codes {
652	s16 code_gy;
653	s16 code_bu;
654	s16 code_rv;
655	};
656	static const struct blanking_codes rgb_blanking = { .code_gy: 64, .code_bu: 64, .code_rv: 64 };
657	static const struct blanking_codes yuv_blanking = { .code_gy: 64, .code_bu: 512, .code_rv: 512 };
658	const struct blanking_codes *blanking_codes = NULL;
659	u8 reg;
660
661	v4l_dbg(1, debug, state->client, "input:%s quant:%s output:%s\n",
662	hdmi_colorspace_names[avi->colorspace],
663	v4l2_quantization_names[c->quantization],
664	vidfmt_names[state->vid_fmt]);
665	state->conv = NULL;
666	switch (state->vid_fmt) {
667	/* RGB output */
668	case OF_FMT_444:
669	blanking_codes = &rgb_blanking;
670	if (c->colorspace == V4L2_COLORSPACE_SRGB) {
671	if (c->quantization == V4L2_QUANTIZATION_LIM_RANGE)
672	state->conv = &conv_matrix[RGBLIMITED_RGBFULL];
673	} else {
674	if (c->colorspace == V4L2_COLORSPACE_REC709)
675	state->conv = &conv_matrix[ITU709_RGBFULL];
676	else if (c->colorspace == V4L2_COLORSPACE_SMPTE170M)
677	state->conv = &conv_matrix[ITU601_RGBFULL];
678	}
679	break;
680
681	/* YUV output */
682	case OF_FMT_422_SMPT: /* semi-planar */
683	case OF_FMT_422_CCIR: /* CCIR656 */
684	blanking_codes = &yuv_blanking;
685	if ((c->colorspace == V4L2_COLORSPACE_SRGB) &&
686	(c->quantization == V4L2_QUANTIZATION_FULL_RANGE)) {
687	if (state->timings.bt.height <= 576)
688	state->conv = &conv_matrix[RGBFULL_ITU601];
689	else
690	state->conv = &conv_matrix[RGBFULL_ITU709];
691	} else if ((c->colorspace == V4L2_COLORSPACE_SRGB) &&
692	(c->quantization == V4L2_QUANTIZATION_LIM_RANGE)) {
693	if (state->timings.bt.height <= 576)
694	state->conv = &conv_matrix[RGBLIMITED_ITU601];
695	else
696	state->conv = &conv_matrix[RGBLIMITED_ITU709];
697	}
698	break;
699	}
700
701	if (state->conv) {
702	v4l_dbg(1, debug, state->client, "%s\n",
703	state->conv->name);
704	/* enable matrix conversion */
705	reg = io_read(sd, REG_VDP_CTRL);
706	reg &= ~VDP_CTRL_MATRIX_BP;
707	io_write(sd, REG_VDP_CTRL, val: reg);
708	/* offset inputs */
709	io_write16(sd, REG_VDP_MATRIX + 0, val: state->conv->offint1);
710	io_write16(sd, REG_VDP_MATRIX + 2, val: state->conv->offint2);
711	io_write16(sd, REG_VDP_MATRIX + 4, val: state->conv->offint3);
712	/* coefficients */
713	io_write16(sd, REG_VDP_MATRIX + 6, val: state->conv->p11coef);
714	io_write16(sd, REG_VDP_MATRIX + 8, val: state->conv->p12coef);
715	io_write16(sd, REG_VDP_MATRIX + 10, val: state->conv->p13coef);
716	io_write16(sd, REG_VDP_MATRIX + 12, val: state->conv->p21coef);
717	io_write16(sd, REG_VDP_MATRIX + 14, val: state->conv->p22coef);
718	io_write16(sd, REG_VDP_MATRIX + 16, val: state->conv->p23coef);
719	io_write16(sd, REG_VDP_MATRIX + 18, val: state->conv->p31coef);
720	io_write16(sd, REG_VDP_MATRIX + 20, val: state->conv->p32coef);
721	io_write16(sd, REG_VDP_MATRIX + 22, val: state->conv->p33coef);
722	/* offset outputs */
723	io_write16(sd, REG_VDP_MATRIX + 24, val: state->conv->offout1);
724	io_write16(sd, REG_VDP_MATRIX + 26, val: state->conv->offout2);
725	io_write16(sd, REG_VDP_MATRIX + 28, val: state->conv->offout3);
726	} else {
727	/* disable matrix conversion */
728	reg = io_read(sd, REG_VDP_CTRL);
729	reg |= VDP_CTRL_MATRIX_BP;
730	io_write(sd, REG_VDP_CTRL, val: reg);
731	}
732
733	/* SetBlankingCodes */
734	if (blanking_codes) {
735	io_write16(sd, REG_BLK_GY, val: blanking_codes->code_gy);
736	io_write16(sd, REG_BLK_BU, val: blanking_codes->code_bu);
737	io_write16(sd, REG_BLK_RV, val: blanking_codes->code_rv);
738	}
739	}
740
741	/* Configure frame detection window and VHREF timing generator */
742	static void
743	tda1997x_configure_vhref(struct v4l2_subdev *sd)
744	{
745	struct tda1997x_state *state = to_state(sd);
746	const struct v4l2_bt_timings *bt = &state->timings.bt;
747	int width, lines;
748	u16 href_start, href_end;
749	u16 vref_f1_start, vref_f2_start;
750	u8 vref_f1_width, vref_f2_width;
751	u8 field_polarity;
752	u16 fieldref_f1_start, fieldref_f2_start;
753	u8 reg;
754
755	href_start = bt->hbackporch + bt->hsync + 1;
756	href_end = href_start + bt->width;
757	vref_f1_start = bt->height + bt->vbackporch + bt->vsync +
758	bt->il_vbackporch + bt->il_vsync +
759	bt->il_vfrontporch;
760	vref_f1_width = bt->vbackporch + bt->vsync + bt->vfrontporch;
761	vref_f2_start = 0;
762	vref_f2_width = 0;
763	fieldref_f1_start = 0;
764	fieldref_f2_start = 0;
765	if (bt->interlaced) {
766	vref_f2_start = (bt->height / 2) +
767	(bt->il_vbackporch + bt->il_vsync - 1);
768	vref_f2_width = bt->il_vbackporch + bt->il_vsync +
769	bt->il_vfrontporch;
770	fieldref_f2_start = vref_f2_start + bt->il_vfrontporch +
771	fieldref_f1_start;
772	}
773	field_polarity = 0;
774
775	width = V4L2_DV_BT_FRAME_WIDTH(bt);
776	lines = V4L2_DV_BT_FRAME_HEIGHT(bt);
777
778	/*
779	* Configure Frame Detection Window:
780	* horiz area where the VHREF module consider a VSYNC a new frame
781	*/
782	io_write16(sd, REG_FDW_S, val: 0x2ef); /* start position */
783	io_write16(sd, REG_FDW_E, val: 0x141); /* end position */
784
785	/* Set Pixel And Line Counters */
786	if (state->chip_revision == 0)
787	io_write16(sd, REG_PXCNT_PR, val: 4);
788	else
789	io_write16(sd, REG_PXCNT_PR, val: 1);
790	io_write16(sd, REG_PXCNT_NPIX, val: width & MASK_VHREF);
791	io_write16(sd, REG_LCNT_PR, val: 1);
792	io_write16(sd, REG_LCNT_NLIN, val: lines & MASK_VHREF);
793
794	/*
795	* Configure the VHRef timing generator responsible for rebuilding all
796	* horiz and vert synch and ref signals from its input allowing auto
797	* detection algorithms and forcing predefined modes (480i & 576i)
798	*/
799	reg = VHREF_STD_DET_OFF << VHREF_STD_DET_SHIFT;
800	io_write(sd, REG_VHREF_CTRL, val: reg);
801
802	/*
803	* Configure the VHRef timing values. In case the VHREF generator has
804	* been configured in manual mode, this will allow to manually set all
805	* horiz and vert ref values (non-active pixel areas) of the generator
806	* and allows setting the frame reference params.
807	*/
808	/* horizontal reference start/end */
809	io_write16(sd, REG_HREF_S, val: href_start & MASK_VHREF);
810	io_write16(sd, REG_HREF_E, val: href_end & MASK_VHREF);
811	/* vertical reference f1 start/end */
812	io_write16(sd, REG_VREF_F1_S, val: vref_f1_start & MASK_VHREF);
813	io_write(sd, REG_VREF_F1_WIDTH, val: vref_f1_width);
814	/* vertical reference f2 start/end */
815	io_write16(sd, REG_VREF_F2_S, val: vref_f2_start & MASK_VHREF);
816	io_write(sd, REG_VREF_F2_WIDTH, val: vref_f2_width);
817
818	/* F1/F2 FREF, field polarity */
819	reg = fieldref_f1_start & MASK_VHREF;
820	reg |= field_polarity << 8;
821	io_write16(sd, REG_FREF_F1_S, val: reg);
822	reg = fieldref_f2_start & MASK_VHREF;
823	io_write16(sd, REG_FREF_F2_S, val: reg);
824	}
825
826	/* Configure Video Output port signals */
827	static int
828	tda1997x_configure_vidout(struct tda1997x_state *state)
829	{
830	struct v4l2_subdev *sd = &state->sd;
831	struct tda1997x_platform_data *pdata = &state->pdata;
832	u8 prefilter;
833	u8 reg;
834
835	/* Configure pixel clock generator: delay, polarity, rate */
836	reg = (state->vid_fmt == OF_FMT_422_CCIR) ?
837	PCLK_SEL_X2 : PCLK_SEL_X1;
838	reg |= pdata->vidout_delay_pclk << PCLK_DELAY_SHIFT;
839	reg |= pdata->vidout_inv_pclk << PCLK_INV_SHIFT;
840	io_write(sd, REG_PCLK, val: reg);
841
842	/* Configure pre-filter */
843	prefilter = 0; /* filters off */
844	/* YUV422 mode requires conversion */
845	if ((state->vid_fmt == OF_FMT_422_SMPT) ||
846	(state->vid_fmt == OF_FMT_422_CCIR)) {
847	/* 2/7 taps for Rv and Bu */
848	prefilter = FILTERS_CTRL_2_7TAP << FILTERS_CTRL_BU_SHIFT |
849	FILTERS_CTRL_2_7TAP << FILTERS_CTRL_RV_SHIFT;
850	}
851	io_write(sd, REG_FILTERS_CTRL, val: prefilter);
852
853	/* Configure video port */
854	reg = state->vid_fmt & OF_FMT_MASK;
855	if (state->vid_fmt == OF_FMT_422_CCIR)
856	reg |= (OF_BLK | OF_TRC);
857	reg |= OF_VP_ENABLE;
858	io_write(sd, REG_OF, val: reg);
859
860	/* Configure formatter and conversions */
861	reg = io_read(sd, REG_VDP_CTRL);
862	/* pre-filter is needed unless (REG_FILTERS_CTRL == 0) */
863	if (!prefilter)
864	reg |= VDP_CTRL_PREFILTER_BP;
865	else
866	reg &= ~VDP_CTRL_PREFILTER_BP;
867	/* formatter is needed for YUV422 and for trc/blc codes */
868	if (state->vid_fmt == OF_FMT_444)
869	reg |= VDP_CTRL_FORMATTER_BP;
870	/* formatter and compdel needed for timing/blanking codes */
871	else
872	reg &= ~(VDP_CTRL_FORMATTER_BP | VDP_CTRL_COMPDEL_BP);
873	/* activate compdel for small sync delays */
874	if ((pdata->vidout_delay_vs < 4) || (pdata->vidout_delay_hs < 4))
875	reg &= ~VDP_CTRL_COMPDEL_BP;
876	io_write(sd, REG_VDP_CTRL, val: reg);
877
878	/* Configure DE output signal: delay, polarity, and source */
879	reg = pdata->vidout_delay_de << DE_FREF_DELAY_SHIFT |
880	pdata->vidout_inv_de << DE_FREF_INV_SHIFT |
881	pdata->vidout_sel_de << DE_FREF_SEL_SHIFT;
882	io_write(sd, REG_DE_FREF, val: reg);
883
884	/* Configure HS/HREF output signal: delay, polarity, and source */
885	if (state->vid_fmt != OF_FMT_422_CCIR) {
886	reg = pdata->vidout_delay_hs << HS_HREF_DELAY_SHIFT |
887	pdata->vidout_inv_hs << HS_HREF_INV_SHIFT |
888	pdata->vidout_sel_hs << HS_HREF_SEL_SHIFT;
889	} else
890	reg = HS_HREF_SEL_NONE << HS_HREF_SEL_SHIFT;
891	io_write(sd, REG_HS_HREF, val: reg);
892
893	/* Configure VS/VREF output signal: delay, polarity, and source */
894	if (state->vid_fmt != OF_FMT_422_CCIR) {
895	reg = pdata->vidout_delay_vs << VS_VREF_DELAY_SHIFT |
896	pdata->vidout_inv_vs << VS_VREF_INV_SHIFT |
897	pdata->vidout_sel_vs << VS_VREF_SEL_SHIFT;
898	} else
899	reg = VS_VREF_SEL_NONE << VS_VREF_SEL_SHIFT;
900	io_write(sd, REG_VS_VREF, val: reg);
901
902	return 0;
903	}
904
905	/* Configure Audio output port signals */
906	static int
907	tda1997x_configure_audout(struct v4l2_subdev *sd, u8 channel_assignment)
908	{
909	struct tda1997x_state *state = to_state(sd);
910	struct tda1997x_platform_data *pdata = &state->pdata;
911	bool sp_used_by_fifo = true;
912	u8 reg;
913
914	if (!pdata->audout_format)
915	return 0;
916
917	/* channel assignment (CEA-861-D Table 20) */
918	io_write(sd, REG_AUDIO_PATH, val: channel_assignment);
919
920	/* Audio output configuration */
921	reg = 0;
922	switch (pdata->audout_format) {
923	case AUDFMT_TYPE_I2S:
924	reg |= AUDCFG_BUS_I2S << AUDCFG_BUS_SHIFT;
925	break;
926	case AUDFMT_TYPE_SPDIF:
927	reg |= AUDCFG_BUS_SPDIF << AUDCFG_BUS_SHIFT;
928	break;
929	}
930	switch (state->audio_type) {
931	case AUDCFG_TYPE_PCM:
932	reg |= AUDCFG_TYPE_PCM << AUDCFG_TYPE_SHIFT;
933	break;
934	case AUDCFG_TYPE_OBA:
935	reg |= AUDCFG_TYPE_OBA << AUDCFG_TYPE_SHIFT;
936	break;
937	case AUDCFG_TYPE_DST:
938	reg |= AUDCFG_TYPE_DST << AUDCFG_TYPE_SHIFT;
939	sp_used_by_fifo = false;
940	break;
941	case AUDCFG_TYPE_HBR:
942	reg |= AUDCFG_TYPE_HBR << AUDCFG_TYPE_SHIFT;
943	if (pdata->audout_layout == 1) {
944	/* demuxed via AP0:AP3 */
945	reg |= AUDCFG_HBR_DEMUX << AUDCFG_HBR_SHIFT;
946	if (pdata->audout_format == AUDFMT_TYPE_SPDIF)
947	sp_used_by_fifo = false;
948	} else {
949	/* straight via AP0 */
950	reg |= AUDCFG_HBR_STRAIGHT << AUDCFG_HBR_SHIFT;
951	}
952	break;
953	}
954	if (pdata->audout_width == 32)
955	reg |= AUDCFG_I2SW_32 << AUDCFG_I2SW_SHIFT;
956	else
957	reg |= AUDCFG_I2SW_16 << AUDCFG_I2SW_SHIFT;
958
959	/* automatic hardware mute */
960	if (pdata->audio_auto_mute)
961	reg |= AUDCFG_AUTO_MUTE_EN;
962	/* clock polarity */
963	if (pdata->audout_invert_clk)
964	reg |= AUDCFG_CLK_INVERT;
965	io_write(sd, REG_AUDCFG, val: reg);
966
967	/* audio layout */
968	reg = (pdata->audout_layout) ? AUDIO_LAYOUT_LAYOUT1 : 0;
969	if (!pdata->audout_layoutauto)
970	reg |= AUDIO_LAYOUT_MANUAL;
971	if (sp_used_by_fifo)
972	reg |= AUDIO_LAYOUT_SP_FLAG;
973	io_write(sd, REG_AUDIO_LAYOUT, val: reg);
974
975	/* FIFO Latency value */
976	io_write(sd, REG_FIFO_LATENCY_VAL, val: 0x80);
977
978	/* Audio output port config */
979	if (sp_used_by_fifo) {
980	reg = AUDIO_OUT_ENABLE_AP0;
981	if (channel_assignment >= 0x01)
982	reg |= AUDIO_OUT_ENABLE_AP1;
983	if (channel_assignment >= 0x04)
984	reg |= AUDIO_OUT_ENABLE_AP2;
985	if (channel_assignment >= 0x0c)
986	reg |= AUDIO_OUT_ENABLE_AP3;
987	/* specific cases where AP1 is not used */
988	if ((channel_assignment == 0x04)
989	|| (channel_assignment == 0x08)
990	|| (channel_assignment == 0x0c)
991	|| (channel_assignment == 0x10)
992	|| (channel_assignment == 0x14)
993	|| (channel_assignment == 0x18)
994	|| (channel_assignment == 0x1c))
995	reg &= ~AUDIO_OUT_ENABLE_AP1;
996	/* specific cases where AP2 is not used */
997	if ((channel_assignment >= 0x14)
998	&& (channel_assignment <= 0x17))
999	reg &= ~AUDIO_OUT_ENABLE_AP2;
1000	} else {
1001	reg = AUDIO_OUT_ENABLE_AP3 |
1002	AUDIO_OUT_ENABLE_AP2 |
1003	AUDIO_OUT_ENABLE_AP1 |
1004	AUDIO_OUT_ENABLE_AP0;
1005	}
1006	if (pdata->audout_format == AUDFMT_TYPE_I2S)
1007	reg |= (AUDIO_OUT_ENABLE_ACLK | AUDIO_OUT_ENABLE_WS);
1008	io_write(sd, REG_AUDIO_OUT_ENABLE, val: reg);
1009
1010	/* reset test mode to normal audio freq auto selection */
1011	io_write(sd, REG_TEST_MODE, val: 0x00);
1012
1013	return 0;
1014	}
1015
1016	/* Soft Reset of specific hdmi info */
1017	static int
1018	tda1997x_hdmi_info_reset(struct v4l2_subdev *sd, u8 info_rst, bool reset_sus)
1019	{
1020	u8 reg;
1021
1022	/* reset infoframe engine packets */
1023	reg = io_read(sd, REG_HDMI_INFO_RST);
1024	io_write(sd, REG_HDMI_INFO_RST, val: info_rst);
1025
1026	/* if infoframe engine has been reset clear INT_FLG_MODE */
1027	if (reg & RESET_IF) {
1028	reg = io_read(sd, REG_INT_FLG_CLR_MODE);
1029	io_write(sd, REG_INT_FLG_CLR_MODE, val: reg);
1030	}
1031
1032	/* Disable REFTIM to restart start-up-sequencer (SUS) */
1033	reg = io_read(sd, REG_RATE_CTRL);
1034	reg &= ~RATE_REFTIM_ENABLE;
1035	if (!reset_sus)
1036	reg |= RATE_REFTIM_ENABLE;
1037	reg = io_write(sd, REG_RATE_CTRL, val: reg);
1038
1039	return 0;
1040	}
1041
1042	static void
1043	tda1997x_power_mode(struct tda1997x_state *state, bool enable)
1044	{
1045	struct v4l2_subdev *sd = &state->sd;
1046	u8 reg;
1047
1048	if (enable) {
1049	/* Automatic control of TMDS */
1050	io_write(sd, REG_PON_OVR_EN, PON_DIS);
1051	/* Enable current bias unit */
1052	io_write(sd, REG_CFG1, PON_EN);
1053	/* Enable deep color PLL */
1054	io_write(sd, REG_DEEP_PLL7_BYP, PON_DIS);
1055	/* Output buffers active */
1056	reg = io_read(sd, REG_OF);
1057	reg &= ~OF_VP_ENABLE;
1058	io_write(sd, REG_OF, val: reg);
1059	} else {
1060	/* Power down EDID mode sequence */
1061	/* Output buffers in HiZ */
1062	reg = io_read(sd, REG_OF);
1063	reg |= OF_VP_ENABLE;
1064	io_write(sd, REG_OF, val: reg);
1065	/* Disable deep color PLL */
1066	io_write(sd, REG_DEEP_PLL7_BYP, PON_EN);
1067	/* Disable current bias unit */
1068	io_write(sd, REG_CFG1, PON_DIS);
1069	/* Manual control of TMDS */
1070	io_write(sd, REG_PON_OVR_EN, PON_EN);
1071	}
1072	}
1073
1074	static bool
1075	tda1997x_detect_tx_5v(struct v4l2_subdev *sd)
1076	{
1077	u8 reg = io_read(sd, REG_DETECT_5V);
1078
1079	return ((reg & DETECT_5V_SEL) ? 1 : 0);
1080	}
1081
1082	static bool
1083	tda1997x_detect_tx_hpd(struct v4l2_subdev *sd)
1084	{
1085	u8 reg = io_read(sd, REG_DETECT_5V);
1086
1087	return ((reg & DETECT_HPD) ? 1 : 0);
1088	}
1089
1090	static int
1091	tda1997x_detect_std(struct tda1997x_state *state,
1092	struct v4l2_dv_timings *timings)
1093	{
1094	struct v4l2_subdev *sd = &state->sd;
1095
1096	/*
1097	* Read the FMT registers
1098	* REG_V_PER: Period of a frame (or field) in MCLK (27MHz) cycles
1099	* REG_H_PER: Period of a line in MCLK (27MHz) cycles
1100	* REG_HS_WIDTH: Period of horiz sync pulse in MCLK (27MHz) cycles
1101	*/
1102	u32 vper, vsync_pos;
1103	u16 hper, hsync_pos, hsper, interlaced;
1104	u16 htot, hact, hfront, hsync, hback;
1105	u16 vtot, vact, vfront1, vfront2, vsync, vback1, vback2;
1106
1107	if (!state->input_detect[0] && !state->input_detect[1])
1108	return -ENOLINK;
1109
1110	vper = io_read24(sd, REG_V_PER);
1111	hper = io_read16(sd, REG_H_PER);
1112	hsper = io_read16(sd, REG_HS_WIDTH);
1113	vsync_pos = vper & MASK_VPER_SYNC_POS;
1114	hsync_pos = hper & MASK_HPER_SYNC_POS;
1115	interlaced = hsper & MASK_HSWIDTH_INTERLACED;
1116	vper &= MASK_VPER;
1117	hper &= MASK_HPER;
1118	hsper &= MASK_HSWIDTH;
1119	v4l2_dbg(1, debug, sd, "Signal Timings: %u/%u/%u\n", vper, hper, hsper);
1120
1121	htot = io_read16(sd, REG_FMT_H_TOT);
1122	hact = io_read16(sd, REG_FMT_H_ACT);
1123	hfront = io_read16(sd, REG_FMT_H_FRONT);
1124	hsync = io_read16(sd, REG_FMT_H_SYNC);
1125	hback = io_read16(sd, REG_FMT_H_BACK);
1126
1127	vtot = io_read16(sd, REG_FMT_V_TOT);
1128	vact = io_read16(sd, REG_FMT_V_ACT);
1129	vfront1 = io_read(sd, REG_FMT_V_FRONT_F1);
1130	vfront2 = io_read(sd, REG_FMT_V_FRONT_F2);
1131	vsync = io_read(sd, REG_FMT_V_SYNC);
1132	vback1 = io_read(sd, REG_FMT_V_BACK_F1);
1133	vback2 = io_read(sd, REG_FMT_V_BACK_F2);
1134
1135	v4l2_dbg(1, debug, sd, "Geometry: H %u %u %u %u %u Sync%c V %u %u %u %u %u %u %u Sync%c\n",
1136	htot, hact, hfront, hsync, hback, hsync_pos ? '+' : '-',
1137	vtot, vact, vfront1, vfront2, vsync, vback1, vback2, vsync_pos ? '+' : '-');
1138
1139	if (!timings)
1140	return 0;
1141
1142	timings->type = V4L2_DV_BT_656_1120;
1143	timings->bt.width = hact;
1144	timings->bt.hfrontporch = hfront;
1145	timings->bt.hsync = hsync;
1146	timings->bt.hbackporch = hback;
1147	timings->bt.height = vact;
1148	timings->bt.vfrontporch = vfront1;
1149	timings->bt.vsync = vsync;
1150	timings->bt.vbackporch = vback1;
1151	timings->bt.interlaced = interlaced ? V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1152	timings->bt.polarities = vsync_pos ? V4L2_DV_VSYNC_POS_POL : 0;
1153	timings->bt.polarities |= hsync_pos ? V4L2_DV_HSYNC_POS_POL : 0;
1154
1155	timings->bt.pixelclock = (u64)htot * vtot * 27000000;
1156	if (interlaced) {
1157	timings->bt.il_vfrontporch = vfront2;
1158	timings->bt.il_vsync = timings->bt.vsync;
1159	timings->bt.il_vbackporch = vback2;
1160	do_div(timings->bt.pixelclock, vper * 2 /* full frame */);
1161	} else {
1162	timings->bt.il_vfrontporch = 0;
1163	timings->bt.il_vsync = 0;
1164	timings->bt.il_vbackporch = 0;
1165	do_div(timings->bt.pixelclock, vper);
1166	}
1167	v4l2_find_dv_timings_cap(t: timings, cap: &tda1997x_dv_timings_cap,
1168	pclock_delta: (u32)timings->bt.pixelclock / 500, NULL, NULL);
1169	v4l2_print_dv_timings(dev_prefix: sd->name, prefix: "Detected format: ", t: timings, detailed: false);
1170	return 0;
1171	}
1172
1173	/* some sort of errata workaround for chip revision 0 (N1) */
1174	static void tda1997x_reset_n1(struct tda1997x_state *state)
1175	{
1176	struct v4l2_subdev *sd = &state->sd;
1177	u8 reg;
1178
1179	/* clear HDMI mode flag in BCAPS */
1180	io_write(sd, REG_CLK_CFG, CLK_CFG_SEL_ACLK_EN | CLK_CFG_SEL_ACLK);
1181	io_write(sd, REG_PON_OVR_EN, PON_EN);
1182	io_write(sd, REG_PON_CBIAS, PON_EN);
1183	io_write(sd, REG_PON_PLL, PON_EN);
1184
1185	reg = io_read(sd, REG_MODE_REC_CFG1);
1186	reg &= ~0x06;
1187	reg |= 0x02;
1188	io_write(sd, REG_MODE_REC_CFG1, val: reg);
1189	io_write(sd, REG_CLK_CFG, CLK_CFG_DIS);
1190	io_write(sd, REG_PON_OVR_EN, PON_DIS);
1191	reg = io_read(sd, REG_MODE_REC_CFG1);
1192	reg &= ~0x06;
1193	io_write(sd, REG_MODE_REC_CFG1, val: reg);
1194	}
1195
1196	/*
1197	* Activity detection must only be notified when stable_clk_x AND active_x
1198	* bits are set to 1. If only stable_clk_x bit is set to 1 but not
1199	* active_x, it means that the TMDS clock is not in the defined range
1200	* and activity detection must not be notified.
1201	*/
1202	static u8
1203	tda1997x_read_activity_status_regs(struct v4l2_subdev *sd)
1204	{
1205	u8 reg, status = 0;
1206
1207	/* Read CLK_A_STATUS register */
1208	reg = io_read(sd, REG_CLK_A_STATUS);
1209	/* ignore if not active */
1210	if ((reg & MASK_CLK_STABLE) && !(reg & MASK_CLK_ACTIVE))
1211	reg &= ~MASK_CLK_STABLE;
1212	status |= ((reg & MASK_CLK_STABLE) >> 2);
1213
1214	/* Read CLK_B_STATUS register */
1215	reg = io_read(sd, REG_CLK_B_STATUS);
1216	/* ignore if not active */
1217	if ((reg & MASK_CLK_STABLE) && !(reg & MASK_CLK_ACTIVE))
1218	reg &= ~MASK_CLK_STABLE;
1219	status |= ((reg & MASK_CLK_STABLE) >> 1);
1220
1221	/* Read the SUS_STATUS register */
1222	reg = io_read(sd, REG_SUS_STATUS);
1223
1224	/* If state = 5 => TMDS is locked */
1225	if ((reg & MASK_SUS_STATUS) == LAST_STATE_REACHED)
1226	status |= MASK_SUS_STATE;
1227	else
1228	status &= ~MASK_SUS_STATE;
1229
1230	return status;
1231	}
1232
1233	static void
1234	set_rgb_quantization_range(struct tda1997x_state *state)
1235	{
1236	struct v4l2_hdmi_colorimetry *c = &state->colorimetry;
1237
1238	state->colorimetry = v4l2_hdmi_rx_colorimetry(avi: &state->avi_infoframe,
1239	NULL,
1240	height: state->timings.bt.height);
1241	/* If ycbcr_enc is V4L2_YCBCR_ENC_DEFAULT, we receive RGB */
1242	if (c->ycbcr_enc == V4L2_YCBCR_ENC_DEFAULT) {
1243	switch (state->rgb_quantization_range) {
1244	case V4L2_DV_RGB_RANGE_LIMITED:
1245	c->quantization = V4L2_QUANTIZATION_FULL_RANGE;
1246	break;
1247	case V4L2_DV_RGB_RANGE_FULL:
1248	c->quantization = V4L2_QUANTIZATION_LIM_RANGE;
1249	break;
1250	}
1251	}
1252	v4l_dbg(1, debug, state->client,
1253	"colorspace=%d/%d colorimetry=%d range=%s content=%d\n",
1254	state->avi_infoframe.colorspace, c->colorspace,
1255	state->avi_infoframe.colorimetry,
1256	v4l2_quantization_names[c->quantization],
1257	state->avi_infoframe.content_type);
1258	}
1259
1260	/* parse an infoframe and do some sanity checks on it */
1261	static unsigned int
1262	tda1997x_parse_infoframe(struct tda1997x_state *state, u16 addr)
1263	{
1264	struct v4l2_subdev *sd = &state->sd;
1265	union hdmi_infoframe frame;
1266	u8 buffer[40] = { 0 };
1267	u8 reg;
1268	int len, err;
1269
1270	/* read data */
1271	len = io_readn(sd, reg: addr, len: sizeof(buffer), data: buffer);
1272	err = hdmi_infoframe_unpack(frame: &frame, buffer, size: len);
1273	if (err) {
1274	v4l_err(state->client,
1275	"failed parsing %d byte infoframe: 0x%04x/0x%02x\n",
1276	len, addr, buffer[0]);
1277	return err;
1278	}
1279	hdmi_infoframe_log(KERN_INFO, dev: &state->client->dev, frame: &frame);
1280	switch (frame.any.type) {
1281	/* Audio InfoFrame: see HDMI spec 8.2.2 */
1282	case HDMI_INFOFRAME_TYPE_AUDIO:
1283	/* sample rate */
1284	switch (frame.audio.sample_frequency) {
1285	case HDMI_AUDIO_SAMPLE_FREQUENCY_32000:
1286	state->audio_samplerate = 32000;
1287	break;
1288	case HDMI_AUDIO_SAMPLE_FREQUENCY_44100:
1289	state->audio_samplerate = 44100;
1290	break;
1291	case HDMI_AUDIO_SAMPLE_FREQUENCY_48000:
1292	state->audio_samplerate = 48000;
1293	break;
1294	case HDMI_AUDIO_SAMPLE_FREQUENCY_88200:
1295	state->audio_samplerate = 88200;
1296	break;
1297	case HDMI_AUDIO_SAMPLE_FREQUENCY_96000:
1298	state->audio_samplerate = 96000;
1299	break;
1300	case HDMI_AUDIO_SAMPLE_FREQUENCY_176400:
1301	state->audio_samplerate = 176400;
1302	break;
1303	case HDMI_AUDIO_SAMPLE_FREQUENCY_192000:
1304	state->audio_samplerate = 192000;
1305	break;
1306	default:
1307	case HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM:
1308	break;
1309	}
1310
1311	/* sample size */
1312	switch (frame.audio.sample_size) {
1313	case HDMI_AUDIO_SAMPLE_SIZE_16:
1314	state->audio_samplesize = 16;
1315	break;
1316	case HDMI_AUDIO_SAMPLE_SIZE_20:
1317	state->audio_samplesize = 20;
1318	break;
1319	case HDMI_AUDIO_SAMPLE_SIZE_24:
1320	state->audio_samplesize = 24;
1321	break;
1322	case HDMI_AUDIO_SAMPLE_SIZE_STREAM:
1323	default:
1324	break;
1325	}
1326
1327	/* Channel Count */
1328	state->audio_channels = frame.audio.channels;
1329	if (frame.audio.channel_allocation &&
1330	frame.audio.channel_allocation != state->audio_ch_alloc) {
1331	/* use the channel assignment from the infoframe */
1332	state->audio_ch_alloc = frame.audio.channel_allocation;
1333	tda1997x_configure_audout(sd, channel_assignment: state->audio_ch_alloc);
1334	/* reset the audio FIFO */
1335	tda1997x_hdmi_info_reset(sd, RESET_AUDIO, reset_sus: false);
1336	}
1337	break;
1338
1339	/* Auxiliary Video information (AVI) InfoFrame: see HDMI spec 8.2.1 */
1340	case HDMI_INFOFRAME_TYPE_AVI:
1341	state->avi_infoframe = frame.avi;
1342	set_rgb_quantization_range(state);
1343
1344	/* configure upsampler: 0=bypass 1=repeatchroma 2=interpolate */
1345	reg = io_read(sd, REG_PIX_REPEAT);
1346	reg &= ~PIX_REPEAT_MASK_UP_SEL;
1347	if (frame.avi.colorspace == HDMI_COLORSPACE_YUV422)
1348	reg |= (PIX_REPEAT_CHROMA << PIX_REPEAT_SHIFT);
1349	io_write(sd, REG_PIX_REPEAT, val: reg);
1350
1351	/* ConfigurePixelRepeater: repeat n-times each pixel */
1352	reg = io_read(sd, REG_PIX_REPEAT);
1353	reg &= ~PIX_REPEAT_MASK_REP;
1354	reg |= frame.avi.pixel_repeat;
1355	io_write(sd, REG_PIX_REPEAT, val: reg);
1356
1357	/* configure the receiver with the new colorspace */
1358	tda1997x_configure_csc(sd);
1359	break;
1360	default:
1361	break;
1362	}
1363	return 0;
1364	}
1365
1366	static void tda1997x_irq_sus(struct tda1997x_state *state, u8 *flags)
1367	{
1368	struct v4l2_subdev *sd = &state->sd;
1369	u8 reg, source;
1370
1371	source = io_read(sd, REG_INT_FLG_CLR_SUS);
1372	io_write(sd, REG_INT_FLG_CLR_SUS, val: source);
1373
1374	if (source & MASK_MPT) {
1375	/* reset MTP in use flag if set */
1376	if (state->mptrw_in_progress)
1377	state->mptrw_in_progress = 0;
1378	}
1379
1380	if (source & MASK_SUS_END) {
1381	/* reset audio FIFO */
1382	reg = io_read(sd, REG_HDMI_INFO_RST);
1383	reg |= MASK_SR_FIFO_FIFO_CTRL;
1384	io_write(sd, REG_HDMI_INFO_RST, val: reg);
1385	reg &= ~MASK_SR_FIFO_FIFO_CTRL;
1386	io_write(sd, REG_HDMI_INFO_RST, val: reg);
1387
1388	/* reset HDMI flags */
1389	state->hdmi_status = 0;
1390	}
1391
1392	/* filter FMT interrupt based on SUS state */
1393	reg = io_read(sd, REG_SUS_STATUS);
1394	if (((reg & MASK_SUS_STATUS) != LAST_STATE_REACHED)
1395	|| (source & MASK_MPT)) {
1396	source &= ~MASK_FMT;
1397	}
1398
1399	if (source & (MASK_FMT | MASK_SUS_END)) {
1400	reg = io_read(sd, REG_SUS_STATUS);
1401	if ((reg & MASK_SUS_STATUS) != LAST_STATE_REACHED) {
1402	v4l_err(state->client, "BAD SUS STATUS\n");
1403	return;
1404	}
1405	if (debug)
1406	tda1997x_detect_std(state, NULL);
1407	/* notify user of change in resolution */
1408	v4l2_subdev_notify_event(sd: &state->sd, ev: &tda1997x_ev_fmt);
1409	}
1410	}
1411
1412	static void tda1997x_irq_ddc(struct tda1997x_state *state, u8 *flags)
1413	{
1414	struct v4l2_subdev *sd = &state->sd;
1415	u8 source;
1416
1417	source = io_read(sd, REG_INT_FLG_CLR_DDC);
1418	io_write(sd, REG_INT_FLG_CLR_DDC, val: source);
1419	if (source & MASK_EDID_MTP) {
1420	/* reset MTP in use flag if set */
1421	if (state->mptrw_in_progress)
1422	state->mptrw_in_progress = 0;
1423	}
1424
1425	/* Detection of +5V */
1426	if (source & MASK_DET_5V) {
1427	v4l2_ctrl_s_ctrl(ctrl: state->detect_tx_5v_ctrl,
1428	val: tda1997x_detect_tx_5v(sd));
1429	}
1430	}
1431
1432	static void tda1997x_irq_rate(struct tda1997x_state *state, u8 *flags)
1433	{
1434	struct v4l2_subdev *sd = &state->sd;
1435	u8 reg, source;
1436
1437	u8 irq_status;
1438
1439	source = io_read(sd, REG_INT_FLG_CLR_RATE);
1440	io_write(sd, REG_INT_FLG_CLR_RATE, val: source);
1441
1442	/* read status regs */
1443	irq_status = tda1997x_read_activity_status_regs(sd);
1444
1445	/*
1446	* read clock status reg until INT_FLG_CLR_RATE is still 0
1447	* after the read to make sure its the last one
1448	*/
1449	reg = source;
1450	while (reg != 0) {
1451	irq_status = tda1997x_read_activity_status_regs(sd);
1452	reg = io_read(sd, REG_INT_FLG_CLR_RATE);
1453	io_write(sd, REG_INT_FLG_CLR_RATE, val: reg);
1454	source |= reg;
1455	}
1456
1457	/* we only pay attention to stability change events */
1458	if (source & (MASK_RATE_A_ST | MASK_RATE_B_ST)) {
1459	int input = (source & MASK_RATE_A_ST)?0:1;
1460	u8 mask = 1<<input;
1461
1462	/* state change */
1463	if ((irq_status & mask) != (state->activity_status & mask)) {
1464	/* activity lost */
1465	if ((irq_status & mask) == 0) {
1466	v4l_info(state->client,
1467	"HDMI-%c: Digital Activity Lost\n",
1468	input+'A');
1469
1470	/* bypass up/down sampler and pixel repeater */
1471	reg = io_read(sd, REG_PIX_REPEAT);
1472	reg &= ~PIX_REPEAT_MASK_UP_SEL;
1473	reg &= ~PIX_REPEAT_MASK_REP;
1474	io_write(sd, REG_PIX_REPEAT, val: reg);
1475
1476	if (state->chip_revision == 0)
1477	tda1997x_reset_n1(state);
1478
1479	state->input_detect[input] = 0;
1480	v4l2_subdev_notify_event(sd, ev: &tda1997x_ev_fmt);
1481	}
1482
1483	/* activity detected */
1484	else {
1485	v4l_info(state->client,
1486	"HDMI-%c: Digital Activity Detected\n",
1487	input+'A');
1488	state->input_detect[input] = 1;
1489	}
1490
1491	/* hold onto current state */
1492	state->activity_status = (irq_status & mask);
1493	}
1494	}
1495	}
1496
1497	static void tda1997x_irq_info(struct tda1997x_state *state, u8 *flags)
1498	{
1499	struct v4l2_subdev *sd = &state->sd;
1500	u8 source;
1501
1502	source = io_read(sd, REG_INT_FLG_CLR_INFO);
1503	io_write(sd, REG_INT_FLG_CLR_INFO, val: source);
1504
1505	/* Audio infoframe */
1506	if (source & MASK_AUD_IF) {
1507	tda1997x_parse_infoframe(state, AUD_IF);
1508	source &= ~MASK_AUD_IF;
1509	}
1510
1511	/* Source Product Descriptor infoframe change */
1512	if (source & MASK_SPD_IF) {
1513	tda1997x_parse_infoframe(state, SPD_IF);
1514	source &= ~MASK_SPD_IF;
1515	}
1516
1517	/* Auxiliary Video Information infoframe */
1518	if (source & MASK_AVI_IF) {
1519	tda1997x_parse_infoframe(state, AVI_IF);
1520	source &= ~MASK_AVI_IF;
1521	}
1522	}
1523
1524	static void tda1997x_irq_audio(struct tda1997x_state *state, u8 *flags)
1525	{
1526	struct v4l2_subdev *sd = &state->sd;
1527	u8 reg, source;
1528
1529	source = io_read(sd, REG_INT_FLG_CLR_AUDIO);
1530	io_write(sd, REG_INT_FLG_CLR_AUDIO, val: source);
1531
1532	/* reset audio FIFO on FIFO pointer error or audio mute */
1533	if (source & MASK_ERROR_FIFO_PT ||
1534	source & MASK_MUTE_FLG) {
1535	/* audio reset audio FIFO */
1536	reg = io_read(sd, REG_SUS_STATUS);
1537	if ((reg & MASK_SUS_STATUS) == LAST_STATE_REACHED) {
1538	reg = io_read(sd, REG_HDMI_INFO_RST);
1539	reg |= MASK_SR_FIFO_FIFO_CTRL;
1540	io_write(sd, REG_HDMI_INFO_RST, val: reg);
1541	reg &= ~MASK_SR_FIFO_FIFO_CTRL;
1542	io_write(sd, REG_HDMI_INFO_RST, val: reg);
1543	/* reset channel status IT if present */
1544	source &= ~(MASK_CH_STATE);
1545	}
1546	}
1547	if (source & MASK_AUDIO_FREQ_FLG) {
1548	static const int freq[] = {
1549	0, 32000, 44100, 48000, 88200, 96000, 176400, 192000
1550	};
1551
1552	reg = io_read(sd, REG_AUDIO_FREQ);
1553	state->audio_samplerate = freq[reg & 7];
1554	v4l_info(state->client, "Audio Frequency Change: %dHz\n",
1555	state->audio_samplerate);
1556	}
1557	if (source & MASK_AUDIO_FLG) {
1558	reg = io_read(sd, REG_AUDIO_FLAGS);
1559	if (reg & BIT(AUDCFG_TYPE_DST))
1560	state->audio_type = AUDCFG_TYPE_DST;
1561	if (reg & BIT(AUDCFG_TYPE_OBA))
1562	state->audio_type = AUDCFG_TYPE_OBA;
1563	if (reg & BIT(AUDCFG_TYPE_HBR))
1564	state->audio_type = AUDCFG_TYPE_HBR;
1565	if (reg & BIT(AUDCFG_TYPE_PCM))
1566	state->audio_type = AUDCFG_TYPE_PCM;
1567	v4l_info(state->client, "Audio Type: %s\n",
1568	audtype_names[state->audio_type]);
1569	}
1570	}
1571
1572	static void tda1997x_irq_hdcp(struct tda1997x_state *state, u8 *flags)
1573	{
1574	struct v4l2_subdev *sd = &state->sd;
1575	u8 reg, source;
1576
1577	source = io_read(sd, REG_INT_FLG_CLR_HDCP);
1578	io_write(sd, REG_INT_FLG_CLR_HDCP, val: source);
1579
1580	/* reset MTP in use flag if set */
1581	if (source & MASK_HDCP_MTP)
1582	state->mptrw_in_progress = 0;
1583	if (source & MASK_STATE_C5) {
1584	/* REPEATER: mask AUDIO and IF irqs to avoid IF during auth */
1585	reg = io_read(sd, REG_INT_MASK_TOP);
1586	reg &= ~(INTERRUPT_AUDIO | INTERRUPT_INFO);
1587	io_write(sd, REG_INT_MASK_TOP, val: reg);
1588	*flags &= (INTERRUPT_AUDIO | INTERRUPT_INFO);
1589	}
1590	}
1591
1592	static irqreturn_t tda1997x_isr_thread(int irq, void *d)
1593	{
1594	struct tda1997x_state *state = d;
1595	struct v4l2_subdev *sd = &state->sd;
1596	u8 flags;
1597
1598	mutex_lock(&state->lock);
1599	do {
1600	/* read interrupt flags */
1601	flags = io_read(sd, REG_INT_FLG_CLR_TOP);
1602	if (flags == 0)
1603	break;
1604
1605	/* SUS interrupt source (Input activity events) */
1606	if (flags & INTERRUPT_SUS)
1607	tda1997x_irq_sus(state, flags: &flags);
1608	/* DDC interrupt source (Display Data Channel) */
1609	else if (flags & INTERRUPT_DDC)
1610	tda1997x_irq_ddc(state, flags: &flags);
1611	/* RATE interrupt source (Digital Input activity) */
1612	else if (flags & INTERRUPT_RATE)
1613	tda1997x_irq_rate(state, flags: &flags);
1614	/* Infoframe change interrupt */
1615	else if (flags & INTERRUPT_INFO)
1616	tda1997x_irq_info(state, flags: &flags);
1617	/* Audio interrupt source:
1618	* freq change, DST,OBA,HBR,ASP flags, mute, FIFO err
1619	*/
1620	else if (flags & INTERRUPT_AUDIO)
1621	tda1997x_irq_audio(state, flags: &flags);
1622	/* HDCP interrupt source (content protection) */
1623	if (flags & INTERRUPT_HDCP)
1624	tda1997x_irq_hdcp(state, flags: &flags);
1625	} while (flags != 0);
1626	mutex_unlock(lock: &state->lock);
1627
1628	return IRQ_HANDLED;
1629	}
1630
1631	/* -----------------------------------------------------------------------------
1632	* v4l2_subdev_video_ops
1633	*/
1634
1635	static int
1636	tda1997x_g_input_status(struct v4l2_subdev *sd, u32 *status)
1637	{
1638	struct tda1997x_state *state = to_state(sd);
1639	u32 vper;
1640	u16 hper;
1641	u16 hsper;
1642
1643	mutex_lock(&state->lock);
1644	vper = io_read24(sd, REG_V_PER) & MASK_VPER;
1645	hper = io_read16(sd, REG_H_PER) & MASK_HPER;
1646	hsper = io_read16(sd, REG_HS_WIDTH) & MASK_HSWIDTH;
1647	/*
1648	* The tda1997x supports A/B inputs but only a single output.
1649	* The irq handler monitors for timing changes on both inputs and
1650	* sets the input_detect array to 0|1 depending on signal presence.
1651	* I believe selection of A vs B is automatic.
1652	*
1653	* The vper/hper/hsper registers provide the frame period, line period
1654	* and horiz sync period (units of MCLK clock cycles (27MHz)) and
1655	* testing shows these values to be random if no signal is present
1656	* or locked.
1657	*/
1658	v4l2_dbg(1, debug, sd, "inputs:%d/%d timings:%d/%d/%d\n",
1659	state->input_detect[0], state->input_detect[1],
1660	vper, hper, hsper);
1661	if (!state->input_detect[0] && !state->input_detect[1])
1662	*status = V4L2_IN_ST_NO_SIGNAL;
1663	else if (!vper || !hper || !hsper)
1664	*status = V4L2_IN_ST_NO_SYNC;
1665	else
1666	*status = 0;
1667	mutex_unlock(lock: &state->lock);
1668
1669	return 0;
1670	};
1671
1672	static int tda1997x_s_dv_timings(struct v4l2_subdev *sd,
1673	struct v4l2_dv_timings *timings)
1674	{
1675	struct tda1997x_state *state = to_state(sd);
1676
1677	v4l_dbg(1, debug, state->client, "%s\n", __func__);
1678
1679	if (v4l2_match_dv_timings(measured: &state->timings, standard: timings, pclock_delta: 0, match_reduced_fps: false))
1680	return 0; /* no changes */
1681
1682	if (!v4l2_valid_dv_timings(t: timings, cap: &tda1997x_dv_timings_cap,
1683	NULL, NULL))
1684	return -ERANGE;
1685
1686	mutex_lock(&state->lock);
1687	state->timings = *timings;
1688	/* setup frame detection window and VHREF timing generator */
1689	tda1997x_configure_vhref(sd);
1690	/* configure colorspace conversion */
1691	tda1997x_configure_csc(sd);
1692	mutex_unlock(lock: &state->lock);
1693
1694	return 0;
1695	}
1696
1697	static int tda1997x_g_dv_timings(struct v4l2_subdev *sd,
1698	struct v4l2_dv_timings *timings)
1699	{
1700	struct tda1997x_state *state = to_state(sd);
1701
1702	v4l_dbg(1, debug, state->client, "%s\n", __func__);
1703	mutex_lock(&state->lock);
1704	*timings = state->timings;
1705	mutex_unlock(lock: &state->lock);
1706
1707	return 0;
1708	}
1709
1710	static int tda1997x_query_dv_timings(struct v4l2_subdev *sd,
1711	struct v4l2_dv_timings *timings)
1712	{
1713	struct tda1997x_state *state = to_state(sd);
1714	int ret;
1715
1716	v4l_dbg(1, debug, state->client, "%s\n", __func__);
1717	memset(timings, 0, sizeof(struct v4l2_dv_timings));
1718	mutex_lock(&state->lock);
1719	ret = tda1997x_detect_std(state, timings);
1720	mutex_unlock(lock: &state->lock);
1721
1722	return ret;
1723	}
1724
1725	static const struct v4l2_subdev_video_ops tda1997x_video_ops = {
1726	.g_input_status = tda1997x_g_input_status,
1727	.s_dv_timings = tda1997x_s_dv_timings,
1728	.g_dv_timings = tda1997x_g_dv_timings,
1729	.query_dv_timings = tda1997x_query_dv_timings,
1730	};
1731
1732
1733	/* -----------------------------------------------------------------------------
1734	* v4l2_subdev_pad_ops
1735	*/
1736
1737	static int tda1997x_init_state(struct v4l2_subdev *sd,
1738	struct v4l2_subdev_state *sd_state)
1739	{
1740	struct tda1997x_state *state = to_state(sd);
1741	struct v4l2_mbus_framefmt *mf;
1742
1743	mf = v4l2_subdev_state_get_format(sd_state, 0);
1744	mf->code = state->mbus_codes[0];
1745
1746	return 0;
1747	}
1748
1749	static int tda1997x_enum_mbus_code(struct v4l2_subdev *sd,
1750	struct v4l2_subdev_state *sd_state,
1751	struct v4l2_subdev_mbus_code_enum *code)
1752	{
1753	struct tda1997x_state *state = to_state(sd);
1754
1755	v4l_dbg(1, debug, state->client, "%s %d\n", __func__, code->index);
1756	if (code->index >= ARRAY_SIZE(state->mbus_codes))
1757	return -EINVAL;
1758
1759	if (!state->mbus_codes[code->index])
1760	return -EINVAL;
1761
1762	code->code = state->mbus_codes[code->index];
1763
1764	return 0;
1765	}
1766
1767	static void tda1997x_fill_format(struct tda1997x_state *state,
1768	struct v4l2_mbus_framefmt *format)
1769	{
1770	const struct v4l2_bt_timings *bt;
1771
1772	memset(format, 0, sizeof(*format));
1773	bt = &state->timings.bt;
1774	format->width = bt->width;
1775	format->height = bt->height;
1776	format->colorspace = state->colorimetry.colorspace;
1777	format->field = (bt->interlaced) ?
1778	V4L2_FIELD_SEQ_TB : V4L2_FIELD_NONE;
1779	}
1780
1781	static int tda1997x_get_format(struct v4l2_subdev *sd,
1782	struct v4l2_subdev_state *sd_state,
1783	struct v4l2_subdev_format *format)
1784	{
1785	struct tda1997x_state *state = to_state(sd);
1786
1787	v4l_dbg(1, debug, state->client, "%s pad=%d which=%d\n",
1788	__func__, format->pad, format->which);
1789
1790	tda1997x_fill_format(state, format: &format->format);
1791
1792	if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1793	struct v4l2_mbus_framefmt *fmt;
1794
1795	fmt = v4l2_subdev_state_get_format(sd_state, format->pad);
1796	format->format.code = fmt->code;
1797	} else
1798	format->format.code = state->mbus_code;
1799
1800	return 0;
1801	}
1802
1803	static int tda1997x_set_format(struct v4l2_subdev *sd,
1804	struct v4l2_subdev_state *sd_state,
1805	struct v4l2_subdev_format *format)
1806	{
1807	struct tda1997x_state *state = to_state(sd);
1808	u32 code = 0;
1809	int i;
1810
1811	v4l_dbg(1, debug, state->client, "%s pad=%d which=%d fmt=0x%x\n",
1812	__func__, format->pad, format->which, format->format.code);
1813
1814	for (i = 0; i < ARRAY_SIZE(state->mbus_codes); i++) {
1815	if (format->format.code == state->mbus_codes[i]) {
1816	code = state->mbus_codes[i];
1817	break;
1818	}
1819	}
1820	if (!code)
1821	code = state->mbus_codes[0];
1822
1823	tda1997x_fill_format(state, format: &format->format);
1824	format->format.code = code;
1825
1826	if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1827	struct v4l2_mbus_framefmt *fmt;
1828
1829	fmt = v4l2_subdev_state_get_format(sd_state, format->pad);
1830	*fmt = format->format;
1831	} else {
1832	int ret = tda1997x_setup_format(state, code: format->format.code);
1833
1834	if (ret)
1835	return ret;
1836	/* mbus_code has changed - re-configure csc/vidout */
1837	tda1997x_configure_csc(sd);
1838	tda1997x_configure_vidout(state);
1839	}
1840
1841	return 0;
1842	}
1843
1844	static int tda1997x_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
1845	{
1846	struct tda1997x_state *state = to_state(sd);
1847
1848	v4l_dbg(1, debug, state->client, "%s pad=%d\n", __func__, edid->pad);
1849	memset(edid->reserved, 0, sizeof(edid->reserved));
1850
1851	if (edid->start_block == 0 && edid->blocks == 0) {
1852	edid->blocks = state->edid.blocks;
1853	return 0;
1854	}
1855
1856	if (!state->edid.present)
1857	return -ENODATA;
1858
1859	if (edid->start_block >= state->edid.blocks)
1860	return -EINVAL;
1861
1862	if (edid->start_block + edid->blocks > state->edid.blocks)
1863	edid->blocks = state->edid.blocks - edid->start_block;
1864
1865	memcpy(edid->edid, state->edid.edid + edid->start_block * 128,
1866	edid->blocks * 128);
1867
1868	return 0;
1869	}
1870
1871	static int tda1997x_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
1872	{
1873	struct tda1997x_state *state = to_state(sd);
1874	int i;
1875
1876	v4l_dbg(1, debug, state->client, "%s pad=%d\n", __func__, edid->pad);
1877	memset(edid->reserved, 0, sizeof(edid->reserved));
1878
1879	if (edid->start_block != 0)
1880	return -EINVAL;
1881
1882	if (edid->blocks == 0) {
1883	state->edid.blocks = 0;
1884	state->edid.present = 0;
1885	tda1997x_disable_edid(sd);
1886	return 0;
1887	}
1888
1889	if (edid->blocks > 2) {
1890	edid->blocks = 2;
1891	return -E2BIG;
1892	}
1893
1894	tda1997x_disable_edid(sd);
1895
1896	/* write base EDID */
1897	for (i = 0; i < 128; i++)
1898	io_write(sd, REG_EDID_IN_BYTE0 + i, val: edid->edid[i]);
1899
1900	/* write CEA Extension */
1901	for (i = 0; i < 128; i++)
1902	io_write(sd, REG_EDID_IN_BYTE128 + i, val: edid->edid[i+128]);
1903
1904	/* store state */
1905	memcpy(state->edid.edid, edid->edid, 256);
1906	state->edid.blocks = edid->blocks;
1907
1908	tda1997x_enable_edid(sd);
1909
1910	return 0;
1911	}
1912
1913	static int tda1997x_get_dv_timings_cap(struct v4l2_subdev *sd,
1914	struct v4l2_dv_timings_cap *cap)
1915	{
1916	*cap = tda1997x_dv_timings_cap;
1917	return 0;
1918	}
1919
1920	static int tda1997x_enum_dv_timings(struct v4l2_subdev *sd,
1921	struct v4l2_enum_dv_timings *timings)
1922	{
1923	return v4l2_enum_dv_timings_cap(t: timings, cap: &tda1997x_dv_timings_cap,
1924	NULL, NULL);
1925	}
1926
1927	static const struct v4l2_subdev_pad_ops tda1997x_pad_ops = {
1928	.enum_mbus_code = tda1997x_enum_mbus_code,
1929	.get_fmt = tda1997x_get_format,
1930	.set_fmt = tda1997x_set_format,
1931	.get_edid = tda1997x_get_edid,
1932	.set_edid = tda1997x_set_edid,
1933	.dv_timings_cap = tda1997x_get_dv_timings_cap,
1934	.enum_dv_timings = tda1997x_enum_dv_timings,
1935	};
1936
1937	/* -----------------------------------------------------------------------------
1938	* v4l2_subdev_core_ops
1939	*/
1940
1941	static int tda1997x_log_infoframe(struct v4l2_subdev *sd, int addr)
1942	{
1943	struct tda1997x_state *state = to_state(sd);
1944	union hdmi_infoframe frame;
1945	u8 buffer[40] = { 0 };
1946	int len, err;
1947
1948	/* read data */
1949	len = io_readn(sd, reg: addr, len: sizeof(buffer), data: buffer);
1950	v4l2_dbg(1, debug, sd, "infoframe: addr=%d len=%d\n", addr, len);
1951	err = hdmi_infoframe_unpack(frame: &frame, buffer, size: len);
1952	if (err) {
1953	v4l_err(state->client,
1954	"failed parsing %d byte infoframe: 0x%04x/0x%02x\n",
1955	len, addr, buffer[0]);
1956	return err;
1957	}
1958	hdmi_infoframe_log(KERN_INFO, dev: &state->client->dev, frame: &frame);
1959
1960	return 0;
1961	}
1962
1963	static int tda1997x_log_status(struct v4l2_subdev *sd)
1964	{
1965	struct tda1997x_state *state = to_state(sd);
1966	struct v4l2_dv_timings timings;
1967	struct hdmi_avi_infoframe *avi = &state->avi_infoframe;
1968
1969	v4l2_info(sd, "-----Chip status-----\n");
1970	v4l2_info(sd, "Chip: %s N%d\n", state->info->name,
1971	state->chip_revision + 1);
1972	v4l2_info(sd, "EDID Enabled: %s\n", state->edid.present ? "yes" : "no");
1973
1974	v4l2_info(sd, "-----Signal status-----\n");
1975	v4l2_info(sd, "Cable detected (+5V power): %s\n",
1976	tda1997x_detect_tx_5v(sd) ? "yes" : "no");
1977	v4l2_info(sd, "HPD detected: %s\n",
1978	tda1997x_detect_tx_hpd(sd) ? "yes" : "no");
1979
1980	v4l2_info(sd, "-----Video Timings-----\n");
1981	switch (tda1997x_detect_std(state, timings: &timings)) {
1982	case -ENOLINK:
1983	v4l2_info(sd, "No video detected\n");
1984	break;
1985	case -ERANGE:
1986	v4l2_info(sd, "Invalid signal detected\n");
1987	break;
1988	}
1989	v4l2_print_dv_timings(dev_prefix: sd->name, prefix: "Configured format: ",
1990	t: &state->timings, detailed: true);
1991
1992	v4l2_info(sd, "-----Color space-----\n");
1993	v4l2_info(sd, "Input color space: %s %s %s",
1994	hdmi_colorspace_names[avi->colorspace],
1995	(avi->colorspace == HDMI_COLORSPACE_RGB) ? "" :
1996	hdmi_colorimetry_names[avi->colorimetry],
1997	v4l2_quantization_names[state->colorimetry.quantization]);
1998	v4l2_info(sd, "Output color space: %s",
1999	vidfmt_names[state->vid_fmt]);
2000	v4l2_info(sd, "Color space conversion: %s", state->conv ?
2001	state->conv->name : "None");
2002
2003	v4l2_info(sd, "-----Audio-----\n");
2004	if (state->audio_channels) {
2005	v4l2_info(sd, "audio: %dch %dHz\n", state->audio_channels,
2006	state->audio_samplerate);
2007	} else {
2008	v4l2_info(sd, "audio: none\n");
2009	}
2010
2011	v4l2_info(sd, "-----Infoframes-----\n");
2012	tda1997x_log_infoframe(sd, AUD_IF);
2013	tda1997x_log_infoframe(sd, SPD_IF);
2014	tda1997x_log_infoframe(sd, AVI_IF);
2015
2016	return 0;
2017	}
2018
2019	static int tda1997x_subscribe_event(struct v4l2_subdev *sd,
2020	struct v4l2_fh *fh,
2021	struct v4l2_event_subscription *sub)
2022	{
2023	switch (sub->type) {
2024	case V4L2_EVENT_SOURCE_CHANGE:
2025	return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
2026	case V4L2_EVENT_CTRL:
2027	return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
2028	default:
2029	return -EINVAL;
2030	}
2031	}
2032
2033	static const struct v4l2_subdev_core_ops tda1997x_core_ops = {
2034	.log_status = tda1997x_log_status,
2035	.subscribe_event = tda1997x_subscribe_event,
2036	.unsubscribe_event = v4l2_event_subdev_unsubscribe,
2037	};
2038
2039	/* -----------------------------------------------------------------------------
2040	* v4l2_subdev_ops
2041	*/
2042
2043	static const struct v4l2_subdev_ops tda1997x_subdev_ops = {
2044	.core = &tda1997x_core_ops,
2045	.video = &tda1997x_video_ops,
2046	.pad = &tda1997x_pad_ops,
2047	};
2048
2049	static const struct v4l2_subdev_internal_ops tda1997x_internal_ops = {
2050	.init_state = tda1997x_init_state,
2051	};
2052
2053	/* -----------------------------------------------------------------------------
2054	* v4l2_controls
2055	*/
2056
2057	static int tda1997x_s_ctrl(struct v4l2_ctrl *ctrl)
2058	{
2059	struct v4l2_subdev *sd = to_sd(ctrl);
2060	struct tda1997x_state *state = to_state(sd);
2061
2062	switch (ctrl->id) {
2063	/* allow overriding the default RGB quantization range */
2064	case V4L2_CID_DV_RX_RGB_RANGE:
2065	state->rgb_quantization_range = ctrl->val;
2066	set_rgb_quantization_range(state);
2067	tda1997x_configure_csc(sd);
2068	return 0;
2069	}
2070
2071	return -EINVAL;
2072	};
2073
2074	static int tda1997x_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
2075	{
2076	struct v4l2_subdev *sd = to_sd(ctrl);
2077	struct tda1997x_state *state = to_state(sd);
2078
2079	if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) {
2080	ctrl->val = state->avi_infoframe.content_type;
2081	return 0;
2082	}
2083	return -EINVAL;
2084	};
2085
2086	static const struct v4l2_ctrl_ops tda1997x_ctrl_ops = {
2087	.s_ctrl = tda1997x_s_ctrl,
2088	.g_volatile_ctrl = tda1997x_g_volatile_ctrl,
2089	};
2090
2091	static int tda1997x_core_init(struct v4l2_subdev *sd)
2092	{
2093	struct tda1997x_state *state = to_state(sd);
2094	struct tda1997x_platform_data *pdata = &state->pdata;
2095	u8 reg;
2096	int i;
2097
2098	/* disable HPD */
2099	io_write(sd, REG_HPD_AUTO_CTRL, HPD_AUTO_HPD_UNSEL);
2100	if (state->chip_revision == 0) {
2101	io_write(sd, REG_MAN_SUS_HDMI_SEL, MAN_DIS_HDCP | MAN_RST_HDCP);
2102	io_write(sd, REG_CGU_DBG_SEL, val: 1 << CGU_DBG_CLK_SEL_SHIFT);
2103	}
2104
2105	/* reset infoframe at end of start-up-sequencer */
2106	io_write(sd, REG_SUS_SET_RGB2, val: 0x06);
2107	io_write(sd, REG_SUS_SET_RGB3, val: 0x06);
2108
2109	/* Enable TMDS pull-ups */
2110	io_write(sd, REG_RT_MAN_CTRL, RT_MAN_CTRL_RT |
2111	RT_MAN_CTRL_RT_B | RT_MAN_CTRL_RT_A);
2112
2113	/* enable sync measurement timing */
2114	tda1997x_cec_write(sd, REG_PWR_CONTROL & 0xff, val: 0x04);
2115	/* adjust CEC clock divider */
2116	tda1997x_cec_write(sd, REG_OSC_DIVIDER & 0xff, val: 0x03);
2117	tda1997x_cec_write(sd, REG_EN_OSC_PERIOD_LSB & 0xff, val: 0xa0);
2118	io_write(sd, REG_TIMER_D, val: 0x54);
2119	/* enable power switch */
2120	reg = tda1997x_cec_read(sd, REG_CONTROL & 0xff);
2121	reg |= 0x20;
2122	tda1997x_cec_write(sd, REG_CONTROL & 0xff, val: reg);
2123	mdelay(50);
2124
2125	/* read the chip version */
2126	reg = io_read(sd, REG_VERSION);
2127	/* get the chip configuration */
2128	reg = io_read(sd, REG_CMTP_REG10);
2129
2130	/* enable interrupts we care about */
2131	io_write(sd, REG_INT_MASK_TOP,
2132	INTERRUPT_HDCP | INTERRUPT_AUDIO | INTERRUPT_INFO |
2133	INTERRUPT_RATE | INTERRUPT_SUS);
2134	/* config_mtp,fmt,sus_end,sus_st */
2135	io_write(sd, REG_INT_MASK_SUS, MASK_MPT | MASK_FMT | MASK_SUS_END);
2136	/* rate stability change for inputs A/B */
2137	io_write(sd, REG_INT_MASK_RATE, MASK_RATE_B_ST | MASK_RATE_A_ST);
2138	/* aud,spd,avi*/
2139	io_write(sd, REG_INT_MASK_INFO,
2140	MASK_AUD_IF | MASK_SPD_IF | MASK_AVI_IF);
2141	/* audio_freq,audio_flg,mute_flg,fifo_err */
2142	io_write(sd, REG_INT_MASK_AUDIO,
2143	MASK_AUDIO_FREQ_FLG | MASK_AUDIO_FLG | MASK_MUTE_FLG |
2144	MASK_ERROR_FIFO_PT);
2145	/* HDCP C5 state reached */
2146	io_write(sd, REG_INT_MASK_HDCP, MASK_STATE_C5);
2147	/* 5V detect and HDP pulse end */
2148	io_write(sd, REG_INT_MASK_DDC, MASK_DET_5V);
2149	/* don't care about AFE/MODE */
2150	io_write(sd, REG_INT_MASK_AFE, val: 0);
2151	io_write(sd, REG_INT_MASK_MODE, val: 0);
2152
2153	/* clear all interrupts */
2154	io_write(sd, REG_INT_FLG_CLR_TOP, val: 0xff);
2155	io_write(sd, REG_INT_FLG_CLR_SUS, val: 0xff);
2156	io_write(sd, REG_INT_FLG_CLR_DDC, val: 0xff);
2157	io_write(sd, REG_INT_FLG_CLR_RATE, val: 0xff);
2158	io_write(sd, REG_INT_FLG_CLR_MODE, val: 0xff);
2159	io_write(sd, REG_INT_FLG_CLR_INFO, val: 0xff);
2160	io_write(sd, REG_INT_FLG_CLR_AUDIO, val: 0xff);
2161	io_write(sd, REG_INT_FLG_CLR_HDCP, val: 0xff);
2162	io_write(sd, REG_INT_FLG_CLR_AFE, val: 0xff);
2163
2164	/* init TMDS equalizer */
2165	if (state->chip_revision == 0)
2166	io_write(sd, REG_CGU_DBG_SEL, val: 1 << CGU_DBG_CLK_SEL_SHIFT);
2167	io_write24(sd, REG_CLK_MIN_RATE, CLK_MIN_RATE);
2168	io_write24(sd, REG_CLK_MAX_RATE, CLK_MAX_RATE);
2169	if (state->chip_revision == 0)
2170	io_write(sd, REG_WDL_CFG, WDL_CFG_VAL);
2171	/* DC filter */
2172	io_write(sd, REG_DEEP_COLOR_CTRL, DC_FILTER_VAL);
2173	/* disable test pattern */
2174	io_write(sd, REG_SVC_MODE, val: 0x00);
2175	/* update HDMI INFO CTRL */
2176	io_write(sd, REG_INFO_CTRL, val: 0xff);
2177	/* write HDMI INFO EXCEED value */
2178	io_write(sd, REG_INFO_EXCEED, val: 3);
2179
2180	if (state->chip_revision == 0)
2181	tda1997x_reset_n1(state);
2182
2183	/*
2184	* No HDCP acknowledge when HDCP is disabled
2185	* and reset SUS to force format detection
2186	*/
2187	tda1997x_hdmi_info_reset(sd, NACK_HDCP, reset_sus: true);
2188
2189	/* Set HPD low */
2190	tda1997x_manual_hpd(sd, mode: HPD_LOW_BP);
2191
2192	/* Configure receiver capabilities */
2193	io_write(sd, REG_HDCP_BCAPS, HDCP_HDMI | HDCP_FAST_REAUTH);
2194
2195	/* Configure HDMI: Auto HDCP mode, packet controlled mute */
2196	reg = HDMI_CTRL_MUTE_AUTO << HDMI_CTRL_MUTE_SHIFT;
2197	reg |= HDMI_CTRL_HDCP_AUTO << HDMI_CTRL_HDCP_SHIFT;
2198	io_write(sd, REG_HDMI_CTRL, val: reg);
2199
2200	/* reset start-up-sequencer to force format detection */
2201	tda1997x_hdmi_info_reset(sd, info_rst: 0, reset_sus: true);
2202
2203	/* disable matrix conversion */
2204	reg = io_read(sd, REG_VDP_CTRL);
2205	reg |= VDP_CTRL_MATRIX_BP;
2206	io_write(sd, REG_VDP_CTRL, val: reg);
2207
2208	/* set video output mode */
2209	tda1997x_configure_vidout(state);
2210
2211	/* configure video output port */
2212	for (i = 0; i < 9; i++) {
2213	v4l_dbg(1, debug, state->client, "vidout_cfg[%d]=0x%02x\n", i,
2214	pdata->vidout_port_cfg[i]);
2215	io_write(sd, REG_VP35_32_CTRL + i, val: pdata->vidout_port_cfg[i]);
2216	}
2217
2218	/* configure audio output port */
2219	tda1997x_configure_audout(sd, channel_assignment: 0);
2220
2221	/* configure audio clock freq */
2222	switch (pdata->audout_mclk_fs) {
2223	case 512:
2224	reg = AUDIO_CLOCK_SEL_512FS;
2225	break;
2226	case 256:
2227	reg = AUDIO_CLOCK_SEL_256FS;
2228	break;
2229	case 128:
2230	reg = AUDIO_CLOCK_SEL_128FS;
2231	break;
2232	case 64:
2233	reg = AUDIO_CLOCK_SEL_64FS;
2234	break;
2235	case 32:
2236	reg = AUDIO_CLOCK_SEL_32FS;
2237	break;
2238	default:
2239	reg = AUDIO_CLOCK_SEL_16FS;
2240	break;
2241	}
2242	io_write(sd, REG_AUDIO_CLOCK, val: reg);
2243
2244	/* reset advanced infoframes (ISRC1/ISRC2/ACP) */
2245	tda1997x_hdmi_info_reset(sd, RESET_AI, reset_sus: false);
2246	/* reset infoframe */
2247	tda1997x_hdmi_info_reset(sd, RESET_IF, reset_sus: false);
2248	/* reset audio infoframes */
2249	tda1997x_hdmi_info_reset(sd, RESET_AUDIO, reset_sus: false);
2250	/* reset gamut */
2251	tda1997x_hdmi_info_reset(sd, RESET_GAMUT, reset_sus: false);
2252
2253	/* get initial HDMI status */
2254	state->hdmi_status = io_read(sd, REG_HDMI_FLAGS);
2255
2256	io_write(sd, REG_EDID_ENABLE, EDID_ENABLE_A_EN | EDID_ENABLE_B_EN);
2257	return 0;
2258	}
2259
2260	static int tda1997x_set_power(struct tda1997x_state *state, bool on)
2261	{
2262	int ret = 0;
2263
2264	if (on) {
2265	ret = regulator_bulk_enable(TDA1997X_NUM_SUPPLIES,
2266	consumers: state->supplies);
2267	msleep(msecs: 300);
2268	} else {
2269	ret = regulator_bulk_disable(TDA1997X_NUM_SUPPLIES,
2270	consumers: state->supplies);
2271	}
2272
2273	return ret;
2274	}
2275
2276	static const struct i2c_device_id tda1997x_i2c_id[] = {
2277	{"tda19971", (kernel_ulong_t)&tda1997x_chip_info[TDA19971]},
2278	{"tda19973", (kernel_ulong_t)&tda1997x_chip_info[TDA19973]},
2279	{ },
2280	};
2281	MODULE_DEVICE_TABLE(i2c, tda1997x_i2c_id);
2282
2283	static const struct of_device_id tda1997x_of_id[] __maybe_unused = {
2284	{ .compatible = "nxp,tda19971", .data = &tda1997x_chip_info[TDA19971] },
2285	{ .compatible = "nxp,tda19973", .data = &tda1997x_chip_info[TDA19973] },
2286	{ },
2287	};
2288	MODULE_DEVICE_TABLE(of, tda1997x_of_id);
2289
2290	static int tda1997x_parse_dt(struct tda1997x_state *state)
2291	{
2292	struct tda1997x_platform_data *pdata = &state->pdata;
2293	struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 };
2294	struct device_node *ep;
2295	struct device_node *np;
2296	unsigned int flags;
2297	const char *str;
2298	int ret;
2299	u32 v;
2300
2301	/*
2302	* setup default values:
2303	* - HREF: active high from start to end of row
2304	* - VS: Vertical Sync active high at beginning of frame
2305	* - DE: Active high when data valid
2306	* - A_CLK: 128*Fs
2307	*/
2308	pdata->vidout_sel_hs = HS_HREF_SEL_HREF_VHREF;
2309	pdata->vidout_sel_vs = VS_VREF_SEL_VREF_HDMI;
2310	pdata->vidout_sel_de = DE_FREF_SEL_DE_VHREF;
2311
2312	np = state->client->dev.of_node;
2313	ep = of_graph_get_endpoint_by_regs(parent: np, port_reg: 0, reg: -1);
2314	if (!ep)
2315	return -EINVAL;
2316
2317	ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep), vep: &bus_cfg);
2318	if (ret) {
2319	of_node_put(node: ep);
2320	return ret;
2321	}
2322	of_node_put(node: ep);
2323	pdata->vidout_bus_type = bus_cfg.bus_type;
2324
2325	/* polarity of HS/VS/DE */
2326	flags = bus_cfg.bus.parallel.flags;
2327	if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
2328	pdata->vidout_inv_hs = 1;
2329	if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
2330	pdata->vidout_inv_vs = 1;
2331	if (flags & V4L2_MBUS_DATA_ACTIVE_LOW)
2332	pdata->vidout_inv_de = 1;
2333	pdata->vidout_bus_width = bus_cfg.bus.parallel.bus_width;
2334
2335	/* video output port config */
2336	ret = of_property_count_u32_elems(np, propname: "nxp,vidout-portcfg");
2337	if (ret > 0) {
2338	u32 reg, val, i;
2339
2340	for (i = 0; i < ret / 2 && i < 9; i++) {
2341	of_property_read_u32_index(np, propname: "nxp,vidout-portcfg",
2342	index: i * 2, out_value: &reg);
2343	of_property_read_u32_index(np, propname: "nxp,vidout-portcfg",
2344	index: i * 2 + 1, out_value: &val);
2345	if (reg < 9)
2346	pdata->vidout_port_cfg[reg] = val;
2347	}
2348	} else {
2349	v4l_err(state->client, "nxp,vidout-portcfg missing\n");
2350	return -EINVAL;
2351	}
2352
2353	/* default to channel layout dictated by packet header */
2354	pdata->audout_layoutauto = true;
2355
2356	pdata->audout_format = AUDFMT_TYPE_DISABLED;
2357	if (!of_property_read_string(np, propname: "nxp,audout-format", out_string: &str)) {
2358	if (strcmp(str, "i2s") == 0)
2359	pdata->audout_format = AUDFMT_TYPE_I2S;
2360	else if (strcmp(str, "spdif") == 0)
2361	pdata->audout_format = AUDFMT_TYPE_SPDIF;
2362	else {
2363	v4l_err(state->client, "nxp,audout-format invalid\n");
2364	return -EINVAL;
2365	}
2366	if (!of_property_read_u32(np, propname: "nxp,audout-layout", out_value: &v)) {
2367	switch (v) {
2368	case 0:
2369	case 1:
2370	break;
2371	default:
2372	v4l_err(state->client,
2373	"nxp,audout-layout invalid\n");
2374	return -EINVAL;
2375	}
2376	pdata->audout_layout = v;
2377	}
2378	if (!of_property_read_u32(np, propname: "nxp,audout-width", out_value: &v)) {
2379	switch (v) {
2380	case 16:
2381	case 32:
2382	break;
2383	default:
2384	v4l_err(state->client,
2385	"nxp,audout-width invalid\n");
2386	return -EINVAL;
2387	}
2388	pdata->audout_width = v;
2389	}
2390	if (!of_property_read_u32(np, propname: "nxp,audout-mclk-fs", out_value: &v)) {
2391	switch (v) {
2392	case 512:
2393	case 256:
2394	case 128:
2395	case 64:
2396	case 32:
2397	case 16:
2398	break;
2399	default:
2400	v4l_err(state->client,
2401	"nxp,audout-mclk-fs invalid\n");
2402	return -EINVAL;
2403	}
2404	pdata->audout_mclk_fs = v;
2405	}
2406	}
2407
2408	return 0;
2409	}
2410
2411	static int tda1997x_get_regulators(struct tda1997x_state *state)
2412	{
2413	int i;
2414
2415	for (i = 0; i < TDA1997X_NUM_SUPPLIES; i++)
2416	state->supplies[i].supply = tda1997x_supply_name[i];
2417
2418	return devm_regulator_bulk_get(dev: &state->client->dev,
2419	TDA1997X_NUM_SUPPLIES,
2420	consumers: state->supplies);
2421	}
2422
2423	static int tda1997x_identify_module(struct tda1997x_state *state)
2424	{
2425	struct v4l2_subdev *sd = &state->sd;
2426	enum tda1997x_type type;
2427	u8 reg;
2428
2429	/* Read chip configuration*/
2430	reg = io_read(sd, REG_CMTP_REG10);
2431	state->tmdsb_clk = (reg >> 6) & 0x01; /* use tmds clock B_inv for B */
2432	state->tmdsb_soc = (reg >> 5) & 0x01; /* tmds of input B */
2433	state->port_30bit = (reg >> 2) & 0x03; /* 30bit vs 24bit */
2434	state->output_2p5 = (reg >> 1) & 0x01; /* output supply 2.5v */
2435	switch ((reg >> 4) & 0x03) {
2436	case 0x00:
2437	type = TDA19971;
2438	break;
2439	case 0x02:
2440	case 0x03:
2441	type = TDA19973;
2442	break;
2443	default:
2444	dev_err(&state->client->dev, "unsupported chip ID\n");
2445	return -EIO;
2446	}
2447	if (state->info->type != type) {
2448	dev_err(&state->client->dev, "chip id mismatch\n");
2449	return -EIO;
2450	}
2451
2452	/* read chip revision */
2453	state->chip_revision = io_read(sd, REG_CMTP_REG11);
2454
2455	return 0;
2456	}
2457
2458	static const struct media_entity_operations tda1997x_media_ops = {
2459	.link_validate = v4l2_subdev_link_validate,
2460	};
2461
2462
2463	/* -----------------------------------------------------------------------------
2464	* HDMI Audio Codec
2465	*/
2466
2467	/* refine sample-rate based on HDMI source */
2468	static int tda1997x_pcm_startup(struct snd_pcm_substream *substream,
2469	struct snd_soc_dai *dai)
2470	{
2471	struct v4l2_subdev *sd = snd_soc_dai_get_drvdata(dai);
2472	struct tda1997x_state *state = to_state(sd);
2473	struct snd_soc_component *component = dai->component;
2474	struct snd_pcm_runtime *rtd = substream->runtime;
2475	int rate, err;
2476
2477	rate = state->audio_samplerate;
2478	err = snd_pcm_hw_constraint_minmax(runtime: rtd, SNDRV_PCM_HW_PARAM_RATE,
2479	min: rate, max: rate);
2480	if (err < 0) {
2481	dev_err(component->dev, "failed to constrain samplerate to %dHz\n",
2482	rate);
2483	return err;
2484	}
2485	dev_info(component->dev, "set samplerate constraint to %dHz\n", rate);
2486
2487	return 0;
2488	}
2489
2490	static const struct snd_soc_dai_ops tda1997x_dai_ops = {
2491	.startup = tda1997x_pcm_startup,
2492	};
2493
2494	static struct snd_soc_dai_driver tda1997x_audio_dai = {
2495	.name = "tda1997x",
2496	.capture = {
2497	.stream_name = "Capture",
2498	.channels_min = 2,
2499	.channels_max = 8,
2500	.rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
2501	SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
2502	SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
2503	SNDRV_PCM_RATE_192000,
2504	},
2505	.ops = &tda1997x_dai_ops,
2506	};
2507
2508	static int tda1997x_codec_probe(struct snd_soc_component *component)
2509	{
2510	return 0;
2511	}
2512
2513	static void tda1997x_codec_remove(struct snd_soc_component *component)
2514	{
2515	}
2516
2517	static struct snd_soc_component_driver tda1997x_codec_driver = {
2518	.probe = tda1997x_codec_probe,
2519	.remove = tda1997x_codec_remove,
2520	.idle_bias_on = 1,
2521	.use_pmdown_time = 1,
2522	.endianness = 1,
2523	};
2524
2525	static int tda1997x_probe(struct i2c_client *client)
2526	{
2527	const struct i2c_device_id *id = i2c_client_get_device_id(client);
2528	struct tda1997x_state *state;
2529	struct tda1997x_platform_data *pdata;
2530	struct v4l2_subdev *sd;
2531	struct v4l2_ctrl_handler *hdl;
2532	struct v4l2_ctrl *ctrl;
2533	static const struct v4l2_dv_timings cea1920x1080 =
2534	V4L2_DV_BT_CEA_1920X1080P60;
2535	u32 *mbus_codes;
2536	int i, ret;
2537
2538	/* Check if the adapter supports the needed features */
2539	if (!i2c_check_functionality(adap: client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2540	return -EIO;
2541
2542	state = kzalloc(size: sizeof(struct tda1997x_state), GFP_KERNEL);
2543	if (!state)
2544	return -ENOMEM;
2545
2546	state->client = client;
2547	pdata = &state->pdata;
2548	if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) {
2549	const struct of_device_id *oid;
2550
2551	oid = of_match_node(matches: tda1997x_of_id, node: client->dev.of_node);
2552	state->info = oid->data;
2553
2554	ret = tda1997x_parse_dt(state);
2555	if (ret < 0) {
2556	v4l_err(client, "DT parsing error\n");
2557	goto err_free_state;
2558	}
2559	} else if (client->dev.platform_data) {
2560	struct tda1997x_platform_data *pdata =
2561	client->dev.platform_data;
2562	state->info =
2563	(const struct tda1997x_chip_info *)id->driver_data;
2564	state->pdata = *pdata;
2565	} else {
2566	v4l_err(client, "No platform data\n");
2567	ret = -ENODEV;
2568	goto err_free_state;
2569	}
2570
2571	ret = tda1997x_get_regulators(state);
2572	if (ret)
2573	goto err_free_state;
2574
2575	ret = tda1997x_set_power(state, on: 1);
2576	if (ret)
2577	goto err_free_state;
2578
2579	mutex_init(&state->page_lock);
2580	mutex_init(&state->lock);
2581	state->page = 0xff;
2582
2583	INIT_DELAYED_WORK(&state->delayed_work_enable_hpd,
2584	tda1997x_delayed_work_enable_hpd);
2585
2586	/* set video format based on chip and bus width */
2587	ret = tda1997x_identify_module(state);
2588	if (ret)
2589	goto err_free_mutex;
2590
2591	/* initialize subdev */
2592	sd = &state->sd;
2593	v4l2_i2c_subdev_init(sd, client, ops: &tda1997x_subdev_ops);
2594	sd->internal_ops = &tda1997x_internal_ops;
2595	snprintf(buf: sd->name, size: sizeof(sd->name), fmt: "%s %d-%04x",
2596	id->name, i2c_adapter_id(adap: client->adapter),
2597	client->addr);
2598	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
2599	sd->entity.function = MEDIA_ENT_F_DV_DECODER;
2600	sd->entity.ops = &tda1997x_media_ops;
2601
2602	/* set allowed mbus modes based on chip, bus-type, and bus-width */
2603	i = 0;
2604	mbus_codes = state->mbus_codes;
2605	switch (state->info->type) {
2606	case TDA19973:
2607	switch (pdata->vidout_bus_type) {
2608	case V4L2_MBUS_PARALLEL:
2609	switch (pdata->vidout_bus_width) {
2610	case 36:
2611	mbus_codes[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
2612	mbus_codes[i++] = MEDIA_BUS_FMT_YUV12_1X36;
2613	fallthrough;
2614	case 24:
2615	mbus_codes[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
2616	break;
2617	}
2618	break;
2619	case V4L2_MBUS_BT656:
2620	switch (pdata->vidout_bus_width) {
2621	case 36:
2622	case 24:
2623	case 12:
2624	mbus_codes[i++] = MEDIA_BUS_FMT_UYVY12_2X12;
2625	mbus_codes[i++] = MEDIA_BUS_FMT_UYVY10_2X10;
2626	mbus_codes[i++] = MEDIA_BUS_FMT_UYVY8_2X8;
2627	break;
2628	}
2629	break;
2630	default:
2631	break;
2632	}
2633	break;
2634	case TDA19971:
2635	switch (pdata->vidout_bus_type) {
2636	case V4L2_MBUS_PARALLEL:
2637	switch (pdata->vidout_bus_width) {
2638	case 24:
2639	mbus_codes[i++] = MEDIA_BUS_FMT_RGB888_1X24;
2640	mbus_codes[i++] = MEDIA_BUS_FMT_YUV8_1X24;
2641	mbus_codes[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
2642	fallthrough;
2643	case 20:
2644	mbus_codes[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
2645	fallthrough;
2646	case 16:
2647	mbus_codes[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
2648	break;
2649	}
2650	break;
2651	case V4L2_MBUS_BT656:
2652	switch (pdata->vidout_bus_width) {
2653	case 24:
2654	case 20:
2655	case 16:
2656	case 12:
2657	mbus_codes[i++] = MEDIA_BUS_FMT_UYVY12_2X12;
2658	fallthrough;
2659	case 10:
2660	mbus_codes[i++] = MEDIA_BUS_FMT_UYVY10_2X10;
2661	fallthrough;
2662	case 8:
2663	mbus_codes[i++] = MEDIA_BUS_FMT_UYVY8_2X8;
2664	break;
2665	}
2666	break;
2667	default:
2668	break;
2669	}
2670	break;
2671	}
2672	if (WARN_ON(i > ARRAY_SIZE(state->mbus_codes))) {
2673	ret = -EINVAL;
2674	goto err_free_mutex;
2675	}
2676
2677	/* default format */
2678	tda1997x_setup_format(state, code: state->mbus_codes[0]);
2679	state->timings = cea1920x1080;
2680
2681	/*
2682	* default to SRGB full range quantization
2683	* (in case we don't get an infoframe such as DVI signal
2684	*/
2685	state->colorimetry.colorspace = V4L2_COLORSPACE_SRGB;
2686	state->colorimetry.quantization = V4L2_QUANTIZATION_FULL_RANGE;
2687
2688	/* disable/reset HDCP to get correct I2C access to Rx HDMI */
2689	io_write(sd, REG_MAN_SUS_HDMI_SEL, MAN_RST_HDCP | MAN_DIS_HDCP);
2690
2691	/*
2692	* if N2 version, reset compdel_bp as it may generate some small pixel
2693	* shifts in case of embedded sync/or delay lower than 4
2694	*/
2695	if (state->chip_revision != 0) {
2696	io_write(sd, REG_MAN_SUS_HDMI_SEL, val: 0x00);
2697	io_write(sd, REG_VDP_CTRL, val: 0x1f);
2698	}
2699
2700	v4l_info(client, "NXP %s N%d detected\n", state->info->name,
2701	state->chip_revision + 1);
2702	v4l_info(client, "video: %dbit %s %d formats available\n",
2703	pdata->vidout_bus_width,
2704	(pdata->vidout_bus_type == V4L2_MBUS_PARALLEL) ?
2705	"parallel" : "BT656",
2706	i);
2707	if (pdata->audout_format) {
2708	v4l_info(client, "audio: %dch %s layout%d sysclk=%d*fs\n",
2709	pdata->audout_layout ? 2 : 8,
2710	audfmt_names[pdata->audout_format],
2711	pdata->audout_layout,
2712	pdata->audout_mclk_fs);
2713	}
2714
2715	ret = 0x34 + ((io_read(sd, REG_SLAVE_ADDR)>>4) & 0x03);
2716	state->client_cec = devm_i2c_new_dummy_device(dev: &client->dev,
2717	adap: client->adapter, address: ret);
2718	if (IS_ERR(ptr: state->client_cec)) {
2719	ret = PTR_ERR(ptr: state->client_cec);
2720	goto err_free_mutex;
2721	}
2722
2723	v4l_info(client, "CEC slave address 0x%02x\n", ret);
2724
2725	ret = tda1997x_core_init(sd);
2726	if (ret)
2727	goto err_free_mutex;
2728
2729	/* control handlers */
2730	hdl = &state->hdl;
2731	v4l2_ctrl_handler_init(hdl, 3);
2732	ctrl = v4l2_ctrl_new_std_menu(hdl, ops: &tda1997x_ctrl_ops,
2733	V4L2_CID_DV_RX_IT_CONTENT_TYPE,
2734	max: V4L2_DV_IT_CONTENT_TYPE_NO_ITC, mask: 0,
2735	def: V4L2_DV_IT_CONTENT_TYPE_NO_ITC);
2736	if (ctrl)
2737	ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
2738	/* custom controls */
2739	state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
2740	V4L2_CID_DV_RX_POWER_PRESENT, min: 0, max: 1, step: 0, def: 0);
2741	state->rgb_quantization_range_ctrl = v4l2_ctrl_new_std_menu(hdl,
2742	ops: &tda1997x_ctrl_ops,
2743	V4L2_CID_DV_RX_RGB_RANGE, max: V4L2_DV_RGB_RANGE_FULL, mask: 0,
2744	def: V4L2_DV_RGB_RANGE_AUTO);
2745	state->sd.ctrl_handler = hdl;
2746	if (hdl->error) {
2747	ret = hdl->error;
2748	goto err_free_handler;
2749	}
2750	v4l2_ctrl_handler_setup(hdl);
2751
2752	/* initialize source pads */
2753	state->pads[TDA1997X_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
2754	ret = media_entity_pads_init(entity: &sd->entity, num_pads: TDA1997X_NUM_PADS,
2755	pads: state->pads);
2756	if (ret) {
2757	v4l_err(client, "failed entity_init: %d", ret);
2758	goto err_free_handler;
2759	}
2760
2761	ret = v4l2_async_register_subdev(sd);
2762	if (ret)
2763	goto err_free_media;
2764
2765	/* register audio DAI */
2766	if (pdata->audout_format) {
2767	u64 formats;
2768
2769	if (pdata->audout_width == 32)
2770	formats = SNDRV_PCM_FMTBIT_S32_LE;
2771	else
2772	formats = SNDRV_PCM_FMTBIT_S16_LE;
2773	tda1997x_audio_dai.capture.formats = formats;
2774	ret = devm_snd_soc_register_component(dev: &state->client->dev,
2775	component_driver: &tda1997x_codec_driver,
2776	dai_drv: &tda1997x_audio_dai, num_dai: 1);
2777	if (ret) {
2778	dev_err(&client->dev, "register audio codec failed\n");
2779	goto err_free_media;
2780	}
2781	v4l_info(state->client, "registered audio codec\n");
2782	}
2783
2784	/* request irq */
2785	ret = devm_request_threaded_irq(dev: &client->dev, irq: client->irq,
2786	NULL, thread_fn: tda1997x_isr_thread,
2787	IRQF_TRIGGER_LOW | IRQF_ONESHOT,
2788	KBUILD_MODNAME, dev_id: state);
2789	if (ret) {
2790	v4l_err(client, "irq%d reg failed: %d\n", client->irq, ret);
2791	goto err_free_media;
2792	}
2793
2794	return 0;
2795
2796	err_free_media:
2797	media_entity_cleanup(entity: &sd->entity);
2798	err_free_handler:
2799	v4l2_ctrl_handler_free(hdl: &state->hdl);
2800	err_free_mutex:
2801	cancel_delayed_work(dwork: &state->delayed_work_enable_hpd);
2802	mutex_destroy(lock: &state->page_lock);
2803	mutex_destroy(lock: &state->lock);
2804	tda1997x_set_power(state, on: 0);
2805	err_free_state:
2806	kfree(objp: state);
2807	dev_err(&client->dev, "%s failed: %d\n", __func__, ret);
2808
2809	return ret;
2810	}
2811
2812	static void tda1997x_remove(struct i2c_client *client)
2813	{
2814	struct v4l2_subdev *sd = i2c_get_clientdata(client);
2815	struct tda1997x_state *state = to_state(sd);
2816	struct tda1997x_platform_data *pdata = &state->pdata;
2817
2818	if (pdata->audout_format) {
2819	mutex_destroy(lock: &state->audio_lock);
2820	}
2821
2822	disable_irq(irq: state->client->irq);
2823	tda1997x_power_mode(state, enable: 0);
2824
2825	v4l2_async_unregister_subdev(sd);
2826	media_entity_cleanup(entity: &sd->entity);
2827	v4l2_ctrl_handler_free(hdl: &state->hdl);
2828	regulator_bulk_disable(TDA1997X_NUM_SUPPLIES, consumers: state->supplies);
2829	cancel_delayed_work_sync(dwork: &state->delayed_work_enable_hpd);
2830	mutex_destroy(lock: &state->page_lock);
2831	mutex_destroy(lock: &state->lock);
2832
2833	kfree(objp: state);
2834	}
2835
2836	static struct i2c_driver tda1997x_i2c_driver = {
2837	.driver = {
2838	.name = "tda1997x",
2839	.of_match_table = of_match_ptr(tda1997x_of_id),
2840	},
2841	.probe = tda1997x_probe,
2842	.remove = tda1997x_remove,
2843	.id_table = tda1997x_i2c_id,
2844	};
2845
2846	module_i2c_driver(tda1997x_i2c_driver);
2847
2848	MODULE_AUTHOR("Tim Harvey <tharvey@gateworks.com>");
2849	MODULE_DESCRIPTION("TDA1997X HDMI Receiver driver");
2850	MODULE_LICENSE("GPL v2");
2851