1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * device driver for Conexant 2388x based TV cards |
4 | * driver core |
5 | * |
6 | * (c) 2003 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs] |
7 | * |
8 | * (c) 2005-2006 Mauro Carvalho Chehab <mchehab@kernel.org> |
9 | * - Multituner support |
10 | * - video_ioctl2 conversion |
11 | * - PAL/M fixes |
12 | */ |
13 | |
14 | #include "cx88.h" |
15 | |
16 | #include <linux/init.h> |
17 | #include <linux/list.h> |
18 | #include <linux/module.h> |
19 | #include <linux/kernel.h> |
20 | #include <linux/slab.h> |
21 | #include <linux/kmod.h> |
22 | #include <linux/sound.h> |
23 | #include <linux/interrupt.h> |
24 | #include <linux/pci.h> |
25 | #include <linux/delay.h> |
26 | #include <linux/videodev2.h> |
27 | #include <linux/mutex.h> |
28 | |
29 | #include <media/v4l2-common.h> |
30 | #include <media/v4l2-ioctl.h> |
31 | |
32 | MODULE_DESCRIPTION("v4l2 driver module for cx2388x based TV cards" ); |
33 | MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]" ); |
34 | MODULE_LICENSE("GPL v2" ); |
35 | |
36 | /* ------------------------------------------------------------------ */ |
37 | |
38 | unsigned int cx88_core_debug; |
39 | module_param_named(core_debug, cx88_core_debug, int, 0644); |
40 | MODULE_PARM_DESC(core_debug, "enable debug messages [core]" ); |
41 | |
42 | static unsigned int nicam; |
43 | module_param(nicam, int, 0644); |
44 | MODULE_PARM_DESC(nicam, "tv audio is nicam" ); |
45 | |
46 | static unsigned int nocomb; |
47 | module_param(nocomb, int, 0644); |
48 | MODULE_PARM_DESC(nocomb, "disable comb filter" ); |
49 | |
50 | #define dprintk0(fmt, arg...) \ |
51 | printk(KERN_DEBUG pr_fmt("%s: core:" fmt), \ |
52 | __func__, ##arg) \ |
53 | |
54 | #define dprintk(level, fmt, arg...) do { \ |
55 | if (cx88_core_debug >= level) \ |
56 | printk(KERN_DEBUG pr_fmt("%s: core:" fmt), \ |
57 | __func__, ##arg); \ |
58 | } while (0) |
59 | |
60 | static unsigned int cx88_devcount; |
61 | static LIST_HEAD(cx88_devlist); |
62 | static DEFINE_MUTEX(devlist); |
63 | |
64 | #define NO_SYNC_LINE (-1U) |
65 | |
66 | /* |
67 | * @lpi: lines per IRQ, or 0 to not generate irqs. Note: IRQ to be |
68 | * generated _after_ lpi lines are transferred. |
69 | */ |
70 | static __le32 *cx88_risc_field(__le32 *rp, struct scatterlist *sglist, |
71 | unsigned int offset, u32 sync_line, |
72 | unsigned int bpl, unsigned int padding, |
73 | unsigned int lines, unsigned int lpi, bool jump) |
74 | { |
75 | struct scatterlist *sg; |
76 | unsigned int line, todo, sol; |
77 | |
78 | if (jump) { |
79 | (*rp++) = cpu_to_le32(RISC_JUMP); |
80 | (*rp++) = 0; |
81 | } |
82 | |
83 | /* sync instruction */ |
84 | if (sync_line != NO_SYNC_LINE) |
85 | *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line); |
86 | |
87 | /* scan lines */ |
88 | sg = sglist; |
89 | for (line = 0; line < lines; line++) { |
90 | while (offset && offset >= sg_dma_len(sg)) { |
91 | offset -= sg_dma_len(sg); |
92 | sg = sg_next(sg); |
93 | } |
94 | if (lpi && line > 0 && !(line % lpi)) |
95 | sol = RISC_SOL | RISC_IRQ1 | RISC_CNT_INC; |
96 | else |
97 | sol = RISC_SOL; |
98 | if (bpl <= sg_dma_len(sg) - offset) { |
99 | /* fits into current chunk */ |
100 | *(rp++) = cpu_to_le32(RISC_WRITE | sol | |
101 | RISC_EOL | bpl); |
102 | *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset); |
103 | offset += bpl; |
104 | } else { |
105 | /* scanline needs to be split */ |
106 | todo = bpl; |
107 | *(rp++) = cpu_to_le32(RISC_WRITE | sol | |
108 | (sg_dma_len(sg) - offset)); |
109 | *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset); |
110 | todo -= (sg_dma_len(sg) - offset); |
111 | offset = 0; |
112 | sg = sg_next(sg); |
113 | while (todo > sg_dma_len(sg)) { |
114 | *(rp++) = cpu_to_le32(RISC_WRITE | |
115 | sg_dma_len(sg)); |
116 | *(rp++) = cpu_to_le32(sg_dma_address(sg)); |
117 | todo -= sg_dma_len(sg); |
118 | sg = sg_next(sg); |
119 | } |
120 | *(rp++) = cpu_to_le32(RISC_WRITE | RISC_EOL | todo); |
121 | *(rp++) = cpu_to_le32(sg_dma_address(sg)); |
122 | offset += todo; |
123 | } |
124 | offset += padding; |
125 | } |
126 | |
127 | return rp; |
128 | } |
129 | |
130 | int cx88_risc_buffer(struct pci_dev *pci, struct cx88_riscmem *risc, |
131 | struct scatterlist *sglist, |
132 | unsigned int top_offset, unsigned int bottom_offset, |
133 | unsigned int bpl, unsigned int padding, unsigned int lines) |
134 | { |
135 | u32 instructions, fields; |
136 | __le32 *rp; |
137 | |
138 | fields = 0; |
139 | if (top_offset != UNSET) |
140 | fields++; |
141 | if (bottom_offset != UNSET) |
142 | fields++; |
143 | |
144 | /* |
145 | * estimate risc mem: worst case is one write per page border + |
146 | * one write per scan line + syncs + jump (all 2 dwords). Padding |
147 | * can cause next bpl to start close to a page border. First DMA |
148 | * region may be smaller than PAGE_SIZE |
149 | */ |
150 | instructions = fields * (1 + ((bpl + padding) * lines) / |
151 | PAGE_SIZE + lines); |
152 | instructions += 4; |
153 | risc->size = instructions * 8; |
154 | risc->dma = 0; |
155 | risc->cpu = dma_alloc_coherent(dev: &pci->dev, size: risc->size, dma_handle: &risc->dma, |
156 | GFP_KERNEL); |
157 | if (!risc->cpu) |
158 | return -ENOMEM; |
159 | |
160 | /* write risc instructions */ |
161 | rp = risc->cpu; |
162 | if (top_offset != UNSET) |
163 | rp = cx88_risc_field(rp, sglist, offset: top_offset, sync_line: 0, |
164 | bpl, padding, lines, lpi: 0, jump: true); |
165 | if (bottom_offset != UNSET) |
166 | rp = cx88_risc_field(rp, sglist, offset: bottom_offset, sync_line: 0x200, |
167 | bpl, padding, lines, lpi: 0, |
168 | jump: top_offset == UNSET); |
169 | |
170 | /* save pointer to jmp instruction address */ |
171 | risc->jmp = rp; |
172 | WARN_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size); |
173 | return 0; |
174 | } |
175 | EXPORT_SYMBOL(cx88_risc_buffer); |
176 | |
177 | int cx88_risc_databuffer(struct pci_dev *pci, struct cx88_riscmem *risc, |
178 | struct scatterlist *sglist, unsigned int bpl, |
179 | unsigned int lines, unsigned int lpi) |
180 | { |
181 | u32 instructions; |
182 | __le32 *rp; |
183 | |
184 | /* |
185 | * estimate risc mem: worst case is one write per page border + |
186 | * one write per scan line + syncs + jump (all 2 dwords). Here |
187 | * there is no padding and no sync. First DMA region may be smaller |
188 | * than PAGE_SIZE |
189 | */ |
190 | instructions = 1 + (bpl * lines) / PAGE_SIZE + lines; |
191 | instructions += 3; |
192 | risc->size = instructions * 8; |
193 | risc->dma = 0; |
194 | risc->cpu = dma_alloc_coherent(dev: &pci->dev, size: risc->size, dma_handle: &risc->dma, |
195 | GFP_KERNEL); |
196 | if (!risc->cpu) |
197 | return -ENOMEM; |
198 | |
199 | /* write risc instructions */ |
200 | rp = risc->cpu; |
201 | rp = cx88_risc_field(rp, sglist, offset: 0, NO_SYNC_LINE, bpl, padding: 0, |
202 | lines, lpi, jump: !lpi); |
203 | |
204 | /* save pointer to jmp instruction address */ |
205 | risc->jmp = rp; |
206 | WARN_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size); |
207 | return 0; |
208 | } |
209 | EXPORT_SYMBOL(cx88_risc_databuffer); |
210 | |
211 | /* |
212 | * our SRAM memory layout |
213 | */ |
214 | |
215 | /* |
216 | * we are going to put all thr risc programs into host memory, so we |
217 | * can use the whole SDRAM for the DMA fifos. To simplify things, we |
218 | * use a static memory layout. That surely will waste memory in case |
219 | * we don't use all DMA channels at the same time (which will be the |
220 | * case most of the time). But that still gives us enough FIFO space |
221 | * to be able to deal with insane long pci latencies ... |
222 | * |
223 | * FIFO space allocations: |
224 | * channel 21 (y video) - 10.0k |
225 | * channel 22 (u video) - 2.0k |
226 | * channel 23 (v video) - 2.0k |
227 | * channel 24 (vbi) - 4.0k |
228 | * channels 25+26 (audio) - 4.0k |
229 | * channel 28 (mpeg) - 4.0k |
230 | * channel 27 (audio rds)- 3.0k |
231 | * TOTAL = 29.0k |
232 | * |
233 | * Every channel has 160 bytes control data (64 bytes instruction |
234 | * queue and 6 CDT entries), which is close to 2k total. |
235 | * |
236 | * Address layout: |
237 | * 0x0000 - 0x03ff CMDs / reserved |
238 | * 0x0400 - 0x0bff instruction queues + CDs |
239 | * 0x0c00 - FIFOs |
240 | */ |
241 | |
242 | const struct sram_channel cx88_sram_channels[] = { |
243 | [SRAM_CH21] = { |
244 | .name = "video y / packed" , |
245 | .cmds_start = 0x180040, |
246 | .ctrl_start = 0x180400, |
247 | .cdt = 0x180400 + 64, |
248 | .fifo_start = 0x180c00, |
249 | .fifo_size = 0x002800, |
250 | .ptr1_reg = MO_DMA21_PTR1, |
251 | .ptr2_reg = MO_DMA21_PTR2, |
252 | .cnt1_reg = MO_DMA21_CNT1, |
253 | .cnt2_reg = MO_DMA21_CNT2, |
254 | }, |
255 | [SRAM_CH22] = { |
256 | .name = "video u" , |
257 | .cmds_start = 0x180080, |
258 | .ctrl_start = 0x1804a0, |
259 | .cdt = 0x1804a0 + 64, |
260 | .fifo_start = 0x183400, |
261 | .fifo_size = 0x000800, |
262 | .ptr1_reg = MO_DMA22_PTR1, |
263 | .ptr2_reg = MO_DMA22_PTR2, |
264 | .cnt1_reg = MO_DMA22_CNT1, |
265 | .cnt2_reg = MO_DMA22_CNT2, |
266 | }, |
267 | [SRAM_CH23] = { |
268 | .name = "video v" , |
269 | .cmds_start = 0x1800c0, |
270 | .ctrl_start = 0x180540, |
271 | .cdt = 0x180540 + 64, |
272 | .fifo_start = 0x183c00, |
273 | .fifo_size = 0x000800, |
274 | .ptr1_reg = MO_DMA23_PTR1, |
275 | .ptr2_reg = MO_DMA23_PTR2, |
276 | .cnt1_reg = MO_DMA23_CNT1, |
277 | .cnt2_reg = MO_DMA23_CNT2, |
278 | }, |
279 | [SRAM_CH24] = { |
280 | .name = "vbi" , |
281 | .cmds_start = 0x180100, |
282 | .ctrl_start = 0x1805e0, |
283 | .cdt = 0x1805e0 + 64, |
284 | .fifo_start = 0x184400, |
285 | .fifo_size = 0x001000, |
286 | .ptr1_reg = MO_DMA24_PTR1, |
287 | .ptr2_reg = MO_DMA24_PTR2, |
288 | .cnt1_reg = MO_DMA24_CNT1, |
289 | .cnt2_reg = MO_DMA24_CNT2, |
290 | }, |
291 | [SRAM_CH25] = { |
292 | .name = "audio from" , |
293 | .cmds_start = 0x180140, |
294 | .ctrl_start = 0x180680, |
295 | .cdt = 0x180680 + 64, |
296 | .fifo_start = 0x185400, |
297 | .fifo_size = 0x001000, |
298 | .ptr1_reg = MO_DMA25_PTR1, |
299 | .ptr2_reg = MO_DMA25_PTR2, |
300 | .cnt1_reg = MO_DMA25_CNT1, |
301 | .cnt2_reg = MO_DMA25_CNT2, |
302 | }, |
303 | [SRAM_CH26] = { |
304 | .name = "audio to" , |
305 | .cmds_start = 0x180180, |
306 | .ctrl_start = 0x180720, |
307 | .cdt = 0x180680 + 64, /* same as audio IN */ |
308 | .fifo_start = 0x185400, /* same as audio IN */ |
309 | .fifo_size = 0x001000, /* same as audio IN */ |
310 | .ptr1_reg = MO_DMA26_PTR1, |
311 | .ptr2_reg = MO_DMA26_PTR2, |
312 | .cnt1_reg = MO_DMA26_CNT1, |
313 | .cnt2_reg = MO_DMA26_CNT2, |
314 | }, |
315 | [SRAM_CH28] = { |
316 | .name = "mpeg" , |
317 | .cmds_start = 0x180200, |
318 | .ctrl_start = 0x1807C0, |
319 | .cdt = 0x1807C0 + 64, |
320 | .fifo_start = 0x186400, |
321 | .fifo_size = 0x001000, |
322 | .ptr1_reg = MO_DMA28_PTR1, |
323 | .ptr2_reg = MO_DMA28_PTR2, |
324 | .cnt1_reg = MO_DMA28_CNT1, |
325 | .cnt2_reg = MO_DMA28_CNT2, |
326 | }, |
327 | [SRAM_CH27] = { |
328 | .name = "audio rds" , |
329 | .cmds_start = 0x1801C0, |
330 | .ctrl_start = 0x180860, |
331 | .cdt = 0x180860 + 64, |
332 | .fifo_start = 0x187400, |
333 | .fifo_size = 0x000C00, |
334 | .ptr1_reg = MO_DMA27_PTR1, |
335 | .ptr2_reg = MO_DMA27_PTR2, |
336 | .cnt1_reg = MO_DMA27_CNT1, |
337 | .cnt2_reg = MO_DMA27_CNT2, |
338 | }, |
339 | }; |
340 | EXPORT_SYMBOL(cx88_sram_channels); |
341 | |
342 | int cx88_sram_channel_setup(struct cx88_core *core, |
343 | const struct sram_channel *ch, |
344 | unsigned int bpl, u32 risc) |
345 | { |
346 | unsigned int i, lines; |
347 | u32 cdt; |
348 | |
349 | bpl = (bpl + 7) & ~7; /* alignment */ |
350 | cdt = ch->cdt; |
351 | lines = ch->fifo_size / bpl; |
352 | if (lines > 6) |
353 | lines = 6; |
354 | WARN_ON(lines < 2); |
355 | |
356 | /* write CDT */ |
357 | for (i = 0; i < lines; i++) |
358 | cx_write(cdt + 16 * i, ch->fifo_start + bpl * i); |
359 | |
360 | /* write CMDS */ |
361 | cx_write(ch->cmds_start + 0, risc); |
362 | cx_write(ch->cmds_start + 4, cdt); |
363 | cx_write(ch->cmds_start + 8, (lines * 16) >> 3); |
364 | cx_write(ch->cmds_start + 12, ch->ctrl_start); |
365 | cx_write(ch->cmds_start + 16, 64 >> 2); |
366 | for (i = 20; i < 64; i += 4) |
367 | cx_write(ch->cmds_start + i, 0); |
368 | |
369 | /* fill registers */ |
370 | cx_write(ch->ptr1_reg, ch->fifo_start); |
371 | cx_write(ch->ptr2_reg, cdt); |
372 | cx_write(ch->cnt1_reg, (bpl >> 3) - 1); |
373 | cx_write(ch->cnt2_reg, (lines * 16) >> 3); |
374 | |
375 | dprintk(2, "sram setup %s: bpl=%d lines=%d\n" , ch->name, bpl, lines); |
376 | return 0; |
377 | } |
378 | EXPORT_SYMBOL(cx88_sram_channel_setup); |
379 | |
380 | /* ------------------------------------------------------------------ */ |
381 | /* debug helper code */ |
382 | |
383 | static int cx88_risc_decode(u32 risc) |
384 | { |
385 | static const char * const instr[16] = { |
386 | [RISC_SYNC >> 28] = "sync" , |
387 | [RISC_WRITE >> 28] = "write" , |
388 | [RISC_WRITEC >> 28] = "writec" , |
389 | [RISC_READ >> 28] = "read" , |
390 | [RISC_READC >> 28] = "readc" , |
391 | [RISC_JUMP >> 28] = "jump" , |
392 | [RISC_SKIP >> 28] = "skip" , |
393 | [RISC_WRITERM >> 28] = "writerm" , |
394 | [RISC_WRITECM >> 28] = "writecm" , |
395 | [RISC_WRITECR >> 28] = "writecr" , |
396 | }; |
397 | static int const incr[16] = { |
398 | [RISC_WRITE >> 28] = 2, |
399 | [RISC_JUMP >> 28] = 2, |
400 | [RISC_WRITERM >> 28] = 3, |
401 | [RISC_WRITECM >> 28] = 3, |
402 | [RISC_WRITECR >> 28] = 4, |
403 | }; |
404 | static const char * const bits[] = { |
405 | "12" , "13" , "14" , "resync" , |
406 | "cnt0" , "cnt1" , "18" , "19" , |
407 | "20" , "21" , "22" , "23" , |
408 | "irq1" , "irq2" , "eol" , "sol" , |
409 | }; |
410 | int i; |
411 | |
412 | dprintk0("0x%08x [ %s" , risc, |
413 | instr[risc >> 28] ? instr[risc >> 28] : "INVALID" ); |
414 | for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--) |
415 | if (risc & (1 << (i + 12))) |
416 | pr_cont(" %s" , bits[i]); |
417 | pr_cont(" count=%d ]\n" , risc & 0xfff); |
418 | return incr[risc >> 28] ? incr[risc >> 28] : 1; |
419 | } |
420 | |
421 | void cx88_sram_channel_dump(struct cx88_core *core, |
422 | const struct sram_channel *ch) |
423 | { |
424 | static const char * const name[] = { |
425 | "initial risc" , |
426 | "cdt base" , |
427 | "cdt size" , |
428 | "iq base" , |
429 | "iq size" , |
430 | "risc pc" , |
431 | "iq wr ptr" , |
432 | "iq rd ptr" , |
433 | "cdt current" , |
434 | "pci target" , |
435 | "line / byte" , |
436 | }; |
437 | u32 risc; |
438 | unsigned int i, j, n; |
439 | |
440 | dprintk0("%s - dma channel status dump\n" , ch->name); |
441 | for (i = 0; i < ARRAY_SIZE(name); i++) |
442 | dprintk0(" cmds: %-12s: 0x%08x\n" , |
443 | name[i], cx_read(ch->cmds_start + 4 * i)); |
444 | for (n = 1, i = 0; i < 4; i++) { |
445 | risc = cx_read(ch->cmds_start + 4 * (i + 11)); |
446 | pr_cont(" risc%d: " , i); |
447 | if (--n) |
448 | pr_cont("0x%08x [ arg #%d ]\n" , risc, n); |
449 | else |
450 | n = cx88_risc_decode(risc); |
451 | } |
452 | for (i = 0; i < 16; i += n) { |
453 | risc = cx_read(ch->ctrl_start + 4 * i); |
454 | dprintk0(" iq %x: " , i); |
455 | n = cx88_risc_decode(risc); |
456 | for (j = 1; j < n; j++) { |
457 | risc = cx_read(ch->ctrl_start + 4 * (i + j)); |
458 | pr_cont(" iq %x: 0x%08x [ arg #%d ]\n" , |
459 | i + j, risc, j); |
460 | } |
461 | } |
462 | |
463 | dprintk0("fifo: 0x%08x -> 0x%x\n" , |
464 | ch->fifo_start, ch->fifo_start + ch->fifo_size); |
465 | dprintk0("ctrl: 0x%08x -> 0x%x\n" , |
466 | ch->ctrl_start, ch->ctrl_start + 6 * 16); |
467 | dprintk0(" ptr1_reg: 0x%08x\n" , cx_read(ch->ptr1_reg)); |
468 | dprintk0(" ptr2_reg: 0x%08x\n" , cx_read(ch->ptr2_reg)); |
469 | dprintk0(" cnt1_reg: 0x%08x\n" , cx_read(ch->cnt1_reg)); |
470 | dprintk0(" cnt2_reg: 0x%08x\n" , cx_read(ch->cnt2_reg)); |
471 | } |
472 | EXPORT_SYMBOL(cx88_sram_channel_dump); |
473 | |
474 | static const char *cx88_pci_irqs[32] = { |
475 | "vid" , "aud" , "ts" , "vip" , "hst" , "5" , "6" , "tm1" , |
476 | "src_dma" , "dst_dma" , "risc_rd_err" , "risc_wr_err" , |
477 | "brdg_err" , "src_dma_err" , "dst_dma_err" , "ipb_dma_err" , |
478 | "i2c" , "i2c_rack" , "ir_smp" , "gpio0" , "gpio1" |
479 | }; |
480 | |
481 | void cx88_print_irqbits(const char *tag, const char *strings[], |
482 | int len, u32 bits, u32 mask) |
483 | { |
484 | unsigned int i; |
485 | |
486 | dprintk0("%s [0x%x]" , tag, bits); |
487 | for (i = 0; i < len; i++) { |
488 | if (!(bits & (1 << i))) |
489 | continue; |
490 | if (strings[i]) |
491 | pr_cont(" %s" , strings[i]); |
492 | else |
493 | pr_cont(" %d" , i); |
494 | if (!(mask & (1 << i))) |
495 | continue; |
496 | pr_cont("*" ); |
497 | } |
498 | pr_cont("\n" ); |
499 | } |
500 | EXPORT_SYMBOL(cx88_print_irqbits); |
501 | |
502 | /* ------------------------------------------------------------------ */ |
503 | |
504 | int cx88_core_irq(struct cx88_core *core, u32 status) |
505 | { |
506 | int handled = 0; |
507 | |
508 | if (status & PCI_INT_IR_SMPINT) { |
509 | cx88_ir_irq(core); |
510 | handled++; |
511 | } |
512 | if (!handled) |
513 | cx88_print_irqbits("irq pci" , |
514 | cx88_pci_irqs, ARRAY_SIZE(cx88_pci_irqs), |
515 | status, core->pci_irqmask); |
516 | return handled; |
517 | } |
518 | EXPORT_SYMBOL(cx88_core_irq); |
519 | |
520 | void cx88_wakeup(struct cx88_core *core, |
521 | struct cx88_dmaqueue *q, u32 count) |
522 | { |
523 | struct cx88_buffer *buf; |
524 | |
525 | buf = list_entry(q->active.next, |
526 | struct cx88_buffer, list); |
527 | buf->vb.vb2_buf.timestamp = ktime_get_ns(); |
528 | buf->vb.field = core->field; |
529 | buf->vb.sequence = q->count++; |
530 | list_del(entry: &buf->list); |
531 | vb2_buffer_done(vb: &buf->vb.vb2_buf, state: VB2_BUF_STATE_DONE); |
532 | } |
533 | EXPORT_SYMBOL(cx88_wakeup); |
534 | |
535 | void cx88_shutdown(struct cx88_core *core) |
536 | { |
537 | /* disable RISC controller + IRQs */ |
538 | cx_write(MO_DEV_CNTRL2, 0); |
539 | |
540 | /* stop dma transfers */ |
541 | cx_write(MO_VID_DMACNTRL, 0x0); |
542 | cx_write(MO_AUD_DMACNTRL, 0x0); |
543 | cx_write(MO_TS_DMACNTRL, 0x0); |
544 | cx_write(MO_VIP_DMACNTRL, 0x0); |
545 | cx_write(MO_GPHST_DMACNTRL, 0x0); |
546 | |
547 | /* stop interrupts */ |
548 | cx_write(MO_PCI_INTMSK, 0x0); |
549 | cx_write(MO_VID_INTMSK, 0x0); |
550 | cx_write(MO_AUD_INTMSK, 0x0); |
551 | cx_write(MO_TS_INTMSK, 0x0); |
552 | cx_write(MO_VIP_INTMSK, 0x0); |
553 | cx_write(MO_GPHST_INTMSK, 0x0); |
554 | |
555 | /* stop capturing */ |
556 | cx_write(VID_CAPTURE_CONTROL, 0); |
557 | } |
558 | EXPORT_SYMBOL(cx88_shutdown); |
559 | |
560 | int cx88_reset(struct cx88_core *core) |
561 | { |
562 | dprintk(1, "" ); |
563 | cx88_shutdown(core); |
564 | |
565 | /* clear irq status */ |
566 | cx_write(MO_VID_INTSTAT, 0xFFFFFFFF); // Clear PIV int |
567 | cx_write(MO_PCI_INTSTAT, 0xFFFFFFFF); // Clear PCI int |
568 | cx_write(MO_INT1_STAT, 0xFFFFFFFF); // Clear RISC int |
569 | |
570 | /* wait a bit */ |
571 | msleep(msecs: 100); |
572 | |
573 | /* init sram */ |
574 | cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH21], |
575 | 720 * 4, 0); |
576 | cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH22], 128, 0); |
577 | cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH23], 128, 0); |
578 | cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH24], 128, 0); |
579 | cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH25], 128, 0); |
580 | cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH26], 128, 0); |
581 | cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH28], |
582 | 188 * 4, 0); |
583 | cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH27], 128, 0); |
584 | |
585 | /* misc init ... */ |
586 | cx_write(MO_INPUT_FORMAT, ((1 << 13) | // agc enable |
587 | (1 << 12) | // agc gain |
588 | (1 << 11) | // adaptibe agc |
589 | (0 << 10) | // chroma agc |
590 | (0 << 9) | // ckillen |
591 | (7))); |
592 | |
593 | /* setup image format */ |
594 | cx_andor(MO_COLOR_CTRL, 0x4000, 0x4000); |
595 | |
596 | /* setup FIFO Thresholds */ |
597 | cx_write(MO_PDMA_STHRSH, 0x0807); |
598 | cx_write(MO_PDMA_DTHRSH, 0x0807); |
599 | |
600 | /* fixes flashing of image */ |
601 | cx_write(MO_AGC_SYNC_TIP1, 0x0380000F); |
602 | cx_write(MO_AGC_BACK_VBI, 0x00E00555); |
603 | |
604 | cx_write(MO_VID_INTSTAT, 0xFFFFFFFF); // Clear PIV int |
605 | cx_write(MO_PCI_INTSTAT, 0xFFFFFFFF); // Clear PCI int |
606 | cx_write(MO_INT1_STAT, 0xFFFFFFFF); // Clear RISC int |
607 | |
608 | /* Reset on-board parts */ |
609 | cx_write(MO_SRST_IO, 0); |
610 | usleep_range(min: 10000, max: 20000); |
611 | cx_write(MO_SRST_IO, 1); |
612 | |
613 | return 0; |
614 | } |
615 | EXPORT_SYMBOL(cx88_reset); |
616 | |
617 | /* ------------------------------------------------------------------ */ |
618 | |
619 | static inline unsigned int norm_swidth(v4l2_std_id norm) |
620 | { |
621 | if (norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) |
622 | return 754; |
623 | |
624 | if (norm & V4L2_STD_PAL_Nc) |
625 | return 745; |
626 | |
627 | return 922; |
628 | } |
629 | |
630 | static inline unsigned int norm_hdelay(v4l2_std_id norm) |
631 | { |
632 | if (norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) |
633 | return 135; |
634 | |
635 | if (norm & V4L2_STD_PAL_Nc) |
636 | return 149; |
637 | |
638 | return 186; |
639 | } |
640 | |
641 | static inline unsigned int norm_vdelay(v4l2_std_id norm) |
642 | { |
643 | return (norm & V4L2_STD_625_50) ? 0x24 : 0x18; |
644 | } |
645 | |
646 | static inline unsigned int norm_fsc8(v4l2_std_id norm) |
647 | { |
648 | if (norm & V4L2_STD_PAL_M) |
649 | return 28604892; // 3.575611 MHz |
650 | |
651 | if (norm & V4L2_STD_PAL_Nc) |
652 | return 28656448; // 3.582056 MHz |
653 | |
654 | if (norm & V4L2_STD_NTSC) // All NTSC/M and variants |
655 | return 28636360; // 3.57954545 MHz +/- 10 Hz |
656 | |
657 | /* |
658 | * SECAM have also different sub carrier for chroma, |
659 | * but step_db and step_dr, at cx88_set_tvnorm already handles that. |
660 | * |
661 | * The same FSC applies to PAL/BGDKIH, PAL/60, NTSC/4.43 and PAL/N |
662 | */ |
663 | |
664 | return 35468950; // 4.43361875 MHz +/- 5 Hz |
665 | } |
666 | |
667 | static inline unsigned int norm_htotal(v4l2_std_id norm) |
668 | { |
669 | unsigned int fsc4 = norm_fsc8(norm) / 2; |
670 | |
671 | /* returns 4*FSC / vtotal / frames per seconds */ |
672 | return (norm & V4L2_STD_625_50) ? |
673 | ((fsc4 + 312) / 625 + 12) / 25 : |
674 | ((fsc4 + 262) / 525 * 1001 + 15000) / 30000; |
675 | } |
676 | |
677 | static inline unsigned int norm_vbipack(v4l2_std_id norm) |
678 | { |
679 | return (norm & V4L2_STD_625_50) ? 511 : 400; |
680 | } |
681 | |
682 | int cx88_set_scale(struct cx88_core *core, unsigned int width, |
683 | unsigned int height, enum v4l2_field field) |
684 | { |
685 | unsigned int swidth = norm_swidth(norm: core->tvnorm); |
686 | unsigned int sheight = norm_maxh(norm: core->tvnorm); |
687 | u32 value; |
688 | |
689 | dprintk(1, "set_scale: %dx%d [%s%s,%s]\n" , width, height, |
690 | V4L2_FIELD_HAS_TOP(field) ? "T" : "" , |
691 | V4L2_FIELD_HAS_BOTTOM(field) ? "B" : "" , |
692 | v4l2_norm_to_name(core->tvnorm)); |
693 | if (!V4L2_FIELD_HAS_BOTH(field)) |
694 | height *= 2; |
695 | |
696 | // recalc H delay and scale registers |
697 | value = (width * norm_hdelay(norm: core->tvnorm)) / swidth; |
698 | value &= 0x3fe; |
699 | cx_write(MO_HDELAY_EVEN, value); |
700 | cx_write(MO_HDELAY_ODD, value); |
701 | dprintk(1, "set_scale: hdelay 0x%04x (width %d)\n" , value, swidth); |
702 | |
703 | value = (swidth * 4096 / width) - 4096; |
704 | cx_write(MO_HSCALE_EVEN, value); |
705 | cx_write(MO_HSCALE_ODD, value); |
706 | dprintk(1, "set_scale: hscale 0x%04x\n" , value); |
707 | |
708 | cx_write(MO_HACTIVE_EVEN, width); |
709 | cx_write(MO_HACTIVE_ODD, width); |
710 | dprintk(1, "set_scale: hactive 0x%04x\n" , width); |
711 | |
712 | // recalc V scale Register (delay is constant) |
713 | cx_write(MO_VDELAY_EVEN, norm_vdelay(core->tvnorm)); |
714 | cx_write(MO_VDELAY_ODD, norm_vdelay(core->tvnorm)); |
715 | dprintk(1, "set_scale: vdelay 0x%04x\n" , norm_vdelay(core->tvnorm)); |
716 | |
717 | value = (0x10000 - (sheight * 512 / height - 512)) & 0x1fff; |
718 | cx_write(MO_VSCALE_EVEN, value); |
719 | cx_write(MO_VSCALE_ODD, value); |
720 | dprintk(1, "set_scale: vscale 0x%04x\n" , value); |
721 | |
722 | cx_write(MO_VACTIVE_EVEN, sheight); |
723 | cx_write(MO_VACTIVE_ODD, sheight); |
724 | dprintk(1, "set_scale: vactive 0x%04x\n" , sheight); |
725 | |
726 | // setup filters |
727 | value = 0; |
728 | value |= (1 << 19); // CFILT (default) |
729 | if (core->tvnorm & V4L2_STD_SECAM) { |
730 | value |= (1 << 15); |
731 | value |= (1 << 16); |
732 | } |
733 | if (INPUT(core->input).type == CX88_VMUX_SVIDEO) |
734 | value |= (1 << 13) | (1 << 5); |
735 | if (field == V4L2_FIELD_INTERLACED) |
736 | value |= (1 << 3); // VINT (interlaced vertical scaling) |
737 | if (width < 385) |
738 | value |= (1 << 0); // 3-tap interpolation |
739 | if (width < 193) |
740 | value |= (1 << 1); // 5-tap interpolation |
741 | if (nocomb) |
742 | value |= (3 << 5); // disable comb filter |
743 | |
744 | cx_andor(MO_FILTER_EVEN, 0x7ffc7f, value); /* preserve PEAKEN, PSEL */ |
745 | cx_andor(MO_FILTER_ODD, 0x7ffc7f, value); |
746 | dprintk(1, "set_scale: filter 0x%04x\n" , value); |
747 | |
748 | return 0; |
749 | } |
750 | EXPORT_SYMBOL(cx88_set_scale); |
751 | |
752 | static const u32 xtal = 28636363; |
753 | |
754 | static int set_pll(struct cx88_core *core, int prescale, u32 ofreq) |
755 | { |
756 | static const u32 pre[] = { 0, 0, 0, 3, 2, 1 }; |
757 | u64 pll; |
758 | u32 reg; |
759 | int i; |
760 | |
761 | if (prescale < 2) |
762 | prescale = 2; |
763 | if (prescale > 5) |
764 | prescale = 5; |
765 | |
766 | pll = ofreq * 8 * prescale * (u64)(1 << 20); |
767 | do_div(pll, xtal); |
768 | reg = (pll & 0x3ffffff) | (pre[prescale] << 26); |
769 | if (((reg >> 20) & 0x3f) < 14) { |
770 | pr_err("pll out of range\n" ); |
771 | return -1; |
772 | } |
773 | |
774 | dprintk(1, "set_pll: MO_PLL_REG 0x%08x [old=0x%08x,freq=%d]\n" , |
775 | reg, cx_read(MO_PLL_REG), ofreq); |
776 | cx_write(MO_PLL_REG, reg); |
777 | for (i = 0; i < 100; i++) { |
778 | reg = cx_read(MO_DEVICE_STATUS); |
779 | if (reg & (1 << 2)) { |
780 | dprintk(1, "pll locked [pre=%d,ofreq=%d]\n" , |
781 | prescale, ofreq); |
782 | return 0; |
783 | } |
784 | dprintk(1, "pll not locked yet, waiting ...\n" ); |
785 | usleep_range(min: 10000, max: 20000); |
786 | } |
787 | dprintk(1, "pll NOT locked [pre=%d,ofreq=%d]\n" , prescale, ofreq); |
788 | return -1; |
789 | } |
790 | |
791 | int cx88_start_audio_dma(struct cx88_core *core) |
792 | { |
793 | /* constant 128 made buzz in analog Nicam-stereo for bigger fifo_size */ |
794 | int bpl = cx88_sram_channels[SRAM_CH25].fifo_size / 4; |
795 | |
796 | int rds_bpl = cx88_sram_channels[SRAM_CH27].fifo_size / AUD_RDS_LINES; |
797 | |
798 | /* If downstream RISC is enabled, bail out; ALSA is managing DMA */ |
799 | if (cx_read(MO_AUD_DMACNTRL) & 0x10) |
800 | return 0; |
801 | |
802 | /* setup fifo + format */ |
803 | cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH25], bpl, 0); |
804 | cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH26], bpl, 0); |
805 | cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH27], |
806 | rds_bpl, 0); |
807 | |
808 | cx_write(MO_AUDD_LNGTH, bpl); /* fifo bpl size */ |
809 | cx_write(MO_AUDR_LNGTH, rds_bpl); /* fifo bpl size */ |
810 | |
811 | /* enable Up, Down and Audio RDS fifo */ |
812 | cx_write(MO_AUD_DMACNTRL, 0x0007); |
813 | |
814 | return 0; |
815 | } |
816 | |
817 | int cx88_stop_audio_dma(struct cx88_core *core) |
818 | { |
819 | /* If downstream RISC is enabled, bail out; ALSA is managing DMA */ |
820 | if (cx_read(MO_AUD_DMACNTRL) & 0x10) |
821 | return 0; |
822 | |
823 | /* stop dma */ |
824 | cx_write(MO_AUD_DMACNTRL, 0x0000); |
825 | |
826 | return 0; |
827 | } |
828 | |
829 | static int set_tvaudio(struct cx88_core *core) |
830 | { |
831 | v4l2_std_id norm = core->tvnorm; |
832 | |
833 | if (INPUT(core->input).type != CX88_VMUX_TELEVISION && |
834 | INPUT(core->input).type != CX88_VMUX_CABLE) |
835 | return 0; |
836 | |
837 | if (V4L2_STD_PAL_BG & norm) { |
838 | core->tvaudio = WW_BG; |
839 | |
840 | } else if (V4L2_STD_PAL_DK & norm) { |
841 | core->tvaudio = WW_DK; |
842 | |
843 | } else if (V4L2_STD_PAL_I & norm) { |
844 | core->tvaudio = WW_I; |
845 | |
846 | } else if (V4L2_STD_SECAM_L & norm) { |
847 | core->tvaudio = WW_L; |
848 | |
849 | } else if ((V4L2_STD_SECAM_B | V4L2_STD_SECAM_G | V4L2_STD_SECAM_H) & |
850 | norm) { |
851 | core->tvaudio = WW_BG; |
852 | |
853 | } else if (V4L2_STD_SECAM_DK & norm) { |
854 | core->tvaudio = WW_DK; |
855 | |
856 | } else if ((V4L2_STD_NTSC_M | V4L2_STD_PAL_M | V4L2_STD_PAL_Nc) & |
857 | norm) { |
858 | core->tvaudio = WW_BTSC; |
859 | |
860 | } else if (V4L2_STD_NTSC_M_JP & norm) { |
861 | core->tvaudio = WW_EIAJ; |
862 | |
863 | } else { |
864 | pr_info("tvaudio support needs work for this tv norm [%s], sorry\n" , |
865 | v4l2_norm_to_name(core->tvnorm)); |
866 | core->tvaudio = WW_NONE; |
867 | return 0; |
868 | } |
869 | |
870 | cx_andor(MO_AFECFG_IO, 0x1f, 0x0); |
871 | cx88_set_tvaudio(core); |
872 | /* cx88_set_stereo(dev,V4L2_TUNER_MODE_STEREO); */ |
873 | |
874 | /* |
875 | * This should be needed only on cx88-alsa. It seems that some cx88 chips have |
876 | * bugs and does require DMA enabled for it to work. |
877 | */ |
878 | cx88_start_audio_dma(core); |
879 | return 0; |
880 | } |
881 | |
882 | int cx88_set_tvnorm(struct cx88_core *core, v4l2_std_id norm) |
883 | { |
884 | u32 fsc8; |
885 | u32 adc_clock; |
886 | u32 vdec_clock; |
887 | u32 step_db, step_dr; |
888 | u64 tmp64; |
889 | u32 bdelay, agcdelay, htotal; |
890 | u32 cxiformat, cxoformat; |
891 | |
892 | if (norm == core->tvnorm) |
893 | return 0; |
894 | if (core->v4ldev && (vb2_is_busy(q: &core->v4ldev->vb2_vidq) || |
895 | vb2_is_busy(q: &core->v4ldev->vb2_vbiq))) |
896 | return -EBUSY; |
897 | if (core->dvbdev && vb2_is_busy(q: &core->dvbdev->vb2_mpegq)) |
898 | return -EBUSY; |
899 | core->tvnorm = norm; |
900 | fsc8 = norm_fsc8(norm); |
901 | adc_clock = xtal; |
902 | vdec_clock = fsc8; |
903 | step_db = fsc8; |
904 | step_dr = fsc8; |
905 | |
906 | if (norm & V4L2_STD_NTSC_M_JP) { |
907 | cxiformat = VideoFormatNTSCJapan; |
908 | cxoformat = 0x181f0008; |
909 | } else if (norm & V4L2_STD_NTSC_443) { |
910 | cxiformat = VideoFormatNTSC443; |
911 | cxoformat = 0x181f0008; |
912 | } else if (norm & V4L2_STD_PAL_M) { |
913 | cxiformat = VideoFormatPALM; |
914 | cxoformat = 0x1c1f0008; |
915 | } else if (norm & V4L2_STD_PAL_N) { |
916 | cxiformat = VideoFormatPALN; |
917 | cxoformat = 0x1c1f0008; |
918 | } else if (norm & V4L2_STD_PAL_Nc) { |
919 | cxiformat = VideoFormatPALNC; |
920 | cxoformat = 0x1c1f0008; |
921 | } else if (norm & V4L2_STD_PAL_60) { |
922 | cxiformat = VideoFormatPAL60; |
923 | cxoformat = 0x181f0008; |
924 | } else if (norm & V4L2_STD_NTSC) { |
925 | cxiformat = VideoFormatNTSC; |
926 | cxoformat = 0x181f0008; |
927 | } else if (norm & V4L2_STD_SECAM) { |
928 | step_db = 4250000 * 8; |
929 | step_dr = 4406250 * 8; |
930 | |
931 | cxiformat = VideoFormatSECAM; |
932 | cxoformat = 0x181f0008; |
933 | } else { /* PAL */ |
934 | cxiformat = VideoFormatPAL; |
935 | cxoformat = 0x181f0008; |
936 | } |
937 | |
938 | dprintk(1, "set_tvnorm: \"%s\" fsc8=%d adc=%d vdec=%d db/dr=%d/%d\n" , |
939 | v4l2_norm_to_name(core->tvnorm), fsc8, adc_clock, vdec_clock, |
940 | step_db, step_dr); |
941 | set_pll(core, prescale: 2, ofreq: vdec_clock); |
942 | |
943 | dprintk(1, "set_tvnorm: MO_INPUT_FORMAT 0x%08x [old=0x%08x]\n" , |
944 | cxiformat, cx_read(MO_INPUT_FORMAT) & 0x0f); |
945 | /* |
946 | * Chroma AGC must be disabled if SECAM is used, we enable it |
947 | * by default on PAL and NTSC |
948 | */ |
949 | cx_andor(MO_INPUT_FORMAT, 0x40f, |
950 | norm & V4L2_STD_SECAM ? cxiformat : cxiformat | 0x400); |
951 | |
952 | // FIXME: as-is from DScaler |
953 | dprintk(1, "set_tvnorm: MO_OUTPUT_FORMAT 0x%08x [old=0x%08x]\n" , |
954 | cxoformat, cx_read(MO_OUTPUT_FORMAT)); |
955 | cx_write(MO_OUTPUT_FORMAT, cxoformat); |
956 | |
957 | // MO_SCONV_REG = adc clock / video dec clock * 2^17 |
958 | tmp64 = adc_clock * (u64)(1 << 17); |
959 | do_div(tmp64, vdec_clock); |
960 | dprintk(1, "set_tvnorm: MO_SCONV_REG 0x%08x [old=0x%08x]\n" , |
961 | (u32)tmp64, cx_read(MO_SCONV_REG)); |
962 | cx_write(MO_SCONV_REG, (u32)tmp64); |
963 | |
964 | // MO_SUB_STEP = 8 * fsc / video dec clock * 2^22 |
965 | tmp64 = step_db * (u64)(1 << 22); |
966 | do_div(tmp64, vdec_clock); |
967 | dprintk(1, "set_tvnorm: MO_SUB_STEP 0x%08x [old=0x%08x]\n" , |
968 | (u32)tmp64, cx_read(MO_SUB_STEP)); |
969 | cx_write(MO_SUB_STEP, (u32)tmp64); |
970 | |
971 | // MO_SUB_STEP_DR = 8 * 4406250 / video dec clock * 2^22 |
972 | tmp64 = step_dr * (u64)(1 << 22); |
973 | do_div(tmp64, vdec_clock); |
974 | dprintk(1, "set_tvnorm: MO_SUB_STEP_DR 0x%08x [old=0x%08x]\n" , |
975 | (u32)tmp64, cx_read(MO_SUB_STEP_DR)); |
976 | cx_write(MO_SUB_STEP_DR, (u32)tmp64); |
977 | |
978 | // bdelay + agcdelay |
979 | bdelay = vdec_clock * 65 / 20000000 + 21; |
980 | agcdelay = vdec_clock * 68 / 20000000 + 15; |
981 | dprintk(1, |
982 | "set_tvnorm: MO_AGC_BURST 0x%08x [old=0x%08x,bdelay=%d,agcdelay=%d]\n" , |
983 | (bdelay << 8) | agcdelay, cx_read(MO_AGC_BURST), |
984 | bdelay, agcdelay); |
985 | cx_write(MO_AGC_BURST, (bdelay << 8) | agcdelay); |
986 | |
987 | // htotal |
988 | tmp64 = norm_htotal(norm) * (u64)vdec_clock; |
989 | do_div(tmp64, fsc8); |
990 | htotal = (u32)tmp64; |
991 | dprintk(1, |
992 | "set_tvnorm: MO_HTOTAL 0x%08x [old=0x%08x,htotal=%d]\n" , |
993 | htotal, cx_read(MO_HTOTAL), (u32)tmp64); |
994 | cx_andor(MO_HTOTAL, 0x07ff, htotal); |
995 | |
996 | // vbi stuff, set vbi offset to 10 (for 20 Clk*2 pixels), this makes |
997 | // the effective vbi offset ~244 samples, the same as the Bt8x8 |
998 | cx_write(MO_VBI_PACKET, (10 << 11) | norm_vbipack(norm)); |
999 | |
1000 | // this is needed as well to set all tvnorm parameter |
1001 | cx88_set_scale(core, 320, 240, V4L2_FIELD_INTERLACED); |
1002 | |
1003 | // audio |
1004 | set_tvaudio(core); |
1005 | |
1006 | // tell i2c chips |
1007 | call_all(core, video, s_std, norm); |
1008 | |
1009 | /* |
1010 | * The chroma_agc control should be inaccessible |
1011 | * if the video format is SECAM |
1012 | */ |
1013 | v4l2_ctrl_grab(ctrl: core->chroma_agc, grabbed: cxiformat == VideoFormatSECAM); |
1014 | |
1015 | // done |
1016 | return 0; |
1017 | } |
1018 | EXPORT_SYMBOL(cx88_set_tvnorm); |
1019 | |
1020 | /* ------------------------------------------------------------------ */ |
1021 | |
1022 | void cx88_vdev_init(struct cx88_core *core, |
1023 | struct pci_dev *pci, |
1024 | struct video_device *vfd, |
1025 | const struct video_device *template_, |
1026 | const char *type) |
1027 | { |
1028 | *vfd = *template_; |
1029 | |
1030 | /* |
1031 | * The dev pointer of v4l2_device is NULL, instead we set the |
1032 | * video_device dev_parent pointer to the correct PCI bus device. |
1033 | * This driver is a rare example where there is one v4l2_device, |
1034 | * but the video nodes have different parent (PCI) devices. |
1035 | */ |
1036 | vfd->v4l2_dev = &core->v4l2_dev; |
1037 | vfd->dev_parent = &pci->dev; |
1038 | vfd->release = video_device_release_empty; |
1039 | vfd->lock = &core->lock; |
1040 | snprintf(buf: vfd->name, size: sizeof(vfd->name), fmt: "%s %s (%s)" , |
1041 | core->name, type, core->board.name); |
1042 | } |
1043 | EXPORT_SYMBOL(cx88_vdev_init); |
1044 | |
1045 | struct cx88_core *cx88_core_get(struct pci_dev *pci) |
1046 | { |
1047 | struct cx88_core *core; |
1048 | |
1049 | mutex_lock(&devlist); |
1050 | list_for_each_entry(core, &cx88_devlist, devlist) { |
1051 | if (pci->bus->number != core->pci_bus) |
1052 | continue; |
1053 | if (PCI_SLOT(pci->devfn) != core->pci_slot) |
1054 | continue; |
1055 | |
1056 | if (cx88_get_resources(core, pci) != 0) { |
1057 | mutex_unlock(lock: &devlist); |
1058 | return NULL; |
1059 | } |
1060 | refcount_inc(r: &core->refcount); |
1061 | mutex_unlock(lock: &devlist); |
1062 | return core; |
1063 | } |
1064 | |
1065 | core = cx88_core_create(pci, nr: cx88_devcount); |
1066 | if (core) { |
1067 | cx88_devcount++; |
1068 | list_add_tail(new: &core->devlist, head: &cx88_devlist); |
1069 | } |
1070 | |
1071 | mutex_unlock(lock: &devlist); |
1072 | return core; |
1073 | } |
1074 | EXPORT_SYMBOL(cx88_core_get); |
1075 | |
1076 | void cx88_core_put(struct cx88_core *core, struct pci_dev *pci) |
1077 | { |
1078 | release_mem_region(pci_resource_start(pci, 0), |
1079 | pci_resource_len(pci, 0)); |
1080 | |
1081 | if (!refcount_dec_and_test(r: &core->refcount)) |
1082 | return; |
1083 | |
1084 | mutex_lock(&devlist); |
1085 | cx88_ir_fini(core); |
1086 | if (core->i2c_rc == 0) { |
1087 | i2c_unregister_device(client: core->i2c_rtc); |
1088 | i2c_del_adapter(adap: &core->i2c_adap); |
1089 | } |
1090 | list_del(entry: &core->devlist); |
1091 | iounmap(addr: core->lmmio); |
1092 | cx88_devcount--; |
1093 | mutex_unlock(lock: &devlist); |
1094 | v4l2_ctrl_handler_free(hdl: &core->video_hdl); |
1095 | v4l2_ctrl_handler_free(hdl: &core->audio_hdl); |
1096 | v4l2_device_unregister(v4l2_dev: &core->v4l2_dev); |
1097 | kfree(objp: core); |
1098 | } |
1099 | EXPORT_SYMBOL(cx88_core_put); |
1100 | |