1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Hantro VPU codec driver
4 *
5 * Copyright 2018 Google LLC.
6 * Tomasz Figa <tfiga@chromium.org>
7 *
8 * Based on s5p-mfc driver by Samsung Electronics Co., Ltd.
9 * Copyright (C) 2011 Samsung Electronics Co., Ltd.
10 */
11
12#ifndef HANTRO_H_
13#define HANTRO_H_
14
15#include <linux/platform_device.h>
16#include <linux/videodev2.h>
17#include <linux/wait.h>
18#include <linux/clk.h>
19#include <linux/reset.h>
20
21#include <media/v4l2-ctrls.h>
22#include <media/v4l2-device.h>
23#include <media/v4l2-ioctl.h>
24#include <media/v4l2-mem2mem.h>
25#include <media/videobuf2-core.h>
26#include <media/videobuf2-dma-contig.h>
27
28#include "hantro_hw.h"
29
30struct hantro_ctx;
31struct hantro_codec_ops;
32struct hantro_postproc_ops;
33
34#define HANTRO_JPEG_ENCODER BIT(0)
35#define HANTRO_ENCODERS 0x0000ffff
36#define HANTRO_MPEG2_DECODER BIT(16)
37#define HANTRO_VP8_DECODER BIT(17)
38#define HANTRO_H264_DECODER BIT(18)
39#define HANTRO_HEVC_DECODER BIT(19)
40#define HANTRO_VP9_DECODER BIT(20)
41#define HANTRO_AV1_DECODER BIT(21)
42#define HANTRO_DECODERS 0xffff0000
43
44/**
45 * struct hantro_irq - irq handler and name
46 *
47 * @name: irq name for device tree lookup
48 * @handler: interrupt handler
49 */
50struct hantro_irq {
51 const char *name;
52 irqreturn_t (*handler)(int irq, void *priv);
53};
54
55/**
56 * struct hantro_variant - information about VPU hardware variant
57 *
58 * @enc_offset: Offset from VPU base to encoder registers.
59 * @dec_offset: Offset from VPU base to decoder registers.
60 * @enc_fmts: Encoder formats.
61 * @num_enc_fmts: Number of encoder formats.
62 * @dec_fmts: Decoder formats.
63 * @num_dec_fmts: Number of decoder formats.
64 * @postproc_fmts: Post-processor formats.
65 * @num_postproc_fmts: Number of post-processor formats.
66 * @postproc_ops: Post-processor ops.
67 * @codec: Supported codecs
68 * @codec_ops: Codec ops.
69 * @init: Initialize hardware, optional.
70 * @runtime_resume: reenable hardware after power gating, optional.
71 * @irqs: array of irq names and interrupt handlers
72 * @num_irqs: number of irqs in the array
73 * @clk_names: array of clock names
74 * @num_clocks: number of clocks in the array
75 * @reg_names: array of register range names
76 * @num_regs: number of register range names in the array
77 * @double_buffer: core needs double buffering
78 * @legacy_regs: core uses legacy register set
79 * @late_postproc: postproc must be set up at the end of the job
80 */
81struct hantro_variant {
82 unsigned int enc_offset;
83 unsigned int dec_offset;
84 const struct hantro_fmt *enc_fmts;
85 unsigned int num_enc_fmts;
86 const struct hantro_fmt *dec_fmts;
87 unsigned int num_dec_fmts;
88 const struct hantro_fmt *postproc_fmts;
89 unsigned int num_postproc_fmts;
90 const struct hantro_postproc_ops *postproc_ops;
91 unsigned int codec;
92 const struct hantro_codec_ops *codec_ops;
93 int (*init)(struct hantro_dev *vpu);
94 int (*runtime_resume)(struct hantro_dev *vpu);
95 const struct hantro_irq *irqs;
96 int num_irqs;
97 const char * const *clk_names;
98 int num_clocks;
99 const char * const *reg_names;
100 int num_regs;
101 unsigned int double_buffer : 1;
102 unsigned int legacy_regs : 1;
103 unsigned int late_postproc : 1;
104};
105
106/**
107 * enum hantro_codec_mode - codec operating mode.
108 * @HANTRO_MODE_NONE: No operating mode. Used for RAW video formats.
109 * @HANTRO_MODE_JPEG_ENC: JPEG encoder.
110 * @HANTRO_MODE_H264_DEC: H264 decoder.
111 * @HANTRO_MODE_MPEG2_DEC: MPEG-2 decoder.
112 * @HANTRO_MODE_VP8_DEC: VP8 decoder.
113 * @HANTRO_MODE_HEVC_DEC: HEVC decoder.
114 * @HANTRO_MODE_VP9_DEC: VP9 decoder.
115 * @HANTRO_MODE_AV1_DEC: AV1 decoder
116 */
117enum hantro_codec_mode {
118 HANTRO_MODE_NONE = -1,
119 HANTRO_MODE_JPEG_ENC,
120 HANTRO_MODE_H264_DEC,
121 HANTRO_MODE_MPEG2_DEC,
122 HANTRO_MODE_VP8_DEC,
123 HANTRO_MODE_HEVC_DEC,
124 HANTRO_MODE_VP9_DEC,
125 HANTRO_MODE_AV1_DEC,
126};
127
128/*
129 * struct hantro_ctrl - helper type to declare supported controls
130 * @codec: codec id this control belong to (HANTRO_JPEG_ENCODER, etc.)
131 * @cfg: control configuration
132 */
133struct hantro_ctrl {
134 unsigned int codec;
135 struct v4l2_ctrl_config cfg;
136};
137
138/*
139 * struct hantro_func - Hantro VPU functionality
140 *
141 * @id: processing functionality ID (can be
142 * %MEDIA_ENT_F_PROC_VIDEO_ENCODER or
143 * %MEDIA_ENT_F_PROC_VIDEO_DECODER)
144 * @vdev: &struct video_device that exposes the encoder or
145 * decoder functionality
146 * @source_pad: &struct media_pad with the source pad.
147 * @sink: &struct media_entity pointer with the sink entity
148 * @sink_pad: &struct media_pad with the sink pad.
149 * @proc: &struct media_entity pointer with the M2M device itself.
150 * @proc_pads: &struct media_pad with the @proc pads.
151 * @intf_devnode: &struct media_intf devnode pointer with the interface
152 * with controls the M2M device.
153 *
154 * Contains everything needed to attach the video device to the media device.
155 */
156struct hantro_func {
157 unsigned int id;
158 struct video_device vdev;
159 struct media_pad source_pad;
160 struct media_entity sink;
161 struct media_pad sink_pad;
162 struct media_entity proc;
163 struct media_pad proc_pads[2];
164 struct media_intf_devnode *intf_devnode;
165};
166
167static inline struct hantro_func *
168hantro_vdev_to_func(struct video_device *vdev)
169{
170 return container_of(vdev, struct hantro_func, vdev);
171}
172
173/**
174 * struct hantro_dev - driver data
175 * @v4l2_dev: V4L2 device to register video devices for.
176 * @m2m_dev: mem2mem device associated to this device.
177 * @mdev: media device associated to this device.
178 * @encoder: encoder functionality.
179 * @decoder: decoder functionality.
180 * @pdev: Pointer to VPU platform device.
181 * @dev: Pointer to device for convenient logging using
182 * dev_ macros.
183 * @clocks: Array of clock handles.
184 * @resets: Array of reset handles.
185 * @reg_bases: Mapped addresses of VPU registers.
186 * @enc_base: Mapped address of VPU encoder register for convenience.
187 * @dec_base: Mapped address of VPU decoder register for convenience.
188 * @ctrl_base: Mapped address of VPU control block.
189 * @vpu_mutex: Mutex to synchronize V4L2 calls.
190 * @irqlock: Spinlock to synchronize access to data structures
191 * shared with interrupt handlers.
192 * @variant: Hardware variant-specific parameters.
193 * @watchdog_work: Delayed work for hardware timeout handling.
194 */
195struct hantro_dev {
196 struct v4l2_device v4l2_dev;
197 struct v4l2_m2m_dev *m2m_dev;
198 struct media_device mdev;
199 struct hantro_func *encoder;
200 struct hantro_func *decoder;
201 struct platform_device *pdev;
202 struct device *dev;
203 struct clk_bulk_data *clocks;
204 struct reset_control *resets;
205 void __iomem **reg_bases;
206 void __iomem *enc_base;
207 void __iomem *dec_base;
208 void __iomem *ctrl_base;
209
210 struct mutex vpu_mutex; /* video_device lock */
211 spinlock_t irqlock;
212 const struct hantro_variant *variant;
213 struct delayed_work watchdog_work;
214};
215
216/**
217 * struct hantro_ctx - Context (instance) private data.
218 *
219 * @dev: VPU driver data to which the context belongs.
220 * @fh: V4L2 file handler.
221 * @is_encoder: Decoder or encoder context?
222 *
223 * @sequence_cap: Sequence counter for capture queue
224 * @sequence_out: Sequence counter for output queue
225 *
226 * @vpu_src_fmt: Descriptor of active source format.
227 * @src_fmt: V4L2 pixel format of active source format.
228 * @vpu_dst_fmt: Descriptor of active destination format.
229 * @dst_fmt: V4L2 pixel format of active destination format.
230 * @ref_fmt: V4L2 pixel format of the reference frames format.
231 *
232 * @ctrl_handler: Control handler used to register controls.
233 * @jpeg_quality: User-specified JPEG compression quality.
234 * @bit_depth: Bit depth of current frame
235 * @need_postproc: Set to true if the bitstream features require to
236 * use the post-processor.
237 *
238 * @codec_ops: Set of operations related to codec mode.
239 * @postproc: Post-processing context.
240 * @h264_dec: H.264-decoding context.
241 * @mpeg2_dec: MPEG-2-decoding context.
242 * @vp8_dec: VP8-decoding context.
243 * @hevc_dec: HEVC-decoding context.
244 * @vp9_dec: VP9-decoding context.
245 * @av1_dec: AV1-decoding context.
246 */
247struct hantro_ctx {
248 struct hantro_dev *dev;
249 struct v4l2_fh fh;
250 bool is_encoder;
251
252 u32 sequence_cap;
253 u32 sequence_out;
254
255 const struct hantro_fmt *vpu_src_fmt;
256 struct v4l2_pix_format_mplane src_fmt;
257 const struct hantro_fmt *vpu_dst_fmt;
258 struct v4l2_pix_format_mplane dst_fmt;
259 struct v4l2_pix_format_mplane ref_fmt;
260
261 struct v4l2_ctrl_handler ctrl_handler;
262 int jpeg_quality;
263 int bit_depth;
264
265 const struct hantro_codec_ops *codec_ops;
266 struct hantro_postproc_ctx postproc;
267 bool need_postproc;
268
269 /* Specific for particular codec modes. */
270 union {
271 struct hantro_h264_dec_hw_ctx h264_dec;
272 struct hantro_mpeg2_dec_hw_ctx mpeg2_dec;
273 struct hantro_vp8_dec_hw_ctx vp8_dec;
274 struct hantro_hevc_dec_hw_ctx hevc_dec;
275 struct hantro_vp9_dec_hw_ctx vp9_dec;
276 struct hantro_av1_dec_hw_ctx av1_dec;
277 };
278};
279
280/**
281 * struct hantro_fmt - information about supported video formats.
282 * @name: Human readable name of the format.
283 * @fourcc: FourCC code of the format. See V4L2_PIX_FMT_*.
284 * @codec_mode: Codec mode related to this format. See
285 * enum hantro_codec_mode.
286 * @header_size: Optional header size. Currently used by JPEG encoder.
287 * @max_depth: Maximum depth, for bitstream formats
288 * @enc_fmt: Format identifier for encoder registers.
289 * @frmsize: Supported range of frame sizes (only for bitstream formats).
290 * @postprocessed: Indicates if this format needs the post-processor.
291 * @match_depth: Indicates if format bit depth must match video bit depth
292 */
293struct hantro_fmt {
294 char *name;
295 u32 fourcc;
296 enum hantro_codec_mode codec_mode;
297 int header_size;
298 int max_depth;
299 enum hantro_enc_fmt enc_fmt;
300 struct v4l2_frmsize_stepwise frmsize;
301 bool postprocessed;
302 bool match_depth;
303};
304
305struct hantro_reg {
306 u32 base;
307 u32 shift;
308 u32 mask;
309};
310
311struct hantro_postproc_regs {
312 struct hantro_reg pipeline_en;
313 struct hantro_reg max_burst;
314 struct hantro_reg clk_gate;
315 struct hantro_reg out_swap32;
316 struct hantro_reg out_endian;
317 struct hantro_reg out_luma_base;
318 struct hantro_reg input_width;
319 struct hantro_reg input_height;
320 struct hantro_reg output_width;
321 struct hantro_reg output_height;
322 struct hantro_reg input_fmt;
323 struct hantro_reg output_fmt;
324 struct hantro_reg orig_width;
325 struct hantro_reg display_width;
326 struct hantro_reg input_width_ext;
327 struct hantro_reg input_height_ext;
328};
329
330struct hantro_vp9_decoded_buffer_info {
331 /* Info needed when the decoded frame serves as a reference frame. */
332 unsigned short width;
333 unsigned short height;
334 size_t chroma_offset;
335 size_t mv_offset;
336 u32 bit_depth : 4;
337};
338
339struct hantro_av1_decoded_buffer_info {
340 /* Info needed when the decoded frame serves as a reference frame. */
341 size_t chroma_offset;
342 size_t mv_offset;
343};
344
345struct hantro_decoded_buffer {
346 /* Must be the first field in this struct. */
347 struct v4l2_m2m_buffer base;
348
349 union {
350 struct hantro_vp9_decoded_buffer_info vp9;
351 struct hantro_av1_decoded_buffer_info av1;
352 };
353};
354
355/* Logging helpers */
356
357/**
358 * DOC: hantro_debug: Module parameter to control level of debugging messages.
359 *
360 * Level of debugging messages can be controlled by bits of
361 * module parameter called "debug". Meaning of particular
362 * bits is as follows:
363 *
364 * bit 0 - global information: mode, size, init, release
365 * bit 1 - each run start/result information
366 * bit 2 - contents of small controls from userspace
367 * bit 3 - contents of big controls from userspace
368 * bit 4 - detail fmt, ctrl, buffer q/dq information
369 * bit 5 - detail function enter/leave trace information
370 * bit 6 - register write/read information
371 */
372extern int hantro_debug;
373
374#define vpu_debug(level, fmt, args...) \
375 do { \
376 if (hantro_debug & BIT(level)) \
377 pr_info("%s:%d: " fmt, \
378 __func__, __LINE__, ##args); \
379 } while (0)
380
381#define vpu_err(fmt, args...) \
382 pr_err("%s:%d: " fmt, __func__, __LINE__, ##args)
383
384/* Structure access helpers. */
385static __always_inline struct hantro_ctx *file_to_ctx(struct file *filp)
386{
387 return container_of(file_to_v4l2_fh(filp), struct hantro_ctx, fh);
388}
389
390/* Register accessors. */
391static __always_inline void vepu_write_relaxed(struct hantro_dev *vpu,
392 u32 val, u32 reg)
393{
394 vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
395 writel_relaxed(val, vpu->enc_base + reg);
396}
397
398static __always_inline void vepu_write(struct hantro_dev *vpu, u32 val, u32 reg)
399{
400 vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
401 writel(val, addr: vpu->enc_base + reg);
402}
403
404static __always_inline u32 vepu_read(struct hantro_dev *vpu, u32 reg)
405{
406 u32 val = readl(addr: vpu->enc_base + reg);
407
408 vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
409 return val;
410}
411
412static __always_inline void vdpu_write_relaxed(struct hantro_dev *vpu,
413 u32 val, u32 reg)
414{
415 vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
416 writel_relaxed(val, vpu->dec_base + reg);
417}
418
419static __always_inline void vdpu_write(struct hantro_dev *vpu, u32 val, u32 reg)
420{
421 vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
422 writel(val, addr: vpu->dec_base + reg);
423}
424
425static __always_inline void hantro_write_addr(struct hantro_dev *vpu,
426 unsigned long offset,
427 dma_addr_t addr)
428{
429 vdpu_write(vpu, val: addr & 0xffffffff, reg: offset);
430}
431
432static __always_inline u32 vdpu_read(struct hantro_dev *vpu, u32 reg)
433{
434 u32 val = readl(addr: vpu->dec_base + reg);
435
436 vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
437 return val;
438}
439
440static __always_inline u32 vdpu_read_mask(struct hantro_dev *vpu,
441 const struct hantro_reg *reg,
442 u32 val)
443{
444 u32 v;
445
446 v = vdpu_read(vpu, reg: reg->base);
447 v &= ~(reg->mask << reg->shift);
448 v |= ((val & reg->mask) << reg->shift);
449 return v;
450}
451
452static __always_inline void hantro_reg_write(struct hantro_dev *vpu,
453 const struct hantro_reg *reg,
454 u32 val)
455{
456 vdpu_write(vpu, val: vdpu_read_mask(vpu, reg, val), reg: reg->base);
457}
458
459static __always_inline void hantro_reg_write_relaxed(struct hantro_dev *vpu,
460 const struct hantro_reg *reg,
461 u32 val)
462{
463 vdpu_write_relaxed(vpu, val: vdpu_read_mask(vpu, reg, val), reg: reg->base);
464}
465
466void *hantro_get_ctrl(struct hantro_ctx *ctx, u32 id);
467dma_addr_t hantro_get_ref(struct hantro_ctx *ctx, u64 ts);
468
469static inline struct vb2_v4l2_buffer *
470hantro_get_src_buf(struct hantro_ctx *ctx)
471{
472 return v4l2_m2m_next_src_buf(m2m_ctx: ctx->fh.m2m_ctx);
473}
474
475static inline struct vb2_v4l2_buffer *
476hantro_get_dst_buf(struct hantro_ctx *ctx)
477{
478 return v4l2_m2m_next_dst_buf(m2m_ctx: ctx->fh.m2m_ctx);
479}
480
481bool hantro_needs_postproc(const struct hantro_ctx *ctx,
482 const struct hantro_fmt *fmt);
483
484dma_addr_t
485hantro_postproc_get_dec_buf_addr(struct hantro_ctx *ctx, int index);
486
487static inline dma_addr_t
488hantro_get_dec_buf_addr(struct hantro_ctx *ctx, struct vb2_buffer *vb)
489{
490 if (hantro_needs_postproc(ctx, fmt: ctx->vpu_dst_fmt))
491 return hantro_postproc_get_dec_buf_addr(ctx, index: vb->index);
492 return vb2_dma_contig_plane_dma_addr(vb, plane_no: 0);
493}
494
495static inline struct hantro_decoded_buffer *
496vb2_to_hantro_decoded_buf(struct vb2_buffer *buf)
497{
498 return container_of(buf, struct hantro_decoded_buffer, base.vb.vb2_buf);
499}
500
501void hantro_postproc_disable(struct hantro_ctx *ctx);
502void hantro_postproc_enable(struct hantro_ctx *ctx);
503int hantro_postproc_init(struct hantro_ctx *ctx);
504void hantro_postproc_free(struct hantro_ctx *ctx);
505int hanto_postproc_enum_framesizes(struct hantro_ctx *ctx,
506 struct v4l2_frmsizeenum *fsize);
507
508#endif /* HANTRO_H_ */
509

source code of linux/drivers/media/platform/verisilicon/hantro.h