1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * lpc_ich.c - LPC interface for Intel ICH |
4 | * |
5 | * LPC bridge function of the Intel ICH contains many other |
6 | * functional units, such as Interrupt controllers, Timers, |
7 | * Power Management, System Management, GPIO, RTC, and LPC |
8 | * Configuration Registers. |
9 | * |
10 | * This driver is derived from lpc_sch. |
11 | * |
12 | * Copyright (c) 2017, 2021-2022 Intel Corporation |
13 | * Copyright (c) 2011 Extreme Engineering Solution, Inc. |
14 | * Author: Aaron Sierra <asierra@xes-inc.com> |
15 | * |
16 | * This driver supports the following I/O Controller hubs: |
17 | * (See the intel documentation on http://developer.intel.com.) |
18 | * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO) |
19 | * document number 290687-002, 298242-027: 82801BA (ICH2) |
20 | * document number 290733-003, 290739-013: 82801CA (ICH3-S) |
21 | * document number 290716-001, 290718-007: 82801CAM (ICH3-M) |
22 | * document number 290744-001, 290745-025: 82801DB (ICH4) |
23 | * document number 252337-001, 252663-008: 82801DBM (ICH4-M) |
24 | * document number 273599-001, 273645-002: 82801E (C-ICH) |
25 | * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R) |
26 | * document number 300641-004, 300884-013: 6300ESB |
27 | * document number 301473-002, 301474-026: 82801F (ICH6) |
28 | * document number 313082-001, 313075-006: 631xESB, 632xESB |
29 | * document number 307013-003, 307014-024: 82801G (ICH7) |
30 | * document number 322896-001, 322897-001: NM10 |
31 | * document number 313056-003, 313057-017: 82801H (ICH8) |
32 | * document number 316972-004, 316973-012: 82801I (ICH9) |
33 | * document number 319973-002, 319974-002: 82801J (ICH10) |
34 | * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH) |
35 | * document number 320066-003, 320257-008: EP80597 (IICH) |
36 | * document number 324645-001, 324646-001: Cougar Point (CPT) |
37 | */ |
38 | |
39 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
40 | |
41 | #include <linux/align.h> |
42 | #include <linux/kernel.h> |
43 | #include <linux/module.h> |
44 | #include <linux/errno.h> |
45 | #include <linux/acpi.h> |
46 | #include <linux/pci.h> |
47 | #include <linux/pinctrl/pinctrl.h> |
48 | #include <linux/mfd/core.h> |
49 | #include <linux/mfd/lpc_ich.h> |
50 | #include <linux/platform_data/itco_wdt.h> |
51 | #include <linux/platform_data/x86/p2sb.h> |
52 | |
53 | #define ACPIBASE 0x40 |
54 | #define ACPIBASE_GPE_OFF 0x28 |
55 | #define ACPIBASE_GPE_END 0x2f |
56 | #define ACPIBASE_SMI_OFF 0x30 |
57 | #define ACPIBASE_SMI_END 0x33 |
58 | #define ACPIBASE_PMC_OFF 0x08 |
59 | #define ACPIBASE_PMC_END 0x0c |
60 | #define ACPIBASE_TCO_OFF 0x60 |
61 | #define ACPIBASE_TCO_END 0x7f |
62 | #define ACPICTRL_PMCBASE 0x44 |
63 | |
64 | #define ACPIBASE_GCS_OFF 0x3410 |
65 | #define ACPIBASE_GCS_END 0x3414 |
66 | |
67 | #define SPIBASE_BYT 0x54 |
68 | #define SPIBASE_BYT_SZ 512 |
69 | #define SPIBASE_BYT_EN BIT(1) |
70 | #define BYT_BCR 0xfc |
71 | #define BYT_BCR_WPD BIT(0) |
72 | |
73 | #define SPIBASE_LPT 0x3800 |
74 | #define SPIBASE_LPT_SZ 512 |
75 | #define BCR 0xdc |
76 | #define BCR_WPD BIT(0) |
77 | |
78 | #define GPIOBASE_ICH0 0x58 |
79 | #define GPIOCTRL_ICH0 0x5C |
80 | #define GPIOBASE_ICH6 0x48 |
81 | #define GPIOCTRL_ICH6 0x4C |
82 | |
83 | #define RCBABASE 0xf0 |
84 | |
85 | #define wdt_io_res(i) wdt_res(0, i) |
86 | #define wdt_mem_res(i) wdt_res(ICH_RES_MEM_OFF, i) |
87 | #define wdt_res(b, i) (&wdt_ich_res[(b) + (i)]) |
88 | |
89 | static struct resource wdt_ich_res[] = { |
90 | /* ACPI - TCO */ |
91 | { |
92 | .flags = IORESOURCE_IO, |
93 | }, |
94 | /* ACPI - SMI */ |
95 | { |
96 | .flags = IORESOURCE_IO, |
97 | }, |
98 | /* GCS or PMC */ |
99 | { |
100 | .flags = IORESOURCE_MEM, |
101 | }, |
102 | }; |
103 | |
104 | static struct resource gpio_ich_res[] = { |
105 | /* GPIO */ |
106 | { |
107 | .flags = IORESOURCE_IO, |
108 | }, |
109 | /* ACPI - GPE0 */ |
110 | { |
111 | .flags = IORESOURCE_IO, |
112 | }, |
113 | }; |
114 | |
115 | static struct resource intel_spi_res[] = { |
116 | { |
117 | .flags = IORESOURCE_MEM, |
118 | } |
119 | }; |
120 | |
121 | static struct mfd_cell lpc_ich_wdt_cell = { |
122 | .name = "iTCO_wdt" , |
123 | .num_resources = ARRAY_SIZE(wdt_ich_res), |
124 | .resources = wdt_ich_res, |
125 | .ignore_resource_conflicts = true, |
126 | }; |
127 | |
128 | static struct mfd_cell lpc_ich_gpio_cell = { |
129 | .name = "gpio_ich" , |
130 | .num_resources = ARRAY_SIZE(gpio_ich_res), |
131 | .resources = gpio_ich_res, |
132 | .ignore_resource_conflicts = true, |
133 | }; |
134 | |
135 | #define INTEL_GPIO_RESOURCE_SIZE 0x1000 |
136 | |
137 | struct lpc_ich_gpio_info { |
138 | const char *hid; |
139 | const struct mfd_cell *devices; |
140 | size_t nr_devices; |
141 | struct resource **resources; |
142 | size_t nr_resources; |
143 | const resource_size_t *offsets; |
144 | }; |
145 | |
146 | #define APL_GPIO_NORTH 0 |
147 | #define APL_GPIO_NORTHWEST 1 |
148 | #define APL_GPIO_WEST 2 |
149 | #define APL_GPIO_SOUTHWEST 3 |
150 | |
151 | #define APL_GPIO_NR_DEVICES 4 |
152 | #define APL_GPIO_NR_RESOURCES 4 |
153 | |
154 | /* Offset data for Apollo Lake GPIO controllers */ |
155 | static const resource_size_t apl_gpio_offsets[APL_GPIO_NR_RESOURCES] = { |
156 | [APL_GPIO_NORTH] = 0xc50000, |
157 | [APL_GPIO_NORTHWEST] = 0xc40000, |
158 | [APL_GPIO_WEST] = 0xc70000, |
159 | [APL_GPIO_SOUTHWEST] = 0xc00000, |
160 | }; |
161 | |
162 | #define APL_GPIO_IRQ 14 |
163 | |
164 | static struct resource apl_gpio_resources[APL_GPIO_NR_DEVICES][2] = { |
165 | [APL_GPIO_NORTH] = { |
166 | DEFINE_RES_MEM(0, 0), |
167 | DEFINE_RES_IRQ(APL_GPIO_IRQ), |
168 | }, |
169 | [APL_GPIO_NORTHWEST] = { |
170 | DEFINE_RES_MEM(0, 0), |
171 | DEFINE_RES_IRQ(APL_GPIO_IRQ), |
172 | }, |
173 | [APL_GPIO_WEST] = { |
174 | DEFINE_RES_MEM(0, 0), |
175 | DEFINE_RES_IRQ(APL_GPIO_IRQ), |
176 | }, |
177 | [APL_GPIO_SOUTHWEST] = { |
178 | DEFINE_RES_MEM(0, 0), |
179 | DEFINE_RES_IRQ(APL_GPIO_IRQ), |
180 | }, |
181 | }; |
182 | |
183 | static struct resource *apl_gpio_mem_resources[APL_GPIO_NR_RESOURCES] = { |
184 | [APL_GPIO_NORTH] = &apl_gpio_resources[APL_GPIO_NORTH][0], |
185 | [APL_GPIO_NORTHWEST] = &apl_gpio_resources[APL_GPIO_NORTHWEST][0], |
186 | [APL_GPIO_WEST] = &apl_gpio_resources[APL_GPIO_WEST][0], |
187 | [APL_GPIO_SOUTHWEST] = &apl_gpio_resources[APL_GPIO_SOUTHWEST][0], |
188 | }; |
189 | |
190 | static const struct mfd_cell apl_gpio_devices[APL_GPIO_NR_DEVICES] = { |
191 | [APL_GPIO_NORTH] = { |
192 | .name = "apollolake-pinctrl" , |
193 | .id = APL_GPIO_NORTH, |
194 | .num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_NORTH]), |
195 | .resources = apl_gpio_resources[APL_GPIO_NORTH], |
196 | .ignore_resource_conflicts = true, |
197 | }, |
198 | [APL_GPIO_NORTHWEST] = { |
199 | .name = "apollolake-pinctrl" , |
200 | .id = APL_GPIO_NORTHWEST, |
201 | .num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_NORTHWEST]), |
202 | .resources = apl_gpio_resources[APL_GPIO_NORTHWEST], |
203 | .ignore_resource_conflicts = true, |
204 | }, |
205 | [APL_GPIO_WEST] = { |
206 | .name = "apollolake-pinctrl" , |
207 | .id = APL_GPIO_WEST, |
208 | .num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_WEST]), |
209 | .resources = apl_gpio_resources[APL_GPIO_WEST], |
210 | .ignore_resource_conflicts = true, |
211 | }, |
212 | [APL_GPIO_SOUTHWEST] = { |
213 | .name = "apollolake-pinctrl" , |
214 | .id = APL_GPIO_SOUTHWEST, |
215 | .num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_SOUTHWEST]), |
216 | .resources = apl_gpio_resources[APL_GPIO_SOUTHWEST], |
217 | .ignore_resource_conflicts = true, |
218 | }, |
219 | }; |
220 | |
221 | static const struct lpc_ich_gpio_info apl_gpio_info = { |
222 | .hid = "INT3452" , |
223 | .devices = apl_gpio_devices, |
224 | .nr_devices = ARRAY_SIZE(apl_gpio_devices), |
225 | .resources = apl_gpio_mem_resources, |
226 | .nr_resources = ARRAY_SIZE(apl_gpio_mem_resources), |
227 | .offsets = apl_gpio_offsets, |
228 | }; |
229 | |
230 | #define DNV_GPIO_NORTH 0 |
231 | #define DNV_GPIO_SOUTH 1 |
232 | |
233 | #define DNV_GPIO_NR_DEVICES 1 |
234 | #define DNV_GPIO_NR_RESOURCES 2 |
235 | |
236 | /* Offset data for Denverton GPIO controllers */ |
237 | static const resource_size_t dnv_gpio_offsets[DNV_GPIO_NR_RESOURCES] = { |
238 | [DNV_GPIO_NORTH] = 0xc20000, |
239 | [DNV_GPIO_SOUTH] = 0xc50000, |
240 | }; |
241 | |
242 | #define DNV_GPIO_IRQ 14 |
243 | |
244 | static struct resource dnv_gpio_resources[DNV_GPIO_NR_RESOURCES + 1] = { |
245 | [DNV_GPIO_NORTH] = DEFINE_RES_MEM(0, 0), |
246 | [DNV_GPIO_SOUTH] = DEFINE_RES_MEM(0, 0), |
247 | DEFINE_RES_IRQ(DNV_GPIO_IRQ), |
248 | }; |
249 | |
250 | static struct resource *dnv_gpio_mem_resources[DNV_GPIO_NR_RESOURCES] = { |
251 | [DNV_GPIO_NORTH] = &dnv_gpio_resources[DNV_GPIO_NORTH], |
252 | [DNV_GPIO_SOUTH] = &dnv_gpio_resources[DNV_GPIO_SOUTH], |
253 | }; |
254 | |
255 | static const struct mfd_cell dnv_gpio_devices[DNV_GPIO_NR_DEVICES] = { |
256 | { |
257 | .name = "denverton-pinctrl" , |
258 | .num_resources = ARRAY_SIZE(dnv_gpio_resources), |
259 | .resources = dnv_gpio_resources, |
260 | .ignore_resource_conflicts = true, |
261 | }, |
262 | }; |
263 | |
264 | static const struct lpc_ich_gpio_info dnv_gpio_info = { |
265 | .hid = "INTC3000" , |
266 | .devices = dnv_gpio_devices, |
267 | .nr_devices = ARRAY_SIZE(dnv_gpio_devices), |
268 | .resources = dnv_gpio_mem_resources, |
269 | .nr_resources = ARRAY_SIZE(dnv_gpio_mem_resources), |
270 | .offsets = dnv_gpio_offsets, |
271 | }; |
272 | |
273 | static struct mfd_cell lpc_ich_spi_cell = { |
274 | .name = "intel-spi" , |
275 | .num_resources = ARRAY_SIZE(intel_spi_res), |
276 | .resources = intel_spi_res, |
277 | .ignore_resource_conflicts = true, |
278 | }; |
279 | |
280 | /* chipset related info */ |
281 | enum lpc_chipsets { |
282 | LPC_ICH = 0, /* ICH */ |
283 | LPC_ICH0, /* ICH0 */ |
284 | LPC_ICH2, /* ICH2 */ |
285 | LPC_ICH2M, /* ICH2-M */ |
286 | LPC_ICH3, /* ICH3-S */ |
287 | LPC_ICH3M, /* ICH3-M */ |
288 | LPC_ICH4, /* ICH4 */ |
289 | LPC_ICH4M, /* ICH4-M */ |
290 | LPC_CICH, /* C-ICH */ |
291 | LPC_ICH5, /* ICH5 & ICH5R */ |
292 | LPC_6300ESB, /* 6300ESB */ |
293 | LPC_ICH6, /* ICH6 & ICH6R */ |
294 | LPC_ICH6M, /* ICH6-M */ |
295 | LPC_ICH6W, /* ICH6W & ICH6RW */ |
296 | LPC_631XESB, /* 631xESB/632xESB */ |
297 | LPC_ICH7, /* ICH7 & ICH7R */ |
298 | LPC_ICH7DH, /* ICH7DH */ |
299 | LPC_ICH7M, /* ICH7-M & ICH7-U */ |
300 | LPC_ICH7MDH, /* ICH7-M DH */ |
301 | LPC_NM10, /* NM10 */ |
302 | LPC_ICH8, /* ICH8 & ICH8R */ |
303 | LPC_ICH8DH, /* ICH8DH */ |
304 | LPC_ICH8DO, /* ICH8DO */ |
305 | LPC_ICH8M, /* ICH8M */ |
306 | LPC_ICH8ME, /* ICH8M-E */ |
307 | LPC_ICH9, /* ICH9 */ |
308 | LPC_ICH9R, /* ICH9R */ |
309 | LPC_ICH9DH, /* ICH9DH */ |
310 | LPC_ICH9DO, /* ICH9DO */ |
311 | LPC_ICH9M, /* ICH9M */ |
312 | LPC_ICH9ME, /* ICH9M-E */ |
313 | LPC_ICH10, /* ICH10 */ |
314 | LPC_ICH10R, /* ICH10R */ |
315 | LPC_ICH10D, /* ICH10D */ |
316 | LPC_ICH10DO, /* ICH10DO */ |
317 | LPC_PCH, /* PCH Desktop Full Featured */ |
318 | LPC_PCHM, /* PCH Mobile Full Featured */ |
319 | LPC_P55, /* P55 */ |
320 | LPC_PM55, /* PM55 */ |
321 | LPC_H55, /* H55 */ |
322 | LPC_QM57, /* QM57 */ |
323 | LPC_H57, /* H57 */ |
324 | LPC_HM55, /* HM55 */ |
325 | LPC_Q57, /* Q57 */ |
326 | LPC_HM57, /* HM57 */ |
327 | LPC_PCHMSFF, /* PCH Mobile SFF Full Featured */ |
328 | LPC_QS57, /* QS57 */ |
329 | LPC_3400, /* 3400 */ |
330 | LPC_3420, /* 3420 */ |
331 | LPC_3450, /* 3450 */ |
332 | LPC_EP80579, /* EP80579 */ |
333 | LPC_CPT, /* Cougar Point */ |
334 | LPC_CPTD, /* Cougar Point Desktop */ |
335 | LPC_CPTM, /* Cougar Point Mobile */ |
336 | LPC_PBG, /* Patsburg */ |
337 | LPC_DH89XXCC, /* DH89xxCC */ |
338 | LPC_PPT, /* Panther Point */ |
339 | LPC_LPT, /* Lynx Point */ |
340 | LPC_LPT_LP, /* Lynx Point-LP */ |
341 | LPC_WBG, /* Wellsburg */ |
342 | LPC_AVN, /* Avoton SoC */ |
343 | LPC_BAYTRAIL, /* Bay Trail SoC */ |
344 | LPC_COLETO, /* Coleto Creek */ |
345 | LPC_WPT_LP, /* Wildcat Point-LP */ |
346 | LPC_BRASWELL, /* Braswell SoC */ |
347 | LPC_LEWISBURG, /* Lewisburg */ |
348 | LPC_9S, /* 9 Series */ |
349 | LPC_APL, /* Apollo Lake SoC */ |
350 | LPC_DNV, /* Denverton SoC */ |
351 | LPC_GLK, /* Gemini Lake SoC */ |
352 | LPC_COUGARMOUNTAIN,/* Cougar Mountain SoC*/ |
353 | }; |
354 | |
355 | struct lpc_ich_priv { |
356 | enum lpc_chipsets chipset; |
357 | |
358 | int abase; /* ACPI base */ |
359 | int actrl_pbase; /* ACPI control or PMC base */ |
360 | int gbase; /* GPIO base */ |
361 | int gctrl; /* GPIO control */ |
362 | |
363 | int abase_save; /* Cached ACPI base value */ |
364 | int actrl_pbase_save; /* Cached ACPI control or PMC base value */ |
365 | int gctrl_save; /* Cached GPIO control value */ |
366 | }; |
367 | |
368 | static struct lpc_ich_info lpc_chipset_info[] = { |
369 | [LPC_ICH] = { |
370 | .name = "ICH" , |
371 | .iTCO_version = 1, |
372 | }, |
373 | [LPC_ICH0] = { |
374 | .name = "ICH0" , |
375 | .iTCO_version = 1, |
376 | }, |
377 | [LPC_ICH2] = { |
378 | .name = "ICH2" , |
379 | .iTCO_version = 1, |
380 | }, |
381 | [LPC_ICH2M] = { |
382 | .name = "ICH2-M" , |
383 | .iTCO_version = 1, |
384 | }, |
385 | [LPC_ICH3] = { |
386 | .name = "ICH3-S" , |
387 | .iTCO_version = 1, |
388 | }, |
389 | [LPC_ICH3M] = { |
390 | .name = "ICH3-M" , |
391 | .iTCO_version = 1, |
392 | }, |
393 | [LPC_ICH4] = { |
394 | .name = "ICH4" , |
395 | .iTCO_version = 1, |
396 | }, |
397 | [LPC_ICH4M] = { |
398 | .name = "ICH4-M" , |
399 | .iTCO_version = 1, |
400 | }, |
401 | [LPC_CICH] = { |
402 | .name = "C-ICH" , |
403 | .iTCO_version = 1, |
404 | }, |
405 | [LPC_ICH5] = { |
406 | .name = "ICH5 or ICH5R" , |
407 | .iTCO_version = 1, |
408 | }, |
409 | [LPC_6300ESB] = { |
410 | .name = "6300ESB" , |
411 | .iTCO_version = 1, |
412 | }, |
413 | [LPC_ICH6] = { |
414 | .name = "ICH6 or ICH6R" , |
415 | .iTCO_version = 2, |
416 | .gpio_version = ICH_V6_GPIO, |
417 | }, |
418 | [LPC_ICH6M] = { |
419 | .name = "ICH6-M" , |
420 | .iTCO_version = 2, |
421 | .gpio_version = ICH_V6_GPIO, |
422 | }, |
423 | [LPC_ICH6W] = { |
424 | .name = "ICH6W or ICH6RW" , |
425 | .iTCO_version = 2, |
426 | .gpio_version = ICH_V6_GPIO, |
427 | }, |
428 | [LPC_631XESB] = { |
429 | .name = "631xESB/632xESB" , |
430 | .iTCO_version = 2, |
431 | .gpio_version = ICH_V6_GPIO, |
432 | }, |
433 | [LPC_ICH7] = { |
434 | .name = "ICH7 or ICH7R" , |
435 | .iTCO_version = 2, |
436 | .gpio_version = ICH_V7_GPIO, |
437 | }, |
438 | [LPC_ICH7DH] = { |
439 | .name = "ICH7DH" , |
440 | .iTCO_version = 2, |
441 | .gpio_version = ICH_V7_GPIO, |
442 | }, |
443 | [LPC_ICH7M] = { |
444 | .name = "ICH7-M or ICH7-U" , |
445 | .iTCO_version = 2, |
446 | .gpio_version = ICH_V7_GPIO, |
447 | }, |
448 | [LPC_ICH7MDH] = { |
449 | .name = "ICH7-M DH" , |
450 | .iTCO_version = 2, |
451 | .gpio_version = ICH_V7_GPIO, |
452 | }, |
453 | [LPC_NM10] = { |
454 | .name = "NM10" , |
455 | .iTCO_version = 2, |
456 | .gpio_version = ICH_V7_GPIO, |
457 | }, |
458 | [LPC_ICH8] = { |
459 | .name = "ICH8 or ICH8R" , |
460 | .iTCO_version = 2, |
461 | .gpio_version = ICH_V7_GPIO, |
462 | }, |
463 | [LPC_ICH8DH] = { |
464 | .name = "ICH8DH" , |
465 | .iTCO_version = 2, |
466 | .gpio_version = ICH_V7_GPIO, |
467 | }, |
468 | [LPC_ICH8DO] = { |
469 | .name = "ICH8DO" , |
470 | .iTCO_version = 2, |
471 | .gpio_version = ICH_V7_GPIO, |
472 | }, |
473 | [LPC_ICH8M] = { |
474 | .name = "ICH8M" , |
475 | .iTCO_version = 2, |
476 | .gpio_version = ICH_V7_GPIO, |
477 | }, |
478 | [LPC_ICH8ME] = { |
479 | .name = "ICH8M-E" , |
480 | .iTCO_version = 2, |
481 | .gpio_version = ICH_V7_GPIO, |
482 | }, |
483 | [LPC_ICH9] = { |
484 | .name = "ICH9" , |
485 | .iTCO_version = 2, |
486 | .gpio_version = ICH_V9_GPIO, |
487 | }, |
488 | [LPC_ICH9R] = { |
489 | .name = "ICH9R" , |
490 | .iTCO_version = 2, |
491 | .gpio_version = ICH_V9_GPIO, |
492 | }, |
493 | [LPC_ICH9DH] = { |
494 | .name = "ICH9DH" , |
495 | .iTCO_version = 2, |
496 | .gpio_version = ICH_V9_GPIO, |
497 | }, |
498 | [LPC_ICH9DO] = { |
499 | .name = "ICH9DO" , |
500 | .iTCO_version = 2, |
501 | .gpio_version = ICH_V9_GPIO, |
502 | }, |
503 | [LPC_ICH9M] = { |
504 | .name = "ICH9M" , |
505 | .iTCO_version = 2, |
506 | .gpio_version = ICH_V9_GPIO, |
507 | }, |
508 | [LPC_ICH9ME] = { |
509 | .name = "ICH9M-E" , |
510 | .iTCO_version = 2, |
511 | .gpio_version = ICH_V9_GPIO, |
512 | }, |
513 | [LPC_ICH10] = { |
514 | .name = "ICH10" , |
515 | .iTCO_version = 2, |
516 | .gpio_version = ICH_V10CONS_GPIO, |
517 | }, |
518 | [LPC_ICH10R] = { |
519 | .name = "ICH10R" , |
520 | .iTCO_version = 2, |
521 | .gpio_version = ICH_V10CONS_GPIO, |
522 | }, |
523 | [LPC_ICH10D] = { |
524 | .name = "ICH10D" , |
525 | .iTCO_version = 2, |
526 | .gpio_version = ICH_V10CORP_GPIO, |
527 | }, |
528 | [LPC_ICH10DO] = { |
529 | .name = "ICH10DO" , |
530 | .iTCO_version = 2, |
531 | .gpio_version = ICH_V10CORP_GPIO, |
532 | }, |
533 | [LPC_PCH] = { |
534 | .name = "PCH Desktop Full Featured" , |
535 | .iTCO_version = 2, |
536 | .gpio_version = ICH_V5_GPIO, |
537 | }, |
538 | [LPC_PCHM] = { |
539 | .name = "PCH Mobile Full Featured" , |
540 | .iTCO_version = 2, |
541 | .gpio_version = ICH_V5_GPIO, |
542 | }, |
543 | [LPC_P55] = { |
544 | .name = "P55" , |
545 | .iTCO_version = 2, |
546 | .gpio_version = ICH_V5_GPIO, |
547 | }, |
548 | [LPC_PM55] = { |
549 | .name = "PM55" , |
550 | .iTCO_version = 2, |
551 | .gpio_version = ICH_V5_GPIO, |
552 | }, |
553 | [LPC_H55] = { |
554 | .name = "H55" , |
555 | .iTCO_version = 2, |
556 | .gpio_version = ICH_V5_GPIO, |
557 | }, |
558 | [LPC_QM57] = { |
559 | .name = "QM57" , |
560 | .iTCO_version = 2, |
561 | .gpio_version = ICH_V5_GPIO, |
562 | }, |
563 | [LPC_H57] = { |
564 | .name = "H57" , |
565 | .iTCO_version = 2, |
566 | .gpio_version = ICH_V5_GPIO, |
567 | }, |
568 | [LPC_HM55] = { |
569 | .name = "HM55" , |
570 | .iTCO_version = 2, |
571 | .gpio_version = ICH_V5_GPIO, |
572 | }, |
573 | [LPC_Q57] = { |
574 | .name = "Q57" , |
575 | .iTCO_version = 2, |
576 | .gpio_version = ICH_V5_GPIO, |
577 | }, |
578 | [LPC_HM57] = { |
579 | .name = "HM57" , |
580 | .iTCO_version = 2, |
581 | .gpio_version = ICH_V5_GPIO, |
582 | }, |
583 | [LPC_PCHMSFF] = { |
584 | .name = "PCH Mobile SFF Full Featured" , |
585 | .iTCO_version = 2, |
586 | .gpio_version = ICH_V5_GPIO, |
587 | }, |
588 | [LPC_QS57] = { |
589 | .name = "QS57" , |
590 | .iTCO_version = 2, |
591 | .gpio_version = ICH_V5_GPIO, |
592 | }, |
593 | [LPC_3400] = { |
594 | .name = "3400" , |
595 | .iTCO_version = 2, |
596 | .gpio_version = ICH_V5_GPIO, |
597 | }, |
598 | [LPC_3420] = { |
599 | .name = "3420" , |
600 | .iTCO_version = 2, |
601 | .gpio_version = ICH_V5_GPIO, |
602 | }, |
603 | [LPC_3450] = { |
604 | .name = "3450" , |
605 | .iTCO_version = 2, |
606 | .gpio_version = ICH_V5_GPIO, |
607 | }, |
608 | [LPC_EP80579] = { |
609 | .name = "EP80579" , |
610 | .iTCO_version = 2, |
611 | }, |
612 | [LPC_CPT] = { |
613 | .name = "Cougar Point" , |
614 | .iTCO_version = 2, |
615 | .gpio_version = ICH_V5_GPIO, |
616 | }, |
617 | [LPC_CPTD] = { |
618 | .name = "Cougar Point Desktop" , |
619 | .iTCO_version = 2, |
620 | .gpio_version = ICH_V5_GPIO, |
621 | }, |
622 | [LPC_CPTM] = { |
623 | .name = "Cougar Point Mobile" , |
624 | .iTCO_version = 2, |
625 | .gpio_version = ICH_V5_GPIO, |
626 | }, |
627 | [LPC_PBG] = { |
628 | .name = "Patsburg" , |
629 | .iTCO_version = 2, |
630 | }, |
631 | [LPC_DH89XXCC] = { |
632 | .name = "DH89xxCC" , |
633 | .iTCO_version = 2, |
634 | .gpio_version = ICH_V5_GPIO, |
635 | }, |
636 | [LPC_PPT] = { |
637 | .name = "Panther Point" , |
638 | .iTCO_version = 2, |
639 | .gpio_version = ICH_V5_GPIO, |
640 | }, |
641 | [LPC_LPT] = { |
642 | .name = "Lynx Point" , |
643 | .iTCO_version = 2, |
644 | .gpio_version = ICH_V5_GPIO, |
645 | .spi_type = INTEL_SPI_LPT, |
646 | }, |
647 | [LPC_LPT_LP] = { |
648 | .name = "Lynx Point_LP" , |
649 | .iTCO_version = 2, |
650 | .spi_type = INTEL_SPI_LPT, |
651 | }, |
652 | [LPC_WBG] = { |
653 | .name = "Wellsburg" , |
654 | .iTCO_version = 2, |
655 | }, |
656 | [LPC_AVN] = { |
657 | .name = "Avoton SoC" , |
658 | .iTCO_version = 3, |
659 | .gpio_version = AVOTON_GPIO, |
660 | .spi_type = INTEL_SPI_BYT, |
661 | }, |
662 | [LPC_BAYTRAIL] = { |
663 | .name = "Bay Trail SoC" , |
664 | .iTCO_version = 3, |
665 | .spi_type = INTEL_SPI_BYT, |
666 | }, |
667 | [LPC_COLETO] = { |
668 | .name = "Coleto Creek" , |
669 | .iTCO_version = 2, |
670 | }, |
671 | [LPC_WPT_LP] = { |
672 | .name = "Wildcat Point_LP" , |
673 | .iTCO_version = 2, |
674 | .spi_type = INTEL_SPI_LPT, |
675 | }, |
676 | [LPC_BRASWELL] = { |
677 | .name = "Braswell SoC" , |
678 | .iTCO_version = 3, |
679 | .spi_type = INTEL_SPI_BYT, |
680 | }, |
681 | [LPC_LEWISBURG] = { |
682 | .name = "Lewisburg" , |
683 | .iTCO_version = 2, |
684 | }, |
685 | [LPC_9S] = { |
686 | .name = "9 Series" , |
687 | .iTCO_version = 2, |
688 | .gpio_version = ICH_V5_GPIO, |
689 | }, |
690 | [LPC_APL] = { |
691 | .name = "Apollo Lake SoC" , |
692 | .iTCO_version = 5, |
693 | .gpio_info = &apl_gpio_info, |
694 | .spi_type = INTEL_SPI_BXT, |
695 | }, |
696 | [LPC_DNV] = { |
697 | .name = "Denverton SoC" , |
698 | .gpio_info = &dnv_gpio_info, |
699 | }, |
700 | [LPC_GLK] = { |
701 | .name = "Gemini Lake SoC" , |
702 | .spi_type = INTEL_SPI_BXT, |
703 | }, |
704 | [LPC_COUGARMOUNTAIN] = { |
705 | .name = "Cougar Mountain SoC" , |
706 | .iTCO_version = 3, |
707 | }, |
708 | }; |
709 | |
710 | /* |
711 | * This data only exists for exporting the supported PCI ids |
712 | * via MODULE_DEVICE_TABLE. We do not actually register a |
713 | * pci_driver, because the I/O Controller Hub has also other |
714 | * functions that probably will be registered by other drivers. |
715 | */ |
716 | static const struct pci_device_id lpc_ich_ids[] = { |
717 | { PCI_VDEVICE(INTEL, 0x0f1c), LPC_BAYTRAIL}, |
718 | { PCI_VDEVICE(INTEL, 0x19dc), LPC_DNV}, |
719 | { PCI_VDEVICE(INTEL, 0x1c41), LPC_CPT}, |
720 | { PCI_VDEVICE(INTEL, 0x1c42), LPC_CPTD}, |
721 | { PCI_VDEVICE(INTEL, 0x1c43), LPC_CPTM}, |
722 | { PCI_VDEVICE(INTEL, 0x1c44), LPC_CPT}, |
723 | { PCI_VDEVICE(INTEL, 0x1c45), LPC_CPT}, |
724 | { PCI_VDEVICE(INTEL, 0x1c46), LPC_CPT}, |
725 | { PCI_VDEVICE(INTEL, 0x1c47), LPC_CPT}, |
726 | { PCI_VDEVICE(INTEL, 0x1c48), LPC_CPT}, |
727 | { PCI_VDEVICE(INTEL, 0x1c49), LPC_CPT}, |
728 | { PCI_VDEVICE(INTEL, 0x1c4a), LPC_CPT}, |
729 | { PCI_VDEVICE(INTEL, 0x1c4b), LPC_CPT}, |
730 | { PCI_VDEVICE(INTEL, 0x1c4c), LPC_CPT}, |
731 | { PCI_VDEVICE(INTEL, 0x1c4d), LPC_CPT}, |
732 | { PCI_VDEVICE(INTEL, 0x1c4e), LPC_CPT}, |
733 | { PCI_VDEVICE(INTEL, 0x1c4f), LPC_CPT}, |
734 | { PCI_VDEVICE(INTEL, 0x1c50), LPC_CPT}, |
735 | { PCI_VDEVICE(INTEL, 0x1c51), LPC_CPT}, |
736 | { PCI_VDEVICE(INTEL, 0x1c52), LPC_CPT}, |
737 | { PCI_VDEVICE(INTEL, 0x1c53), LPC_CPT}, |
738 | { PCI_VDEVICE(INTEL, 0x1c54), LPC_CPT}, |
739 | { PCI_VDEVICE(INTEL, 0x1c55), LPC_CPT}, |
740 | { PCI_VDEVICE(INTEL, 0x1c56), LPC_CPT}, |
741 | { PCI_VDEVICE(INTEL, 0x1c57), LPC_CPT}, |
742 | { PCI_VDEVICE(INTEL, 0x1c58), LPC_CPT}, |
743 | { PCI_VDEVICE(INTEL, 0x1c59), LPC_CPT}, |
744 | { PCI_VDEVICE(INTEL, 0x1c5a), LPC_CPT}, |
745 | { PCI_VDEVICE(INTEL, 0x1c5b), LPC_CPT}, |
746 | { PCI_VDEVICE(INTEL, 0x1c5c), LPC_CPT}, |
747 | { PCI_VDEVICE(INTEL, 0x1c5d), LPC_CPT}, |
748 | { PCI_VDEVICE(INTEL, 0x1c5e), LPC_CPT}, |
749 | { PCI_VDEVICE(INTEL, 0x1c5f), LPC_CPT}, |
750 | { PCI_VDEVICE(INTEL, 0x1d40), LPC_PBG}, |
751 | { PCI_VDEVICE(INTEL, 0x1d41), LPC_PBG}, |
752 | { PCI_VDEVICE(INTEL, 0x1e40), LPC_PPT}, |
753 | { PCI_VDEVICE(INTEL, 0x1e41), LPC_PPT}, |
754 | { PCI_VDEVICE(INTEL, 0x1e42), LPC_PPT}, |
755 | { PCI_VDEVICE(INTEL, 0x1e43), LPC_PPT}, |
756 | { PCI_VDEVICE(INTEL, 0x1e44), LPC_PPT}, |
757 | { PCI_VDEVICE(INTEL, 0x1e45), LPC_PPT}, |
758 | { PCI_VDEVICE(INTEL, 0x1e46), LPC_PPT}, |
759 | { PCI_VDEVICE(INTEL, 0x1e47), LPC_PPT}, |
760 | { PCI_VDEVICE(INTEL, 0x1e48), LPC_PPT}, |
761 | { PCI_VDEVICE(INTEL, 0x1e49), LPC_PPT}, |
762 | { PCI_VDEVICE(INTEL, 0x1e4a), LPC_PPT}, |
763 | { PCI_VDEVICE(INTEL, 0x1e4b), LPC_PPT}, |
764 | { PCI_VDEVICE(INTEL, 0x1e4c), LPC_PPT}, |
765 | { PCI_VDEVICE(INTEL, 0x1e4d), LPC_PPT}, |
766 | { PCI_VDEVICE(INTEL, 0x1e4e), LPC_PPT}, |
767 | { PCI_VDEVICE(INTEL, 0x1e4f), LPC_PPT}, |
768 | { PCI_VDEVICE(INTEL, 0x1e50), LPC_PPT}, |
769 | { PCI_VDEVICE(INTEL, 0x1e51), LPC_PPT}, |
770 | { PCI_VDEVICE(INTEL, 0x1e52), LPC_PPT}, |
771 | { PCI_VDEVICE(INTEL, 0x1e53), LPC_PPT}, |
772 | { PCI_VDEVICE(INTEL, 0x1e54), LPC_PPT}, |
773 | { PCI_VDEVICE(INTEL, 0x1e55), LPC_PPT}, |
774 | { PCI_VDEVICE(INTEL, 0x1e56), LPC_PPT}, |
775 | { PCI_VDEVICE(INTEL, 0x1e57), LPC_PPT}, |
776 | { PCI_VDEVICE(INTEL, 0x1e58), LPC_PPT}, |
777 | { PCI_VDEVICE(INTEL, 0x1e59), LPC_PPT}, |
778 | { PCI_VDEVICE(INTEL, 0x1e5a), LPC_PPT}, |
779 | { PCI_VDEVICE(INTEL, 0x1e5b), LPC_PPT}, |
780 | { PCI_VDEVICE(INTEL, 0x1e5c), LPC_PPT}, |
781 | { PCI_VDEVICE(INTEL, 0x1e5d), LPC_PPT}, |
782 | { PCI_VDEVICE(INTEL, 0x1e5e), LPC_PPT}, |
783 | { PCI_VDEVICE(INTEL, 0x1e5f), LPC_PPT}, |
784 | { PCI_VDEVICE(INTEL, 0x1f38), LPC_AVN}, |
785 | { PCI_VDEVICE(INTEL, 0x1f39), LPC_AVN}, |
786 | { PCI_VDEVICE(INTEL, 0x1f3a), LPC_AVN}, |
787 | { PCI_VDEVICE(INTEL, 0x1f3b), LPC_AVN}, |
788 | { PCI_VDEVICE(INTEL, 0x229c), LPC_BRASWELL}, |
789 | { PCI_VDEVICE(INTEL, 0x2310), LPC_DH89XXCC}, |
790 | { PCI_VDEVICE(INTEL, 0x2390), LPC_COLETO}, |
791 | { PCI_VDEVICE(INTEL, 0x2410), LPC_ICH}, |
792 | { PCI_VDEVICE(INTEL, 0x2420), LPC_ICH0}, |
793 | { PCI_VDEVICE(INTEL, 0x2440), LPC_ICH2}, |
794 | { PCI_VDEVICE(INTEL, 0x244c), LPC_ICH2M}, |
795 | { PCI_VDEVICE(INTEL, 0x2450), LPC_CICH}, |
796 | { PCI_VDEVICE(INTEL, 0x2480), LPC_ICH3}, |
797 | { PCI_VDEVICE(INTEL, 0x248c), LPC_ICH3M}, |
798 | { PCI_VDEVICE(INTEL, 0x24c0), LPC_ICH4}, |
799 | { PCI_VDEVICE(INTEL, 0x24cc), LPC_ICH4M}, |
800 | { PCI_VDEVICE(INTEL, 0x24d0), LPC_ICH5}, |
801 | { PCI_VDEVICE(INTEL, 0x25a1), LPC_6300ESB}, |
802 | { PCI_VDEVICE(INTEL, 0x2640), LPC_ICH6}, |
803 | { PCI_VDEVICE(INTEL, 0x2641), LPC_ICH6M}, |
804 | { PCI_VDEVICE(INTEL, 0x2642), LPC_ICH6W}, |
805 | { PCI_VDEVICE(INTEL, 0x2670), LPC_631XESB}, |
806 | { PCI_VDEVICE(INTEL, 0x2671), LPC_631XESB}, |
807 | { PCI_VDEVICE(INTEL, 0x2672), LPC_631XESB}, |
808 | { PCI_VDEVICE(INTEL, 0x2673), LPC_631XESB}, |
809 | { PCI_VDEVICE(INTEL, 0x2674), LPC_631XESB}, |
810 | { PCI_VDEVICE(INTEL, 0x2675), LPC_631XESB}, |
811 | { PCI_VDEVICE(INTEL, 0x2676), LPC_631XESB}, |
812 | { PCI_VDEVICE(INTEL, 0x2677), LPC_631XESB}, |
813 | { PCI_VDEVICE(INTEL, 0x2678), LPC_631XESB}, |
814 | { PCI_VDEVICE(INTEL, 0x2679), LPC_631XESB}, |
815 | { PCI_VDEVICE(INTEL, 0x267a), LPC_631XESB}, |
816 | { PCI_VDEVICE(INTEL, 0x267b), LPC_631XESB}, |
817 | { PCI_VDEVICE(INTEL, 0x267c), LPC_631XESB}, |
818 | { PCI_VDEVICE(INTEL, 0x267d), LPC_631XESB}, |
819 | { PCI_VDEVICE(INTEL, 0x267e), LPC_631XESB}, |
820 | { PCI_VDEVICE(INTEL, 0x267f), LPC_631XESB}, |
821 | { PCI_VDEVICE(INTEL, 0x27b0), LPC_ICH7DH}, |
822 | { PCI_VDEVICE(INTEL, 0x27b8), LPC_ICH7}, |
823 | { PCI_VDEVICE(INTEL, 0x27b9), LPC_ICH7M}, |
824 | { PCI_VDEVICE(INTEL, 0x27bc), LPC_NM10}, |
825 | { PCI_VDEVICE(INTEL, 0x27bd), LPC_ICH7MDH}, |
826 | { PCI_VDEVICE(INTEL, 0x2810), LPC_ICH8}, |
827 | { PCI_VDEVICE(INTEL, 0x2811), LPC_ICH8ME}, |
828 | { PCI_VDEVICE(INTEL, 0x2812), LPC_ICH8DH}, |
829 | { PCI_VDEVICE(INTEL, 0x2814), LPC_ICH8DO}, |
830 | { PCI_VDEVICE(INTEL, 0x2815), LPC_ICH8M}, |
831 | { PCI_VDEVICE(INTEL, 0x2912), LPC_ICH9DH}, |
832 | { PCI_VDEVICE(INTEL, 0x2914), LPC_ICH9DO}, |
833 | { PCI_VDEVICE(INTEL, 0x2916), LPC_ICH9R}, |
834 | { PCI_VDEVICE(INTEL, 0x2917), LPC_ICH9ME}, |
835 | { PCI_VDEVICE(INTEL, 0x2918), LPC_ICH9}, |
836 | { PCI_VDEVICE(INTEL, 0x2919), LPC_ICH9M}, |
837 | { PCI_VDEVICE(INTEL, 0x3197), LPC_GLK}, |
838 | { PCI_VDEVICE(INTEL, 0x2b9c), LPC_COUGARMOUNTAIN}, |
839 | { PCI_VDEVICE(INTEL, 0x3a14), LPC_ICH10DO}, |
840 | { PCI_VDEVICE(INTEL, 0x3a16), LPC_ICH10R}, |
841 | { PCI_VDEVICE(INTEL, 0x3a18), LPC_ICH10}, |
842 | { PCI_VDEVICE(INTEL, 0x3a1a), LPC_ICH10D}, |
843 | { PCI_VDEVICE(INTEL, 0x3b00), LPC_PCH}, |
844 | { PCI_VDEVICE(INTEL, 0x3b01), LPC_PCHM}, |
845 | { PCI_VDEVICE(INTEL, 0x3b02), LPC_P55}, |
846 | { PCI_VDEVICE(INTEL, 0x3b03), LPC_PM55}, |
847 | { PCI_VDEVICE(INTEL, 0x3b06), LPC_H55}, |
848 | { PCI_VDEVICE(INTEL, 0x3b07), LPC_QM57}, |
849 | { PCI_VDEVICE(INTEL, 0x3b08), LPC_H57}, |
850 | { PCI_VDEVICE(INTEL, 0x3b09), LPC_HM55}, |
851 | { PCI_VDEVICE(INTEL, 0x3b0a), LPC_Q57}, |
852 | { PCI_VDEVICE(INTEL, 0x3b0b), LPC_HM57}, |
853 | { PCI_VDEVICE(INTEL, 0x3b0d), LPC_PCHMSFF}, |
854 | { PCI_VDEVICE(INTEL, 0x3b0f), LPC_QS57}, |
855 | { PCI_VDEVICE(INTEL, 0x3b12), LPC_3400}, |
856 | { PCI_VDEVICE(INTEL, 0x3b14), LPC_3420}, |
857 | { PCI_VDEVICE(INTEL, 0x3b16), LPC_3450}, |
858 | { PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579}, |
859 | { PCI_VDEVICE(INTEL, 0x5ae8), LPC_APL}, |
860 | { PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT}, |
861 | { PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT}, |
862 | { PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT}, |
863 | { PCI_VDEVICE(INTEL, 0x8c43), LPC_LPT}, |
864 | { PCI_VDEVICE(INTEL, 0x8c44), LPC_LPT}, |
865 | { PCI_VDEVICE(INTEL, 0x8c45), LPC_LPT}, |
866 | { PCI_VDEVICE(INTEL, 0x8c46), LPC_LPT}, |
867 | { PCI_VDEVICE(INTEL, 0x8c47), LPC_LPT}, |
868 | { PCI_VDEVICE(INTEL, 0x8c48), LPC_LPT}, |
869 | { PCI_VDEVICE(INTEL, 0x8c49), LPC_LPT}, |
870 | { PCI_VDEVICE(INTEL, 0x8c4a), LPC_LPT}, |
871 | { PCI_VDEVICE(INTEL, 0x8c4b), LPC_LPT}, |
872 | { PCI_VDEVICE(INTEL, 0x8c4c), LPC_LPT}, |
873 | { PCI_VDEVICE(INTEL, 0x8c4d), LPC_LPT}, |
874 | { PCI_VDEVICE(INTEL, 0x8c4e), LPC_LPT}, |
875 | { PCI_VDEVICE(INTEL, 0x8c4f), LPC_LPT}, |
876 | { PCI_VDEVICE(INTEL, 0x8c50), LPC_LPT}, |
877 | { PCI_VDEVICE(INTEL, 0x8c51), LPC_LPT}, |
878 | { PCI_VDEVICE(INTEL, 0x8c52), LPC_LPT}, |
879 | { PCI_VDEVICE(INTEL, 0x8c53), LPC_LPT}, |
880 | { PCI_VDEVICE(INTEL, 0x8c54), LPC_LPT}, |
881 | { PCI_VDEVICE(INTEL, 0x8c55), LPC_LPT}, |
882 | { PCI_VDEVICE(INTEL, 0x8c56), LPC_LPT}, |
883 | { PCI_VDEVICE(INTEL, 0x8c57), LPC_LPT}, |
884 | { PCI_VDEVICE(INTEL, 0x8c58), LPC_LPT}, |
885 | { PCI_VDEVICE(INTEL, 0x8c59), LPC_LPT}, |
886 | { PCI_VDEVICE(INTEL, 0x8c5a), LPC_LPT}, |
887 | { PCI_VDEVICE(INTEL, 0x8c5b), LPC_LPT}, |
888 | { PCI_VDEVICE(INTEL, 0x8c5c), LPC_LPT}, |
889 | { PCI_VDEVICE(INTEL, 0x8c5d), LPC_LPT}, |
890 | { PCI_VDEVICE(INTEL, 0x8c5e), LPC_LPT}, |
891 | { PCI_VDEVICE(INTEL, 0x8c5f), LPC_LPT}, |
892 | { PCI_VDEVICE(INTEL, 0x8cc1), LPC_9S}, |
893 | { PCI_VDEVICE(INTEL, 0x8cc2), LPC_9S}, |
894 | { PCI_VDEVICE(INTEL, 0x8cc3), LPC_9S}, |
895 | { PCI_VDEVICE(INTEL, 0x8cc4), LPC_9S}, |
896 | { PCI_VDEVICE(INTEL, 0x8cc6), LPC_9S}, |
897 | { PCI_VDEVICE(INTEL, 0x8d40), LPC_WBG}, |
898 | { PCI_VDEVICE(INTEL, 0x8d41), LPC_WBG}, |
899 | { PCI_VDEVICE(INTEL, 0x8d42), LPC_WBG}, |
900 | { PCI_VDEVICE(INTEL, 0x8d43), LPC_WBG}, |
901 | { PCI_VDEVICE(INTEL, 0x8d44), LPC_WBG}, |
902 | { PCI_VDEVICE(INTEL, 0x8d45), LPC_WBG}, |
903 | { PCI_VDEVICE(INTEL, 0x8d46), LPC_WBG}, |
904 | { PCI_VDEVICE(INTEL, 0x8d47), LPC_WBG}, |
905 | { PCI_VDEVICE(INTEL, 0x8d48), LPC_WBG}, |
906 | { PCI_VDEVICE(INTEL, 0x8d49), LPC_WBG}, |
907 | { PCI_VDEVICE(INTEL, 0x8d4a), LPC_WBG}, |
908 | { PCI_VDEVICE(INTEL, 0x8d4b), LPC_WBG}, |
909 | { PCI_VDEVICE(INTEL, 0x8d4c), LPC_WBG}, |
910 | { PCI_VDEVICE(INTEL, 0x8d4d), LPC_WBG}, |
911 | { PCI_VDEVICE(INTEL, 0x8d4e), LPC_WBG}, |
912 | { PCI_VDEVICE(INTEL, 0x8d4f), LPC_WBG}, |
913 | { PCI_VDEVICE(INTEL, 0x8d50), LPC_WBG}, |
914 | { PCI_VDEVICE(INTEL, 0x8d51), LPC_WBG}, |
915 | { PCI_VDEVICE(INTEL, 0x8d52), LPC_WBG}, |
916 | { PCI_VDEVICE(INTEL, 0x8d53), LPC_WBG}, |
917 | { PCI_VDEVICE(INTEL, 0x8d54), LPC_WBG}, |
918 | { PCI_VDEVICE(INTEL, 0x8d55), LPC_WBG}, |
919 | { PCI_VDEVICE(INTEL, 0x8d56), LPC_WBG}, |
920 | { PCI_VDEVICE(INTEL, 0x8d57), LPC_WBG}, |
921 | { PCI_VDEVICE(INTEL, 0x8d58), LPC_WBG}, |
922 | { PCI_VDEVICE(INTEL, 0x8d59), LPC_WBG}, |
923 | { PCI_VDEVICE(INTEL, 0x8d5a), LPC_WBG}, |
924 | { PCI_VDEVICE(INTEL, 0x8d5b), LPC_WBG}, |
925 | { PCI_VDEVICE(INTEL, 0x8d5c), LPC_WBG}, |
926 | { PCI_VDEVICE(INTEL, 0x8d5d), LPC_WBG}, |
927 | { PCI_VDEVICE(INTEL, 0x8d5e), LPC_WBG}, |
928 | { PCI_VDEVICE(INTEL, 0x8d5f), LPC_WBG}, |
929 | { PCI_VDEVICE(INTEL, 0x9c40), LPC_LPT_LP}, |
930 | { PCI_VDEVICE(INTEL, 0x9c41), LPC_LPT_LP}, |
931 | { PCI_VDEVICE(INTEL, 0x9c42), LPC_LPT_LP}, |
932 | { PCI_VDEVICE(INTEL, 0x9c43), LPC_LPT_LP}, |
933 | { PCI_VDEVICE(INTEL, 0x9c44), LPC_LPT_LP}, |
934 | { PCI_VDEVICE(INTEL, 0x9c45), LPC_LPT_LP}, |
935 | { PCI_VDEVICE(INTEL, 0x9c46), LPC_LPT_LP}, |
936 | { PCI_VDEVICE(INTEL, 0x9c47), LPC_LPT_LP}, |
937 | { PCI_VDEVICE(INTEL, 0x9cc1), LPC_WPT_LP}, |
938 | { PCI_VDEVICE(INTEL, 0x9cc2), LPC_WPT_LP}, |
939 | { PCI_VDEVICE(INTEL, 0x9cc3), LPC_WPT_LP}, |
940 | { PCI_VDEVICE(INTEL, 0x9cc5), LPC_WPT_LP}, |
941 | { PCI_VDEVICE(INTEL, 0x9cc6), LPC_WPT_LP}, |
942 | { PCI_VDEVICE(INTEL, 0x9cc7), LPC_WPT_LP}, |
943 | { PCI_VDEVICE(INTEL, 0x9cc9), LPC_WPT_LP}, |
944 | { PCI_VDEVICE(INTEL, 0xa1c1), LPC_LEWISBURG}, |
945 | { PCI_VDEVICE(INTEL, 0xa1c2), LPC_LEWISBURG}, |
946 | { PCI_VDEVICE(INTEL, 0xa1c3), LPC_LEWISBURG}, |
947 | { PCI_VDEVICE(INTEL, 0xa1c4), LPC_LEWISBURG}, |
948 | { PCI_VDEVICE(INTEL, 0xa1c5), LPC_LEWISBURG}, |
949 | { PCI_VDEVICE(INTEL, 0xa1c6), LPC_LEWISBURG}, |
950 | { PCI_VDEVICE(INTEL, 0xa1c7), LPC_LEWISBURG}, |
951 | { PCI_VDEVICE(INTEL, 0xa242), LPC_LEWISBURG}, |
952 | { PCI_VDEVICE(INTEL, 0xa243), LPC_LEWISBURG}, |
953 | { 0, }, /* End of list */ |
954 | }; |
955 | MODULE_DEVICE_TABLE(pci, lpc_ich_ids); |
956 | |
957 | static void lpc_ich_restore_config_space(struct pci_dev *dev) |
958 | { |
959 | struct lpc_ich_priv *priv = pci_get_drvdata(pdev: dev); |
960 | |
961 | if (priv->abase_save >= 0) { |
962 | pci_write_config_byte(dev, where: priv->abase, val: priv->abase_save); |
963 | priv->abase_save = -1; |
964 | } |
965 | |
966 | if (priv->actrl_pbase_save >= 0) { |
967 | pci_write_config_byte(dev, where: priv->actrl_pbase, |
968 | val: priv->actrl_pbase_save); |
969 | priv->actrl_pbase_save = -1; |
970 | } |
971 | |
972 | if (priv->gctrl_save >= 0) { |
973 | pci_write_config_byte(dev, where: priv->gctrl, val: priv->gctrl_save); |
974 | priv->gctrl_save = -1; |
975 | } |
976 | } |
977 | |
978 | static void lpc_ich_enable_acpi_space(struct pci_dev *dev) |
979 | { |
980 | struct lpc_ich_priv *priv = pci_get_drvdata(pdev: dev); |
981 | u8 reg_save; |
982 | |
983 | switch (lpc_chipset_info[priv->chipset].iTCO_version) { |
984 | case 3: |
985 | /* |
986 | * Some chipsets (eg Avoton) enable the ACPI space in the |
987 | * ACPI BASE register. |
988 | */ |
989 | pci_read_config_byte(dev, where: priv->abase, val: ®_save); |
990 | pci_write_config_byte(dev, where: priv->abase, val: reg_save | 0x2); |
991 | priv->abase_save = reg_save; |
992 | break; |
993 | default: |
994 | /* |
995 | * Most chipsets enable the ACPI space in the ACPI control |
996 | * register. |
997 | */ |
998 | pci_read_config_byte(dev, where: priv->actrl_pbase, val: ®_save); |
999 | pci_write_config_byte(dev, where: priv->actrl_pbase, val: reg_save | 0x80); |
1000 | priv->actrl_pbase_save = reg_save; |
1001 | break; |
1002 | } |
1003 | } |
1004 | |
1005 | static void lpc_ich_enable_gpio_space(struct pci_dev *dev) |
1006 | { |
1007 | struct lpc_ich_priv *priv = pci_get_drvdata(pdev: dev); |
1008 | u8 reg_save; |
1009 | |
1010 | pci_read_config_byte(dev, where: priv->gctrl, val: ®_save); |
1011 | pci_write_config_byte(dev, where: priv->gctrl, val: reg_save | 0x10); |
1012 | priv->gctrl_save = reg_save; |
1013 | } |
1014 | |
1015 | static void lpc_ich_enable_pmc_space(struct pci_dev *dev) |
1016 | { |
1017 | struct lpc_ich_priv *priv = pci_get_drvdata(pdev: dev); |
1018 | u8 reg_save; |
1019 | |
1020 | pci_read_config_byte(dev, where: priv->actrl_pbase, val: ®_save); |
1021 | pci_write_config_byte(dev, where: priv->actrl_pbase, val: reg_save | 0x2); |
1022 | |
1023 | priv->actrl_pbase_save = reg_save; |
1024 | } |
1025 | |
1026 | static int lpc_ich_finalize_wdt_cell(struct pci_dev *dev) |
1027 | { |
1028 | struct itco_wdt_platform_data *pdata; |
1029 | struct lpc_ich_priv *priv = pci_get_drvdata(pdev: dev); |
1030 | struct lpc_ich_info *info; |
1031 | struct mfd_cell *cell = &lpc_ich_wdt_cell; |
1032 | |
1033 | pdata = devm_kzalloc(dev: &dev->dev, size: sizeof(*pdata), GFP_KERNEL); |
1034 | if (!pdata) |
1035 | return -ENOMEM; |
1036 | |
1037 | info = &lpc_chipset_info[priv->chipset]; |
1038 | |
1039 | pdata->version = info->iTCO_version; |
1040 | strscpy(pdata->name, info->name, sizeof(pdata->name)); |
1041 | |
1042 | cell->platform_data = pdata; |
1043 | cell->pdata_size = sizeof(*pdata); |
1044 | return 0; |
1045 | } |
1046 | |
1047 | static void lpc_ich_finalize_gpio_cell(struct pci_dev *dev) |
1048 | { |
1049 | struct lpc_ich_priv *priv = pci_get_drvdata(pdev: dev); |
1050 | struct mfd_cell *cell = &lpc_ich_gpio_cell; |
1051 | |
1052 | cell->platform_data = &lpc_chipset_info[priv->chipset]; |
1053 | cell->pdata_size = sizeof(struct lpc_ich_info); |
1054 | } |
1055 | |
1056 | /* |
1057 | * We don't check for resource conflict globally. There are 2 or 3 independent |
1058 | * GPIO groups and it's enough to have access to one of these to instantiate |
1059 | * the device. |
1060 | */ |
1061 | static int lpc_ich_check_conflict_gpio(struct resource *res) |
1062 | { |
1063 | int ret; |
1064 | u8 use_gpio = 0; |
1065 | |
1066 | if (resource_size(res) >= 0x50 && |
1067 | !acpi_check_region(start: res->start + 0x40, n: 0x10, name: "LPC ICH GPIO3" )) |
1068 | use_gpio |= 1 << 2; |
1069 | |
1070 | if (!acpi_check_region(start: res->start + 0x30, n: 0x10, name: "LPC ICH GPIO2" )) |
1071 | use_gpio |= 1 << 1; |
1072 | |
1073 | ret = acpi_check_region(start: res->start + 0x00, n: 0x30, name: "LPC ICH GPIO1" ); |
1074 | if (!ret) |
1075 | use_gpio |= 1 << 0; |
1076 | |
1077 | return use_gpio ? use_gpio : ret; |
1078 | } |
1079 | |
1080 | static int lpc_ich_init_gpio(struct pci_dev *dev) |
1081 | { |
1082 | struct lpc_ich_priv *priv = pci_get_drvdata(pdev: dev); |
1083 | u32 base_addr_cfg; |
1084 | u32 base_addr; |
1085 | int ret; |
1086 | bool acpi_conflict = false; |
1087 | struct resource *res; |
1088 | |
1089 | /* Setup power management base register */ |
1090 | pci_read_config_dword(dev, where: priv->abase, val: &base_addr_cfg); |
1091 | base_addr = base_addr_cfg & 0x0000ff80; |
1092 | if (!base_addr) { |
1093 | dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n" ); |
1094 | lpc_ich_gpio_cell.num_resources--; |
1095 | goto gpe0_done; |
1096 | } |
1097 | |
1098 | res = &gpio_ich_res[ICH_RES_GPE0]; |
1099 | res->start = base_addr + ACPIBASE_GPE_OFF; |
1100 | res->end = base_addr + ACPIBASE_GPE_END; |
1101 | ret = acpi_check_resource_conflict(res); |
1102 | if (ret) { |
1103 | /* |
1104 | * This isn't fatal for the GPIO, but we have to make sure that |
1105 | * the platform_device subsystem doesn't see this resource |
1106 | * or it will register an invalid region. |
1107 | */ |
1108 | lpc_ich_gpio_cell.num_resources--; |
1109 | acpi_conflict = true; |
1110 | } else { |
1111 | lpc_ich_enable_acpi_space(dev); |
1112 | } |
1113 | |
1114 | gpe0_done: |
1115 | /* Setup GPIO base register */ |
1116 | pci_read_config_dword(dev, where: priv->gbase, val: &base_addr_cfg); |
1117 | base_addr = base_addr_cfg & 0x0000ff80; |
1118 | if (!base_addr) { |
1119 | dev_notice(&dev->dev, "I/O space for GPIO uninitialized\n" ); |
1120 | ret = -ENODEV; |
1121 | goto gpio_done; |
1122 | } |
1123 | |
1124 | /* Older devices provide fewer GPIO and have a smaller resource size. */ |
1125 | res = &gpio_ich_res[ICH_RES_GPIO]; |
1126 | res->start = base_addr; |
1127 | switch (lpc_chipset_info[priv->chipset].gpio_version) { |
1128 | case ICH_V5_GPIO: |
1129 | case ICH_V10CORP_GPIO: |
1130 | res->end = res->start + 128 - 1; |
1131 | break; |
1132 | default: |
1133 | res->end = res->start + 64 - 1; |
1134 | break; |
1135 | } |
1136 | |
1137 | ret = lpc_ich_check_conflict_gpio(res); |
1138 | if (ret < 0) { |
1139 | /* this isn't necessarily fatal for the GPIO */ |
1140 | acpi_conflict = true; |
1141 | goto gpio_done; |
1142 | } |
1143 | lpc_chipset_info[priv->chipset].use_gpio = ret; |
1144 | lpc_ich_enable_gpio_space(dev); |
1145 | |
1146 | lpc_ich_finalize_gpio_cell(dev); |
1147 | ret = mfd_add_devices(parent: &dev->dev, PLATFORM_DEVID_AUTO, |
1148 | cells: &lpc_ich_gpio_cell, n_devs: 1, NULL, irq_base: 0, NULL); |
1149 | |
1150 | gpio_done: |
1151 | if (acpi_conflict) |
1152 | pr_warn("Resource conflict(s) found affecting %s\n" , |
1153 | lpc_ich_gpio_cell.name); |
1154 | return ret; |
1155 | } |
1156 | |
1157 | static int lpc_ich_init_wdt(struct pci_dev *dev) |
1158 | { |
1159 | struct lpc_ich_priv *priv = pci_get_drvdata(pdev: dev); |
1160 | u32 base_addr_cfg; |
1161 | u32 base_addr; |
1162 | int ret; |
1163 | struct resource *res; |
1164 | |
1165 | /* If we have ACPI based watchdog use that instead */ |
1166 | if (acpi_has_watchdog()) |
1167 | return -ENODEV; |
1168 | |
1169 | /* Setup power management base register */ |
1170 | pci_read_config_dword(dev, where: priv->abase, val: &base_addr_cfg); |
1171 | base_addr = base_addr_cfg & 0x0000ff80; |
1172 | if (!base_addr) { |
1173 | dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n" ); |
1174 | ret = -ENODEV; |
1175 | goto wdt_done; |
1176 | } |
1177 | |
1178 | res = wdt_io_res(ICH_RES_IO_TCO); |
1179 | res->start = base_addr + ACPIBASE_TCO_OFF; |
1180 | res->end = base_addr + ACPIBASE_TCO_END; |
1181 | |
1182 | res = wdt_io_res(ICH_RES_IO_SMI); |
1183 | res->start = base_addr + ACPIBASE_SMI_OFF; |
1184 | res->end = base_addr + ACPIBASE_SMI_END; |
1185 | |
1186 | lpc_ich_enable_acpi_space(dev); |
1187 | |
1188 | /* |
1189 | * iTCO v2: |
1190 | * Get the Memory-Mapped GCS register. To get access to it |
1191 | * we have to read RCBA from PCI Config space 0xf0 and use |
1192 | * it as base. GCS = RCBA + ICH6_GCS(0x3410). |
1193 | * |
1194 | * iTCO v3: |
1195 | * Get the Power Management Configuration register. To get access |
1196 | * to it we have to read the PMC BASE from config space and address |
1197 | * the register at offset 0x8. |
1198 | */ |
1199 | if (lpc_chipset_info[priv->chipset].iTCO_version == 1) { |
1200 | /* Don't register iomem for TCO ver 1 */ |
1201 | lpc_ich_wdt_cell.num_resources--; |
1202 | } else if (lpc_chipset_info[priv->chipset].iTCO_version == 2) { |
1203 | pci_read_config_dword(dev, RCBABASE, val: &base_addr_cfg); |
1204 | base_addr = base_addr_cfg & 0xffffc000; |
1205 | if (!(base_addr_cfg & 1)) { |
1206 | dev_notice(&dev->dev, "RCBA is disabled by " |
1207 | "hardware/BIOS, device disabled\n" ); |
1208 | ret = -ENODEV; |
1209 | goto wdt_done; |
1210 | } |
1211 | res = wdt_mem_res(ICH_RES_MEM_GCS_PMC); |
1212 | res->start = base_addr + ACPIBASE_GCS_OFF; |
1213 | res->end = base_addr + ACPIBASE_GCS_END; |
1214 | } else if (lpc_chipset_info[priv->chipset].iTCO_version == 3) { |
1215 | lpc_ich_enable_pmc_space(dev); |
1216 | pci_read_config_dword(dev, ACPICTRL_PMCBASE, val: &base_addr_cfg); |
1217 | base_addr = base_addr_cfg & 0xfffffe00; |
1218 | |
1219 | res = wdt_mem_res(ICH_RES_MEM_GCS_PMC); |
1220 | res->start = base_addr + ACPIBASE_PMC_OFF; |
1221 | res->end = base_addr + ACPIBASE_PMC_END; |
1222 | } |
1223 | |
1224 | ret = lpc_ich_finalize_wdt_cell(dev); |
1225 | if (ret) |
1226 | goto wdt_done; |
1227 | |
1228 | ret = mfd_add_devices(parent: &dev->dev, PLATFORM_DEVID_AUTO, |
1229 | cells: &lpc_ich_wdt_cell, n_devs: 1, NULL, irq_base: 0, NULL); |
1230 | |
1231 | wdt_done: |
1232 | return ret; |
1233 | } |
1234 | |
1235 | static int lpc_ich_init_pinctrl(struct pci_dev *dev) |
1236 | { |
1237 | struct lpc_ich_priv *priv = pci_get_drvdata(pdev: dev); |
1238 | const struct lpc_ich_gpio_info *info = lpc_chipset_info[priv->chipset].gpio_info; |
1239 | struct resource base; |
1240 | unsigned int i; |
1241 | int ret; |
1242 | |
1243 | /* Check, if GPIO has been exported as an ACPI device */ |
1244 | if (acpi_dev_present(hid: info->hid, NULL, hrv: -1)) |
1245 | return -EEXIST; |
1246 | |
1247 | ret = p2sb_bar(bus: dev->bus, devfn: 0, mem: &base); |
1248 | if (ret) |
1249 | return ret; |
1250 | |
1251 | for (i = 0; i < info->nr_resources; i++) { |
1252 | struct resource *mem = info->resources[i]; |
1253 | resource_size_t offset = info->offsets[i]; |
1254 | |
1255 | /* Fill MEM resource */ |
1256 | mem->start = base.start + offset; |
1257 | mem->end = base.start + offset + INTEL_GPIO_RESOURCE_SIZE - 1; |
1258 | mem->flags = base.flags; |
1259 | } |
1260 | |
1261 | return mfd_add_devices(parent: &dev->dev, id: 0, cells: info->devices, n_devs: info->nr_devices, |
1262 | NULL, irq_base: 0, NULL); |
1263 | } |
1264 | |
1265 | static bool lpc_ich_byt_set_writeable(void __iomem *base, void *data) |
1266 | { |
1267 | u32 val; |
1268 | |
1269 | val = readl(addr: base + BYT_BCR); |
1270 | if (!(val & BYT_BCR_WPD)) { |
1271 | val |= BYT_BCR_WPD; |
1272 | writel(val, addr: base + BYT_BCR); |
1273 | val = readl(addr: base + BYT_BCR); |
1274 | } |
1275 | |
1276 | return val & BYT_BCR_WPD; |
1277 | } |
1278 | |
1279 | static bool lpc_ich_set_writeable(struct pci_bus *bus, unsigned int devfn) |
1280 | { |
1281 | u32 bcr; |
1282 | |
1283 | pci_bus_read_config_dword(bus, devfn, BCR, val: &bcr); |
1284 | if (!(bcr & BCR_WPD)) { |
1285 | bcr |= BCR_WPD; |
1286 | pci_bus_write_config_dword(bus, devfn, BCR, val: bcr); |
1287 | pci_bus_read_config_dword(bus, devfn, BCR, val: &bcr); |
1288 | } |
1289 | |
1290 | return bcr & BCR_WPD; |
1291 | } |
1292 | |
1293 | static bool lpc_ich_lpt_set_writeable(void __iomem *base, void *data) |
1294 | { |
1295 | struct pci_dev *pdev = data; |
1296 | |
1297 | return lpc_ich_set_writeable(bus: pdev->bus, devfn: pdev->devfn); |
1298 | } |
1299 | |
1300 | static bool lpc_ich_bxt_set_writeable(void __iomem *base, void *data) |
1301 | { |
1302 | struct pci_dev *pdev = data; |
1303 | |
1304 | return lpc_ich_set_writeable(bus: pdev->bus, PCI_DEVFN(13, 2)); |
1305 | } |
1306 | |
1307 | static int lpc_ich_init_spi(struct pci_dev *dev) |
1308 | { |
1309 | struct lpc_ich_priv *priv = pci_get_drvdata(pdev: dev); |
1310 | struct resource *res = &intel_spi_res[0]; |
1311 | struct intel_spi_boardinfo *info; |
1312 | u32 spi_base, rcba; |
1313 | int ret; |
1314 | |
1315 | info = devm_kzalloc(dev: &dev->dev, size: sizeof(*info), GFP_KERNEL); |
1316 | if (!info) |
1317 | return -ENOMEM; |
1318 | |
1319 | info->type = lpc_chipset_info[priv->chipset].spi_type; |
1320 | |
1321 | switch (info->type) { |
1322 | case INTEL_SPI_BYT: |
1323 | pci_read_config_dword(dev, SPIBASE_BYT, val: &spi_base); |
1324 | if (spi_base & SPIBASE_BYT_EN) { |
1325 | res->start = ALIGN_DOWN(spi_base, SPIBASE_BYT_SZ); |
1326 | res->end = res->start + SPIBASE_BYT_SZ - 1; |
1327 | |
1328 | info->set_writeable = lpc_ich_byt_set_writeable; |
1329 | } |
1330 | break; |
1331 | |
1332 | case INTEL_SPI_LPT: |
1333 | pci_read_config_dword(dev, RCBABASE, val: &rcba); |
1334 | if (rcba & 1) { |
1335 | spi_base = round_down(rcba, SPIBASE_LPT_SZ); |
1336 | res->start = spi_base + SPIBASE_LPT; |
1337 | res->end = res->start + SPIBASE_LPT_SZ - 1; |
1338 | |
1339 | info->set_writeable = lpc_ich_lpt_set_writeable; |
1340 | info->data = dev; |
1341 | } |
1342 | break; |
1343 | |
1344 | case INTEL_SPI_BXT: |
1345 | /* |
1346 | * The P2SB is hidden by BIOS and we need to unhide it in |
1347 | * order to read BAR of the SPI flash device. Once that is |
1348 | * done we hide it again. |
1349 | */ |
1350 | ret = p2sb_bar(bus: dev->bus, PCI_DEVFN(13, 2), mem: res); |
1351 | if (ret) |
1352 | return ret; |
1353 | |
1354 | info->set_writeable = lpc_ich_bxt_set_writeable; |
1355 | info->data = dev; |
1356 | break; |
1357 | |
1358 | default: |
1359 | return -EINVAL; |
1360 | } |
1361 | |
1362 | if (!res->start) |
1363 | return -ENODEV; |
1364 | |
1365 | lpc_ich_spi_cell.platform_data = info; |
1366 | lpc_ich_spi_cell.pdata_size = sizeof(*info); |
1367 | |
1368 | return mfd_add_devices(parent: &dev->dev, PLATFORM_DEVID_NONE, |
1369 | cells: &lpc_ich_spi_cell, n_devs: 1, NULL, irq_base: 0, NULL); |
1370 | } |
1371 | |
1372 | static int lpc_ich_probe(struct pci_dev *dev, |
1373 | const struct pci_device_id *id) |
1374 | { |
1375 | struct lpc_ich_priv *priv; |
1376 | int ret; |
1377 | bool cell_added = false; |
1378 | |
1379 | priv = devm_kzalloc(dev: &dev->dev, |
1380 | size: sizeof(struct lpc_ich_priv), GFP_KERNEL); |
1381 | if (!priv) |
1382 | return -ENOMEM; |
1383 | |
1384 | priv->chipset = id->driver_data; |
1385 | |
1386 | priv->actrl_pbase_save = -1; |
1387 | priv->abase_save = -1; |
1388 | |
1389 | priv->abase = ACPIBASE; |
1390 | priv->actrl_pbase = ACPICTRL_PMCBASE; |
1391 | |
1392 | priv->gctrl_save = -1; |
1393 | if (priv->chipset <= LPC_ICH5) { |
1394 | priv->gbase = GPIOBASE_ICH0; |
1395 | priv->gctrl = GPIOCTRL_ICH0; |
1396 | } else { |
1397 | priv->gbase = GPIOBASE_ICH6; |
1398 | priv->gctrl = GPIOCTRL_ICH6; |
1399 | } |
1400 | |
1401 | pci_set_drvdata(pdev: dev, data: priv); |
1402 | |
1403 | if (lpc_chipset_info[priv->chipset].iTCO_version) { |
1404 | ret = lpc_ich_init_wdt(dev); |
1405 | if (!ret) |
1406 | cell_added = true; |
1407 | } |
1408 | |
1409 | if (lpc_chipset_info[priv->chipset].gpio_version) { |
1410 | ret = lpc_ich_init_gpio(dev); |
1411 | if (!ret) |
1412 | cell_added = true; |
1413 | } |
1414 | |
1415 | if (lpc_chipset_info[priv->chipset].gpio_info) { |
1416 | ret = lpc_ich_init_pinctrl(dev); |
1417 | if (!ret) |
1418 | cell_added = true; |
1419 | } |
1420 | |
1421 | if (lpc_chipset_info[priv->chipset].spi_type) { |
1422 | ret = lpc_ich_init_spi(dev); |
1423 | if (!ret) |
1424 | cell_added = true; |
1425 | } |
1426 | |
1427 | /* |
1428 | * We only care if at least one or none of the cells registered |
1429 | * successfully. |
1430 | */ |
1431 | if (!cell_added) { |
1432 | dev_warn(&dev->dev, "No MFD cells added\n" ); |
1433 | lpc_ich_restore_config_space(dev); |
1434 | return -ENODEV; |
1435 | } |
1436 | |
1437 | return 0; |
1438 | } |
1439 | |
1440 | static void lpc_ich_remove(struct pci_dev *dev) |
1441 | { |
1442 | mfd_remove_devices(parent: &dev->dev); |
1443 | lpc_ich_restore_config_space(dev); |
1444 | } |
1445 | |
1446 | static struct pci_driver lpc_ich_driver = { |
1447 | .name = "lpc_ich" , |
1448 | .id_table = lpc_ich_ids, |
1449 | .probe = lpc_ich_probe, |
1450 | .remove = lpc_ich_remove, |
1451 | }; |
1452 | |
1453 | module_pci_driver(lpc_ich_driver); |
1454 | |
1455 | MODULE_AUTHOR("Aaron Sierra <asierra@xes-inc.com>" ); |
1456 | MODULE_DESCRIPTION("LPC interface for Intel ICH" ); |
1457 | MODULE_LICENSE("GPL" ); |
1458 | |