1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Core functions for TI TPS6594/TPS6593/LP8764 PMICs |
4 | * |
5 | * Copyright (C) 2023 BayLibre Incorporated - https://www.baylibre.com/ |
6 | */ |
7 | |
8 | #include <linux/completion.h> |
9 | #include <linux/delay.h> |
10 | #include <linux/interrupt.h> |
11 | #include <linux/module.h> |
12 | #include <linux/of.h> |
13 | |
14 | #include <linux/mfd/core.h> |
15 | #include <linux/mfd/tps6594.h> |
16 | |
17 | #define TPS6594_CRC_SYNC_TIMEOUT_MS 150 |
18 | |
19 | /* Completion to synchronize CRC feature enabling on all PMICs */ |
20 | static DECLARE_COMPLETION(tps6594_crc_comp); |
21 | |
22 | static const struct resource tps6594_regulator_resources[] = { |
23 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK1_OV, TPS6594_IRQ_NAME_BUCK1_OV), |
24 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK1_UV, TPS6594_IRQ_NAME_BUCK1_UV), |
25 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK1_SC, TPS6594_IRQ_NAME_BUCK1_SC), |
26 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK1_ILIM, TPS6594_IRQ_NAME_BUCK1_ILIM), |
27 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK2_OV, TPS6594_IRQ_NAME_BUCK2_OV), |
28 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK2_UV, TPS6594_IRQ_NAME_BUCK2_UV), |
29 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK2_SC, TPS6594_IRQ_NAME_BUCK2_SC), |
30 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK2_ILIM, TPS6594_IRQ_NAME_BUCK2_ILIM), |
31 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK3_OV, TPS6594_IRQ_NAME_BUCK3_OV), |
32 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK3_UV, TPS6594_IRQ_NAME_BUCK3_UV), |
33 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK3_SC, TPS6594_IRQ_NAME_BUCK3_SC), |
34 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK3_ILIM, TPS6594_IRQ_NAME_BUCK3_ILIM), |
35 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK4_OV, TPS6594_IRQ_NAME_BUCK4_OV), |
36 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK4_UV, TPS6594_IRQ_NAME_BUCK4_UV), |
37 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK4_SC, TPS6594_IRQ_NAME_BUCK4_SC), |
38 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK4_ILIM, TPS6594_IRQ_NAME_BUCK4_ILIM), |
39 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK5_OV, TPS6594_IRQ_NAME_BUCK5_OV), |
40 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK5_UV, TPS6594_IRQ_NAME_BUCK5_UV), |
41 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK5_SC, TPS6594_IRQ_NAME_BUCK5_SC), |
42 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK5_ILIM, TPS6594_IRQ_NAME_BUCK5_ILIM), |
43 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO1_OV, TPS6594_IRQ_NAME_LDO1_OV), |
44 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO1_UV, TPS6594_IRQ_NAME_LDO1_UV), |
45 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO1_SC, TPS6594_IRQ_NAME_LDO1_SC), |
46 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO1_ILIM, TPS6594_IRQ_NAME_LDO1_ILIM), |
47 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO2_OV, TPS6594_IRQ_NAME_LDO2_OV), |
48 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO2_UV, TPS6594_IRQ_NAME_LDO2_UV), |
49 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO2_SC, TPS6594_IRQ_NAME_LDO2_SC), |
50 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO2_ILIM, TPS6594_IRQ_NAME_LDO2_ILIM), |
51 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO3_OV, TPS6594_IRQ_NAME_LDO3_OV), |
52 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO3_UV, TPS6594_IRQ_NAME_LDO3_UV), |
53 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO3_SC, TPS6594_IRQ_NAME_LDO3_SC), |
54 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO3_ILIM, TPS6594_IRQ_NAME_LDO3_ILIM), |
55 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO4_OV, TPS6594_IRQ_NAME_LDO4_OV), |
56 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO4_UV, TPS6594_IRQ_NAME_LDO4_UV), |
57 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO4_SC, TPS6594_IRQ_NAME_LDO4_SC), |
58 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO4_ILIM, TPS6594_IRQ_NAME_LDO4_ILIM), |
59 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VCCA_OV, TPS6594_IRQ_NAME_VCCA_OV), |
60 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VCCA_UV, TPS6594_IRQ_NAME_VCCA_UV), |
61 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VMON1_OV, TPS6594_IRQ_NAME_VMON1_OV), |
62 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VMON1_UV, TPS6594_IRQ_NAME_VMON1_UV), |
63 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VMON1_RV, TPS6594_IRQ_NAME_VMON1_RV), |
64 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VMON2_OV, TPS6594_IRQ_NAME_VMON2_OV), |
65 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VMON2_UV, TPS6594_IRQ_NAME_VMON2_UV), |
66 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VMON2_RV, TPS6594_IRQ_NAME_VMON2_RV), |
67 | }; |
68 | |
69 | static const struct resource tps6594_pinctrl_resources[] = { |
70 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO9, TPS6594_IRQ_NAME_GPIO9), |
71 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO10, TPS6594_IRQ_NAME_GPIO10), |
72 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO11, TPS6594_IRQ_NAME_GPIO11), |
73 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO1, TPS6594_IRQ_NAME_GPIO1), |
74 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO2, TPS6594_IRQ_NAME_GPIO2), |
75 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO3, TPS6594_IRQ_NAME_GPIO3), |
76 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO4, TPS6594_IRQ_NAME_GPIO4), |
77 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO5, TPS6594_IRQ_NAME_GPIO5), |
78 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO6, TPS6594_IRQ_NAME_GPIO6), |
79 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO7, TPS6594_IRQ_NAME_GPIO7), |
80 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO8, TPS6594_IRQ_NAME_GPIO8), |
81 | }; |
82 | |
83 | static const struct resource tps6594_pfsm_resources[] = { |
84 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_NPWRON_START, TPS6594_IRQ_NAME_NPWRON_START), |
85 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_ENABLE, TPS6594_IRQ_NAME_ENABLE), |
86 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_FSD, TPS6594_IRQ_NAME_FSD), |
87 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_SOFT_REBOOT, TPS6594_IRQ_NAME_SOFT_REBOOT), |
88 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BIST_PASS, TPS6594_IRQ_NAME_BIST_PASS), |
89 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_EXT_CLK, TPS6594_IRQ_NAME_EXT_CLK), |
90 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_TWARN, TPS6594_IRQ_NAME_TWARN), |
91 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_TSD_ORD, TPS6594_IRQ_NAME_TSD_ORD), |
92 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BIST_FAIL, TPS6594_IRQ_NAME_BIST_FAIL), |
93 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_REG_CRC_ERR, TPS6594_IRQ_NAME_REG_CRC_ERR), |
94 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_RECOV_CNT, TPS6594_IRQ_NAME_RECOV_CNT), |
95 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_SPMI_ERR, TPS6594_IRQ_NAME_SPMI_ERR), |
96 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_NPWRON_LONG, TPS6594_IRQ_NAME_NPWRON_LONG), |
97 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_NINT_READBACK, TPS6594_IRQ_NAME_NINT_READBACK), |
98 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_NRSTOUT_READBACK, TPS6594_IRQ_NAME_NRSTOUT_READBACK), |
99 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_TSD_IMM, TPS6594_IRQ_NAME_TSD_IMM), |
100 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VCCA_OVP, TPS6594_IRQ_NAME_VCCA_OVP), |
101 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_PFSM_ERR, TPS6594_IRQ_NAME_PFSM_ERR), |
102 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_IMM_SHUTDOWN, TPS6594_IRQ_NAME_IMM_SHUTDOWN), |
103 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_ORD_SHUTDOWN, TPS6594_IRQ_NAME_ORD_SHUTDOWN), |
104 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_MCU_PWR_ERR, TPS6594_IRQ_NAME_MCU_PWR_ERR), |
105 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_SOC_PWR_ERR, TPS6594_IRQ_NAME_SOC_PWR_ERR), |
106 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_COMM_FRM_ERR, TPS6594_IRQ_NAME_COMM_FRM_ERR), |
107 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_COMM_CRC_ERR, TPS6594_IRQ_NAME_COMM_CRC_ERR), |
108 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_COMM_ADR_ERR, TPS6594_IRQ_NAME_COMM_ADR_ERR), |
109 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_EN_DRV_READBACK, TPS6594_IRQ_NAME_EN_DRV_READBACK), |
110 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_NRSTOUT_SOC_READBACK, |
111 | TPS6594_IRQ_NAME_NRSTOUT_SOC_READBACK), |
112 | }; |
113 | |
114 | static const struct resource tps6594_esm_resources[] = { |
115 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_ESM_SOC_PIN, TPS6594_IRQ_NAME_ESM_SOC_PIN), |
116 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_ESM_SOC_FAIL, TPS6594_IRQ_NAME_ESM_SOC_FAIL), |
117 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_ESM_SOC_RST, TPS6594_IRQ_NAME_ESM_SOC_RST), |
118 | }; |
119 | |
120 | static const struct resource tps6594_rtc_resources[] = { |
121 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_TIMER, TPS6594_IRQ_NAME_TIMER), |
122 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_ALARM, TPS6594_IRQ_NAME_ALARM), |
123 | DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_POWER_UP, TPS6594_IRQ_NAME_POWERUP), |
124 | }; |
125 | |
126 | static const struct mfd_cell tps6594_common_cells[] = { |
127 | MFD_CELL_RES("tps6594-regulator" , tps6594_regulator_resources), |
128 | MFD_CELL_RES("tps6594-pinctrl" , tps6594_pinctrl_resources), |
129 | MFD_CELL_RES("tps6594-pfsm" , tps6594_pfsm_resources), |
130 | MFD_CELL_RES("tps6594-esm" , tps6594_esm_resources), |
131 | }; |
132 | |
133 | static const struct mfd_cell tps6594_rtc_cells[] = { |
134 | MFD_CELL_RES("tps6594-rtc" , tps6594_rtc_resources), |
135 | }; |
136 | |
137 | static const struct regmap_irq tps6594_irqs[] = { |
138 | /* INT_BUCK1_2 register */ |
139 | REGMAP_IRQ_REG(TPS6594_IRQ_BUCK1_OV, 0, TPS6594_BIT_BUCKX_OV_INT(0)), |
140 | REGMAP_IRQ_REG(TPS6594_IRQ_BUCK1_UV, 0, TPS6594_BIT_BUCKX_UV_INT(0)), |
141 | REGMAP_IRQ_REG(TPS6594_IRQ_BUCK1_SC, 0, TPS6594_BIT_BUCKX_SC_INT(0)), |
142 | REGMAP_IRQ_REG(TPS6594_IRQ_BUCK1_ILIM, 0, TPS6594_BIT_BUCKX_ILIM_INT(0)), |
143 | REGMAP_IRQ_REG(TPS6594_IRQ_BUCK2_OV, 0, TPS6594_BIT_BUCKX_OV_INT(1)), |
144 | REGMAP_IRQ_REG(TPS6594_IRQ_BUCK2_UV, 0, TPS6594_BIT_BUCKX_UV_INT(1)), |
145 | REGMAP_IRQ_REG(TPS6594_IRQ_BUCK2_SC, 0, TPS6594_BIT_BUCKX_SC_INT(1)), |
146 | REGMAP_IRQ_REG(TPS6594_IRQ_BUCK2_ILIM, 0, TPS6594_BIT_BUCKX_ILIM_INT(1)), |
147 | |
148 | /* INT_BUCK3_4 register */ |
149 | REGMAP_IRQ_REG(TPS6594_IRQ_BUCK3_OV, 1, TPS6594_BIT_BUCKX_OV_INT(2)), |
150 | REGMAP_IRQ_REG(TPS6594_IRQ_BUCK3_UV, 1, TPS6594_BIT_BUCKX_UV_INT(2)), |
151 | REGMAP_IRQ_REG(TPS6594_IRQ_BUCK3_SC, 1, TPS6594_BIT_BUCKX_SC_INT(2)), |
152 | REGMAP_IRQ_REG(TPS6594_IRQ_BUCK3_ILIM, 1, TPS6594_BIT_BUCKX_ILIM_INT(2)), |
153 | REGMAP_IRQ_REG(TPS6594_IRQ_BUCK4_OV, 1, TPS6594_BIT_BUCKX_OV_INT(3)), |
154 | REGMAP_IRQ_REG(TPS6594_IRQ_BUCK4_UV, 1, TPS6594_BIT_BUCKX_UV_INT(3)), |
155 | REGMAP_IRQ_REG(TPS6594_IRQ_BUCK4_SC, 1, TPS6594_BIT_BUCKX_SC_INT(3)), |
156 | REGMAP_IRQ_REG(TPS6594_IRQ_BUCK4_ILIM, 1, TPS6594_BIT_BUCKX_ILIM_INT(3)), |
157 | |
158 | /* INT_BUCK5 register */ |
159 | REGMAP_IRQ_REG(TPS6594_IRQ_BUCK5_OV, 2, TPS6594_BIT_BUCKX_OV_INT(4)), |
160 | REGMAP_IRQ_REG(TPS6594_IRQ_BUCK5_UV, 2, TPS6594_BIT_BUCKX_UV_INT(4)), |
161 | REGMAP_IRQ_REG(TPS6594_IRQ_BUCK5_SC, 2, TPS6594_BIT_BUCKX_SC_INT(4)), |
162 | REGMAP_IRQ_REG(TPS6594_IRQ_BUCK5_ILIM, 2, TPS6594_BIT_BUCKX_ILIM_INT(4)), |
163 | |
164 | /* INT_LDO1_2 register */ |
165 | REGMAP_IRQ_REG(TPS6594_IRQ_LDO1_OV, 3, TPS6594_BIT_LDOX_OV_INT(0)), |
166 | REGMAP_IRQ_REG(TPS6594_IRQ_LDO1_UV, 3, TPS6594_BIT_LDOX_UV_INT(0)), |
167 | REGMAP_IRQ_REG(TPS6594_IRQ_LDO1_SC, 3, TPS6594_BIT_LDOX_SC_INT(0)), |
168 | REGMAP_IRQ_REG(TPS6594_IRQ_LDO1_ILIM, 3, TPS6594_BIT_LDOX_ILIM_INT(0)), |
169 | REGMAP_IRQ_REG(TPS6594_IRQ_LDO2_OV, 3, TPS6594_BIT_LDOX_OV_INT(1)), |
170 | REGMAP_IRQ_REG(TPS6594_IRQ_LDO2_UV, 3, TPS6594_BIT_LDOX_UV_INT(1)), |
171 | REGMAP_IRQ_REG(TPS6594_IRQ_LDO2_SC, 3, TPS6594_BIT_LDOX_SC_INT(1)), |
172 | REGMAP_IRQ_REG(TPS6594_IRQ_LDO2_ILIM, 3, TPS6594_BIT_LDOX_ILIM_INT(1)), |
173 | |
174 | /* INT_LDO3_4 register */ |
175 | REGMAP_IRQ_REG(TPS6594_IRQ_LDO3_OV, 4, TPS6594_BIT_LDOX_OV_INT(2)), |
176 | REGMAP_IRQ_REG(TPS6594_IRQ_LDO3_UV, 4, TPS6594_BIT_LDOX_UV_INT(2)), |
177 | REGMAP_IRQ_REG(TPS6594_IRQ_LDO3_SC, 4, TPS6594_BIT_LDOX_SC_INT(2)), |
178 | REGMAP_IRQ_REG(TPS6594_IRQ_LDO3_ILIM, 4, TPS6594_BIT_LDOX_ILIM_INT(2)), |
179 | REGMAP_IRQ_REG(TPS6594_IRQ_LDO4_OV, 4, TPS6594_BIT_LDOX_OV_INT(3)), |
180 | REGMAP_IRQ_REG(TPS6594_IRQ_LDO4_UV, 4, TPS6594_BIT_LDOX_UV_INT(3)), |
181 | REGMAP_IRQ_REG(TPS6594_IRQ_LDO4_SC, 4, TPS6594_BIT_LDOX_SC_INT(3)), |
182 | REGMAP_IRQ_REG(TPS6594_IRQ_LDO4_ILIM, 4, TPS6594_BIT_LDOX_ILIM_INT(3)), |
183 | |
184 | /* INT_VMON register */ |
185 | REGMAP_IRQ_REG(TPS6594_IRQ_VCCA_OV, 5, TPS6594_BIT_VCCA_OV_INT), |
186 | REGMAP_IRQ_REG(TPS6594_IRQ_VCCA_UV, 5, TPS6594_BIT_VCCA_UV_INT), |
187 | REGMAP_IRQ_REG(TPS6594_IRQ_VMON1_OV, 5, TPS6594_BIT_VMON1_OV_INT), |
188 | REGMAP_IRQ_REG(TPS6594_IRQ_VMON1_UV, 5, TPS6594_BIT_VMON1_UV_INT), |
189 | REGMAP_IRQ_REG(TPS6594_IRQ_VMON1_RV, 5, TPS6594_BIT_VMON1_RV_INT), |
190 | REGMAP_IRQ_REG(TPS6594_IRQ_VMON2_OV, 5, TPS6594_BIT_VMON2_OV_INT), |
191 | REGMAP_IRQ_REG(TPS6594_IRQ_VMON2_UV, 5, TPS6594_BIT_VMON2_UV_INT), |
192 | REGMAP_IRQ_REG(TPS6594_IRQ_VMON2_RV, 5, TPS6594_BIT_VMON2_RV_INT), |
193 | |
194 | /* INT_GPIO register */ |
195 | REGMAP_IRQ_REG(TPS6594_IRQ_GPIO9, 6, TPS6594_BIT_GPIO9_INT), |
196 | REGMAP_IRQ_REG(TPS6594_IRQ_GPIO10, 6, TPS6594_BIT_GPIO10_INT), |
197 | REGMAP_IRQ_REG(TPS6594_IRQ_GPIO11, 6, TPS6594_BIT_GPIO11_INT), |
198 | |
199 | /* INT_GPIO1_8 register */ |
200 | REGMAP_IRQ_REG(TPS6594_IRQ_GPIO1, 7, TPS6594_BIT_GPIOX_INT(0)), |
201 | REGMAP_IRQ_REG(TPS6594_IRQ_GPIO2, 7, TPS6594_BIT_GPIOX_INT(1)), |
202 | REGMAP_IRQ_REG(TPS6594_IRQ_GPIO3, 7, TPS6594_BIT_GPIOX_INT(2)), |
203 | REGMAP_IRQ_REG(TPS6594_IRQ_GPIO4, 7, TPS6594_BIT_GPIOX_INT(3)), |
204 | REGMAP_IRQ_REG(TPS6594_IRQ_GPIO5, 7, TPS6594_BIT_GPIOX_INT(4)), |
205 | REGMAP_IRQ_REG(TPS6594_IRQ_GPIO6, 7, TPS6594_BIT_GPIOX_INT(5)), |
206 | REGMAP_IRQ_REG(TPS6594_IRQ_GPIO7, 7, TPS6594_BIT_GPIOX_INT(6)), |
207 | REGMAP_IRQ_REG(TPS6594_IRQ_GPIO8, 7, TPS6594_BIT_GPIOX_INT(7)), |
208 | |
209 | /* INT_STARTUP register */ |
210 | REGMAP_IRQ_REG(TPS6594_IRQ_NPWRON_START, 8, TPS6594_BIT_NPWRON_START_INT), |
211 | REGMAP_IRQ_REG(TPS6594_IRQ_ENABLE, 8, TPS6594_BIT_ENABLE_INT), |
212 | REGMAP_IRQ_REG(TPS6594_IRQ_FSD, 8, TPS6594_BIT_FSD_INT), |
213 | REGMAP_IRQ_REG(TPS6594_IRQ_SOFT_REBOOT, 8, TPS6594_BIT_SOFT_REBOOT_INT), |
214 | |
215 | /* INT_MISC register */ |
216 | REGMAP_IRQ_REG(TPS6594_IRQ_BIST_PASS, 9, TPS6594_BIT_BIST_PASS_INT), |
217 | REGMAP_IRQ_REG(TPS6594_IRQ_EXT_CLK, 9, TPS6594_BIT_EXT_CLK_INT), |
218 | REGMAP_IRQ_REG(TPS6594_IRQ_TWARN, 9, TPS6594_BIT_TWARN_INT), |
219 | |
220 | /* INT_MODERATE_ERR register */ |
221 | REGMAP_IRQ_REG(TPS6594_IRQ_TSD_ORD, 10, TPS6594_BIT_TSD_ORD_INT), |
222 | REGMAP_IRQ_REG(TPS6594_IRQ_BIST_FAIL, 10, TPS6594_BIT_BIST_FAIL_INT), |
223 | REGMAP_IRQ_REG(TPS6594_IRQ_REG_CRC_ERR, 10, TPS6594_BIT_REG_CRC_ERR_INT), |
224 | REGMAP_IRQ_REG(TPS6594_IRQ_RECOV_CNT, 10, TPS6594_BIT_RECOV_CNT_INT), |
225 | REGMAP_IRQ_REG(TPS6594_IRQ_SPMI_ERR, 10, TPS6594_BIT_SPMI_ERR_INT), |
226 | REGMAP_IRQ_REG(TPS6594_IRQ_NPWRON_LONG, 10, TPS6594_BIT_NPWRON_LONG_INT), |
227 | REGMAP_IRQ_REG(TPS6594_IRQ_NINT_READBACK, 10, TPS6594_BIT_NINT_READBACK_INT), |
228 | REGMAP_IRQ_REG(TPS6594_IRQ_NRSTOUT_READBACK, 10, TPS6594_BIT_NRSTOUT_READBACK_INT), |
229 | |
230 | /* INT_SEVERE_ERR register */ |
231 | REGMAP_IRQ_REG(TPS6594_IRQ_TSD_IMM, 11, TPS6594_BIT_TSD_IMM_INT), |
232 | REGMAP_IRQ_REG(TPS6594_IRQ_VCCA_OVP, 11, TPS6594_BIT_VCCA_OVP_INT), |
233 | REGMAP_IRQ_REG(TPS6594_IRQ_PFSM_ERR, 11, TPS6594_BIT_PFSM_ERR_INT), |
234 | |
235 | /* INT_FSM_ERR register */ |
236 | REGMAP_IRQ_REG(TPS6594_IRQ_IMM_SHUTDOWN, 12, TPS6594_BIT_IMM_SHUTDOWN_INT), |
237 | REGMAP_IRQ_REG(TPS6594_IRQ_ORD_SHUTDOWN, 12, TPS6594_BIT_ORD_SHUTDOWN_INT), |
238 | REGMAP_IRQ_REG(TPS6594_IRQ_MCU_PWR_ERR, 12, TPS6594_BIT_MCU_PWR_ERR_INT), |
239 | REGMAP_IRQ_REG(TPS6594_IRQ_SOC_PWR_ERR, 12, TPS6594_BIT_SOC_PWR_ERR_INT), |
240 | |
241 | /* INT_COMM_ERR register */ |
242 | REGMAP_IRQ_REG(TPS6594_IRQ_COMM_FRM_ERR, 13, TPS6594_BIT_COMM_FRM_ERR_INT), |
243 | REGMAP_IRQ_REG(TPS6594_IRQ_COMM_CRC_ERR, 13, TPS6594_BIT_COMM_CRC_ERR_INT), |
244 | REGMAP_IRQ_REG(TPS6594_IRQ_COMM_ADR_ERR, 13, TPS6594_BIT_COMM_ADR_ERR_INT), |
245 | |
246 | /* INT_READBACK_ERR register */ |
247 | REGMAP_IRQ_REG(TPS6594_IRQ_EN_DRV_READBACK, 14, TPS6594_BIT_EN_DRV_READBACK_INT), |
248 | REGMAP_IRQ_REG(TPS6594_IRQ_NRSTOUT_SOC_READBACK, 14, TPS6594_BIT_NRSTOUT_SOC_READBACK_INT), |
249 | |
250 | /* INT_ESM register */ |
251 | REGMAP_IRQ_REG(TPS6594_IRQ_ESM_SOC_PIN, 15, TPS6594_BIT_ESM_SOC_PIN_INT), |
252 | REGMAP_IRQ_REG(TPS6594_IRQ_ESM_SOC_FAIL, 15, TPS6594_BIT_ESM_SOC_FAIL_INT), |
253 | REGMAP_IRQ_REG(TPS6594_IRQ_ESM_SOC_RST, 15, TPS6594_BIT_ESM_SOC_RST_INT), |
254 | |
255 | /* RTC_STATUS register */ |
256 | REGMAP_IRQ_REG(TPS6594_IRQ_TIMER, 16, TPS6594_BIT_TIMER), |
257 | REGMAP_IRQ_REG(TPS6594_IRQ_ALARM, 16, TPS6594_BIT_ALARM), |
258 | REGMAP_IRQ_REG(TPS6594_IRQ_POWER_UP, 16, TPS6594_BIT_POWER_UP), |
259 | }; |
260 | |
261 | static const unsigned int tps6594_irq_reg[] = { |
262 | TPS6594_REG_INT_BUCK1_2, |
263 | TPS6594_REG_INT_BUCK3_4, |
264 | TPS6594_REG_INT_BUCK5, |
265 | TPS6594_REG_INT_LDO1_2, |
266 | TPS6594_REG_INT_LDO3_4, |
267 | TPS6594_REG_INT_VMON, |
268 | TPS6594_REG_INT_GPIO, |
269 | TPS6594_REG_INT_GPIO1_8, |
270 | TPS6594_REG_INT_STARTUP, |
271 | TPS6594_REG_INT_MISC, |
272 | TPS6594_REG_INT_MODERATE_ERR, |
273 | TPS6594_REG_INT_SEVERE_ERR, |
274 | TPS6594_REG_INT_FSM_ERR, |
275 | TPS6594_REG_INT_COMM_ERR, |
276 | TPS6594_REG_INT_READBACK_ERR, |
277 | TPS6594_REG_INT_ESM, |
278 | TPS6594_REG_RTC_STATUS, |
279 | }; |
280 | |
281 | static inline unsigned int tps6594_get_irq_reg(struct regmap_irq_chip_data *data, |
282 | unsigned int base, int index) |
283 | { |
284 | return tps6594_irq_reg[index]; |
285 | }; |
286 | |
287 | static int tps6594_handle_post_irq(void *irq_drv_data) |
288 | { |
289 | struct tps6594 *tps = irq_drv_data; |
290 | int ret = 0; |
291 | |
292 | /* |
293 | * When CRC is enabled, writing to a read-only bit triggers an error, |
294 | * and COMM_ADR_ERR_INT bit is set. Besides, bits indicating interrupts |
295 | * (that must be cleared) and read-only bits are sometimes grouped in |
296 | * the same register. |
297 | * Since regmap clears interrupts by doing a write per register, clearing |
298 | * an interrupt bit in a register containing also a read-only bit makes |
299 | * COMM_ADR_ERR_INT bit set. Clear immediately this bit to avoid raising |
300 | * a new interrupt. |
301 | */ |
302 | if (tps->use_crc) |
303 | ret = regmap_write_bits(map: tps->regmap, TPS6594_REG_INT_COMM_ERR, |
304 | TPS6594_BIT_COMM_ADR_ERR_INT, |
305 | TPS6594_BIT_COMM_ADR_ERR_INT); |
306 | |
307 | return ret; |
308 | }; |
309 | |
310 | static struct regmap_irq_chip tps6594_irq_chip = { |
311 | .ack_base = TPS6594_REG_INT_BUCK1_2, |
312 | .ack_invert = 1, |
313 | .clear_ack = 1, |
314 | .init_ack_masked = 1, |
315 | .num_regs = ARRAY_SIZE(tps6594_irq_reg), |
316 | .irqs = tps6594_irqs, |
317 | .num_irqs = ARRAY_SIZE(tps6594_irqs), |
318 | .get_irq_reg = tps6594_get_irq_reg, |
319 | .handle_post_irq = tps6594_handle_post_irq, |
320 | }; |
321 | |
322 | bool tps6594_is_volatile_reg(struct device *dev, unsigned int reg) |
323 | { |
324 | return (reg >= TPS6594_REG_INT_TOP && reg <= TPS6594_REG_STAT_READBACK_ERR) || |
325 | reg == TPS6594_REG_RTC_STATUS; |
326 | } |
327 | EXPORT_SYMBOL_GPL(tps6594_is_volatile_reg); |
328 | |
329 | static int tps6594_check_crc_mode(struct tps6594 *tps, bool primary_pmic) |
330 | { |
331 | int ret; |
332 | |
333 | /* |
334 | * Check if CRC is enabled. |
335 | * Once CRC is enabled, it can't be disabled until next power cycle. |
336 | */ |
337 | tps->use_crc = true; |
338 | ret = regmap_test_bits(map: tps->regmap, TPS6594_REG_SERIAL_IF_CONFIG, |
339 | TPS6594_BIT_I2C1_SPI_CRC_EN); |
340 | if (ret == 0) { |
341 | ret = -EIO; |
342 | } else if (ret > 0) { |
343 | dev_info(tps->dev, "CRC feature enabled on %s PMIC" , |
344 | primary_pmic ? "primary" : "secondary" ); |
345 | ret = 0; |
346 | } |
347 | |
348 | return ret; |
349 | } |
350 | |
351 | static int tps6594_set_crc_feature(struct tps6594 *tps) |
352 | { |
353 | int ret; |
354 | |
355 | ret = tps6594_check_crc_mode(tps, primary_pmic: true); |
356 | if (ret) { |
357 | /* |
358 | * If CRC is not already enabled, force PFSM I2C_2 trigger to enable it |
359 | * on primary PMIC. |
360 | */ |
361 | tps->use_crc = false; |
362 | ret = regmap_write_bits(map: tps->regmap, TPS6594_REG_FSM_I2C_TRIGGERS, |
363 | TPS6594_BIT_TRIGGER_I2C(2), TPS6594_BIT_TRIGGER_I2C(2)); |
364 | if (ret) |
365 | return ret; |
366 | |
367 | /* |
368 | * Wait for PFSM to process trigger. |
369 | * The datasheet indicates 2 ms, and clock specification is +/-5%. |
370 | * 4 ms should provide sufficient margin. |
371 | */ |
372 | usleep_range(min: 4000, max: 5000); |
373 | |
374 | ret = tps6594_check_crc_mode(tps, primary_pmic: true); |
375 | } |
376 | |
377 | return ret; |
378 | } |
379 | |
380 | static int tps6594_enable_crc(struct tps6594 *tps) |
381 | { |
382 | struct device *dev = tps->dev; |
383 | unsigned int is_primary; |
384 | unsigned long timeout = msecs_to_jiffies(TPS6594_CRC_SYNC_TIMEOUT_MS); |
385 | int ret; |
386 | |
387 | /* |
388 | * CRC mode can be used with I2C or SPI protocols. |
389 | * If this mode is specified for primary PMIC, it will also be applied to secondary PMICs |
390 | * through SPMI serial interface. |
391 | * In this multi-PMIC synchronization scheme, the primary PMIC is the controller device |
392 | * on the SPMI bus, and the secondary PMICs are the target devices on the SPMI bus. |
393 | */ |
394 | is_primary = of_property_read_bool(np: dev->of_node, propname: "ti,primary-pmic" ); |
395 | if (is_primary) { |
396 | /* Enable CRC feature on primary PMIC */ |
397 | ret = tps6594_set_crc_feature(tps); |
398 | if (ret) |
399 | return ret; |
400 | |
401 | /* Notify secondary PMICs that CRC feature is enabled */ |
402 | complete_all(&tps6594_crc_comp); |
403 | } else { |
404 | /* Wait for CRC feature enabling event from primary PMIC */ |
405 | ret = wait_for_completion_interruptible_timeout(x: &tps6594_crc_comp, timeout); |
406 | if (ret == 0) |
407 | ret = -ETIMEDOUT; |
408 | else if (ret > 0) |
409 | ret = tps6594_check_crc_mode(tps, primary_pmic: false); |
410 | } |
411 | |
412 | return ret; |
413 | } |
414 | |
415 | int tps6594_device_init(struct tps6594 *tps, bool enable_crc) |
416 | { |
417 | struct device *dev = tps->dev; |
418 | int ret; |
419 | |
420 | if (enable_crc) { |
421 | ret = tps6594_enable_crc(tps); |
422 | if (ret) |
423 | return dev_err_probe(dev, err: ret, fmt: "Failed to enable CRC\n" ); |
424 | } |
425 | |
426 | /* Keep PMIC in ACTIVE state */ |
427 | ret = regmap_set_bits(map: tps->regmap, TPS6594_REG_FSM_NSLEEP_TRIGGERS, |
428 | TPS6594_BIT_NSLEEP1B | TPS6594_BIT_NSLEEP2B); |
429 | if (ret) |
430 | return dev_err_probe(dev, err: ret, fmt: "Failed to set PMIC state\n" ); |
431 | |
432 | tps6594_irq_chip.irq_drv_data = tps; |
433 | tps6594_irq_chip.name = devm_kasprintf(dev, GFP_KERNEL, fmt: "%s-%ld-0x%02x" , |
434 | dev->driver->name, tps->chip_id, tps->reg); |
435 | |
436 | if (!tps6594_irq_chip.name) |
437 | return -ENOMEM; |
438 | |
439 | ret = devm_regmap_add_irq_chip(dev, map: tps->regmap, irq: tps->irq, IRQF_SHARED | IRQF_ONESHOT, |
440 | irq_base: 0, chip: &tps6594_irq_chip, data: &tps->irq_data); |
441 | if (ret) |
442 | return dev_err_probe(dev, err: ret, fmt: "Failed to add regmap IRQ\n" ); |
443 | |
444 | ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, cells: tps6594_common_cells, |
445 | ARRAY_SIZE(tps6594_common_cells), NULL, irq_base: 0, |
446 | irq_domain: regmap_irq_get_domain(data: tps->irq_data)); |
447 | if (ret) |
448 | return dev_err_probe(dev, err: ret, fmt: "Failed to add common child devices\n" ); |
449 | |
450 | /* No RTC for LP8764 */ |
451 | if (tps->chip_id != LP8764) { |
452 | ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, cells: tps6594_rtc_cells, |
453 | ARRAY_SIZE(tps6594_rtc_cells), NULL, irq_base: 0, |
454 | irq_domain: regmap_irq_get_domain(data: tps->irq_data)); |
455 | if (ret) |
456 | return dev_err_probe(dev, err: ret, fmt: "Failed to add RTC child device\n" ); |
457 | } |
458 | |
459 | return 0; |
460 | } |
461 | EXPORT_SYMBOL_GPL(tps6594_device_init); |
462 | |
463 | MODULE_AUTHOR("Julien Panis <jpanis@baylibre.com>" ); |
464 | MODULE_DESCRIPTION("TPS6594 Driver" ); |
465 | MODULE_LICENSE("GPL" ); |
466 | |