1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * Copyright 2018-2020 Broadcom. |
4 | */ |
5 | |
6 | #ifndef BCM_VK_H |
7 | #define BCM_VK_H |
8 | |
9 | #include <linux/atomic.h> |
10 | #include <linux/firmware.h> |
11 | #include <linux/irq.h> |
12 | #include <linux/kref.h> |
13 | #include <linux/miscdevice.h> |
14 | #include <linux/mutex.h> |
15 | #include <linux/pci.h> |
16 | #include <linux/poll.h> |
17 | #include <linux/sched/signal.h> |
18 | #include <linux/tty.h> |
19 | #include <linux/uaccess.h> |
20 | #include <uapi/linux/misc/bcm_vk.h> |
21 | |
22 | #include "bcm_vk_msg.h" |
23 | |
24 | #define DRV_MODULE_NAME "bcm-vk" |
25 | |
26 | /* |
27 | * Load Image is completed in two stages: |
28 | * |
29 | * 1) When the VK device boot-up, M7 CPU runs and executes the BootROM. |
30 | * The Secure Boot Loader (SBL) as part of the BootROM will run |
31 | * to open up ITCM for host to push BOOT1 image. |
32 | * SBL will authenticate the image before jumping to BOOT1 image. |
33 | * |
34 | * 2) Because BOOT1 image is a secured image, we also called it the |
35 | * Secure Boot Image (SBI). At second stage, SBI will initialize DDR |
36 | * and wait for host to push BOOT2 image to DDR. |
37 | * SBI will authenticate the image before jumping to BOOT2 image. |
38 | * |
39 | */ |
40 | /* Location of registers of interest in BAR0 */ |
41 | |
42 | /* Request register for Secure Boot Loader (SBL) download */ |
43 | #define BAR_CODEPUSH_SBL 0x400 |
44 | /* Start of ITCM */ |
45 | #define CODEPUSH_BOOT1_ENTRY 0x00400000 |
46 | #define CODEPUSH_MASK 0xfffff000 |
47 | #define CODEPUSH_BOOTSTART BIT(0) |
48 | |
49 | /* Boot Status register */ |
50 | #define BAR_BOOT_STATUS 0x404 |
51 | |
52 | #define SRAM_OPEN BIT(16) |
53 | #define DDR_OPEN BIT(17) |
54 | |
55 | /* Firmware loader progress status definitions */ |
56 | #define FW_LOADER_ACK_SEND_MORE_DATA BIT(18) |
57 | #define FW_LOADER_ACK_IN_PROGRESS BIT(19) |
58 | #define FW_LOADER_ACK_RCVD_ALL_DATA BIT(20) |
59 | |
60 | /* Boot1/2 is running in standalone mode */ |
61 | #define BOOT_STDALONE_RUNNING BIT(21) |
62 | |
63 | /* definitions for boot status register */ |
64 | #define BOOT_STATE_MASK (0xffffffff & \ |
65 | ~(FW_LOADER_ACK_SEND_MORE_DATA | \ |
66 | FW_LOADER_ACK_IN_PROGRESS | \ |
67 | BOOT_STDALONE_RUNNING)) |
68 | |
69 | #define BOOT_ERR_SHIFT 4 |
70 | #define BOOT_ERR_MASK (0xf << BOOT_ERR_SHIFT) |
71 | #define BOOT_PROG_MASK 0xf |
72 | |
73 | #define BROM_STATUS_NOT_RUN 0x2 |
74 | #define BROM_NOT_RUN (SRAM_OPEN | BROM_STATUS_NOT_RUN) |
75 | #define BROM_STATUS_COMPLETE 0x6 |
76 | #define BROM_RUNNING (SRAM_OPEN | BROM_STATUS_COMPLETE) |
77 | #define BOOT1_STATUS_COMPLETE 0x6 |
78 | #define BOOT1_RUNNING (DDR_OPEN | BOOT1_STATUS_COMPLETE) |
79 | #define BOOT2_STATUS_COMPLETE 0x6 |
80 | #define BOOT2_RUNNING (FW_LOADER_ACK_RCVD_ALL_DATA | \ |
81 | BOOT2_STATUS_COMPLETE) |
82 | |
83 | /* Boot request for Secure Boot Image (SBI) */ |
84 | #define BAR_CODEPUSH_SBI 0x408 |
85 | /* 64M mapped to BAR2 */ |
86 | #define CODEPUSH_BOOT2_ENTRY 0x60000000 |
87 | |
88 | #define BAR_CARD_STATUS 0x410 |
89 | /* CARD_STATUS definitions */ |
90 | #define CARD_STATUS_TTYVK0_READY BIT(0) |
91 | #define CARD_STATUS_TTYVK1_READY BIT(1) |
92 | |
93 | #define BAR_BOOT1_STDALONE_PROGRESS 0x420 |
94 | #define BOOT1_STDALONE_SUCCESS (BIT(13) | BIT(14)) |
95 | #define BOOT1_STDALONE_PROGRESS_MASK BOOT1_STDALONE_SUCCESS |
96 | |
97 | #define BAR_METADATA_VERSION 0x440 |
98 | #define BAR_OS_UPTIME 0x444 |
99 | #define BAR_CHIP_ID 0x448 |
100 | #define MAJOR_SOC_REV(_chip_id) (((_chip_id) >> 20) & 0xf) |
101 | |
102 | #define BAR_CARD_TEMPERATURE 0x45c |
103 | /* defines for all temperature sensor */ |
104 | #define BCM_VK_TEMP_FIELD_MASK 0xff |
105 | #define BCM_VK_CPU_TEMP_SHIFT 0 |
106 | #define BCM_VK_DDR0_TEMP_SHIFT 8 |
107 | #define BCM_VK_DDR1_TEMP_SHIFT 16 |
108 | |
109 | #define BAR_CARD_VOLTAGE 0x460 |
110 | /* defines for voltage rail conversion */ |
111 | #define BCM_VK_VOLT_RAIL_MASK 0xffff |
112 | #define BCM_VK_3P3_VOLT_REG_SHIFT 16 |
113 | |
114 | #define BAR_CARD_ERR_LOG 0x464 |
115 | /* Error log register bit definition - register for error alerts */ |
116 | #define ERR_LOG_UECC BIT(0) |
117 | #define ERR_LOG_SSIM_BUSY BIT(1) |
118 | #define ERR_LOG_AFBC_BUSY BIT(2) |
119 | #define ERR_LOG_HIGH_TEMP_ERR BIT(3) |
120 | #define ERR_LOG_WDOG_TIMEOUT BIT(4) |
121 | #define ERR_LOG_SYS_FAULT BIT(5) |
122 | #define ERR_LOG_RAMDUMP BIT(6) |
123 | #define ERR_LOG_COP_WDOG_TIMEOUT BIT(7) |
124 | /* warnings */ |
125 | #define ERR_LOG_MEM_ALLOC_FAIL BIT(8) |
126 | #define ERR_LOG_LOW_TEMP_WARN BIT(9) |
127 | #define ERR_LOG_ECC BIT(10) |
128 | #define ERR_LOG_IPC_DWN BIT(11) |
129 | |
130 | /* Alert bit definitions detectd on host */ |
131 | #define ERR_LOG_HOST_INTF_V_FAIL BIT(13) |
132 | #define ERR_LOG_HOST_HB_FAIL BIT(14) |
133 | #define ERR_LOG_HOST_PCIE_DWN BIT(15) |
134 | |
135 | #define BAR_CARD_ERR_MEM 0x468 |
136 | /* defines for mem err, all fields have same width */ |
137 | #define BCM_VK_MEM_ERR_FIELD_MASK 0xff |
138 | #define BCM_VK_ECC_MEM_ERR_SHIFT 0 |
139 | #define BCM_VK_UECC_MEM_ERR_SHIFT 8 |
140 | /* threshold of event occurrence and logs start to come out */ |
141 | #define BCM_VK_ECC_THRESHOLD 10 |
142 | #define BCM_VK_UECC_THRESHOLD 1 |
143 | |
144 | #define BAR_CARD_PWR_AND_THRE 0x46c |
145 | /* defines for power and temp threshold, all fields have same width */ |
146 | #define BCM_VK_PWR_AND_THRE_FIELD_MASK 0xff |
147 | #define BCM_VK_LOW_TEMP_THRE_SHIFT 0 |
148 | #define BCM_VK_HIGH_TEMP_THRE_SHIFT 8 |
149 | #define BCM_VK_PWR_STATE_SHIFT 16 |
150 | |
151 | #define BAR_CARD_STATIC_INFO 0x470 |
152 | |
153 | #define BAR_INTF_VER 0x47c |
154 | #define BAR_INTF_VER_MAJOR_SHIFT 16 |
155 | #define BAR_INTF_VER_MASK 0xffff |
156 | /* |
157 | * major and minor semantic version numbers supported |
158 | * Please update as required on interface changes |
159 | */ |
160 | #define SEMANTIC_MAJOR 1 |
161 | #define SEMANTIC_MINOR 0 |
162 | |
163 | /* |
164 | * first door bell reg, ie for queue = 0. Only need the first one, as |
165 | * we will use the queue number to derive the others |
166 | */ |
167 | #define VK_BAR0_REGSEG_DB_BASE 0x484 |
168 | #define VK_BAR0_REGSEG_DB_REG_GAP 8 /* |
169 | * DB register gap, |
170 | * DB1 at 0x48c and DB2 at 0x494 |
171 | */ |
172 | |
173 | /* reset register and specific values */ |
174 | #define VK_BAR0_RESET_DB_NUM 3 |
175 | #define VK_BAR0_RESET_DB_SOFT 0xffffffff |
176 | #define VK_BAR0_RESET_DB_HARD 0xfffffffd |
177 | #define VK_BAR0_RESET_RAMPDUMP 0xa0000000 |
178 | |
179 | #define VK_BAR0_Q_DB_BASE(q_num) (VK_BAR0_REGSEG_DB_BASE + \ |
180 | ((q_num) * VK_BAR0_REGSEG_DB_REG_GAP)) |
181 | #define VK_BAR0_RESET_DB_BASE (VK_BAR0_REGSEG_DB_BASE + \ |
182 | (VK_BAR0_RESET_DB_NUM * VK_BAR0_REGSEG_DB_REG_GAP)) |
183 | |
184 | #define BAR_BOOTSRC_SELECT 0xc78 |
185 | /* BOOTSRC definitions */ |
186 | #define BOOTSRC_SOFT_ENABLE BIT(14) |
187 | |
188 | /* Card OS Firmware version size */ |
189 | #define BAR_FIRMWARE_TAG_SIZE 50 |
190 | #define FIRMWARE_STATUS_PRE_INIT_DONE 0x1f |
191 | |
192 | /* VK MSG_ID defines */ |
193 | #define VK_MSG_ID_BITMAP_SIZE 4096 |
194 | #define VK_MSG_ID_BITMAP_MASK (VK_MSG_ID_BITMAP_SIZE - 1) |
195 | #define VK_MSG_ID_OVERFLOW 0xffff |
196 | |
197 | /* |
198 | * BAR1 |
199 | */ |
200 | |
201 | /* BAR1 message q definition */ |
202 | |
203 | /* indicate if msgq ctrl in BAR1 is populated */ |
204 | #define VK_BAR1_MSGQ_DEF_RDY 0x60c0 |
205 | /* ready marker value for the above location, normal boot2 */ |
206 | #define VK_BAR1_MSGQ_RDY_MARKER 0xbeefcafe |
207 | /* ready marker value for the above location, normal boot2 */ |
208 | #define VK_BAR1_DIAG_RDY_MARKER 0xdeadcafe |
209 | /* number of msgqs in BAR1 */ |
210 | #define VK_BAR1_MSGQ_NR 0x60c4 |
211 | /* BAR1 queue control structure offset */ |
212 | #define VK_BAR1_MSGQ_CTRL_OFF 0x60c8 |
213 | |
214 | /* BAR1 ucode and boot1 version tag */ |
215 | #define VK_BAR1_UCODE_VER_TAG 0x6170 |
216 | #define VK_BAR1_BOOT1_VER_TAG 0x61b0 |
217 | #define VK_BAR1_VER_TAG_SIZE 64 |
218 | |
219 | /* Memory to hold the DMA buffer memory address allocated for boot2 download */ |
220 | #define VK_BAR1_DMA_BUF_OFF_HI 0x61e0 |
221 | #define VK_BAR1_DMA_BUF_OFF_LO (VK_BAR1_DMA_BUF_OFF_HI + 4) |
222 | #define VK_BAR1_DMA_BUF_SZ (VK_BAR1_DMA_BUF_OFF_HI + 8) |
223 | |
224 | /* Scratch memory allocated on host for VK */ |
225 | #define VK_BAR1_SCRATCH_OFF_HI 0x61f0 |
226 | #define VK_BAR1_SCRATCH_OFF_LO (VK_BAR1_SCRATCH_OFF_HI + 4) |
227 | #define VK_BAR1_SCRATCH_SZ_ADDR (VK_BAR1_SCRATCH_OFF_HI + 8) |
228 | #define VK_BAR1_SCRATCH_DEF_NR_PAGES 32 |
229 | |
230 | /* BAR1 DAUTH info */ |
231 | #define VK_BAR1_DAUTH_BASE_ADDR 0x6200 |
232 | #define VK_BAR1_DAUTH_STORE_SIZE 0x48 |
233 | #define VK_BAR1_DAUTH_VALID_SIZE 0x8 |
234 | #define VK_BAR1_DAUTH_MAX 4 |
235 | #define VK_BAR1_DAUTH_STORE_ADDR(x) \ |
236 | (VK_BAR1_DAUTH_BASE_ADDR + \ |
237 | (x) * (VK_BAR1_DAUTH_STORE_SIZE + VK_BAR1_DAUTH_VALID_SIZE)) |
238 | #define VK_BAR1_DAUTH_VALID_ADDR(x) \ |
239 | (VK_BAR1_DAUTH_STORE_ADDR(x) + VK_BAR1_DAUTH_STORE_SIZE) |
240 | |
241 | /* BAR1 SOTP AUTH and REVID info */ |
242 | #define VK_BAR1_SOTP_REVID_BASE_ADDR 0x6340 |
243 | #define VK_BAR1_SOTP_REVID_SIZE 0x10 |
244 | #define VK_BAR1_SOTP_REVID_MAX 2 |
245 | #define VK_BAR1_SOTP_REVID_ADDR(x) \ |
246 | (VK_BAR1_SOTP_REVID_BASE_ADDR + (x) * VK_BAR1_SOTP_REVID_SIZE) |
247 | |
248 | /* VK device supports a maximum of 3 bars */ |
249 | #define MAX_BAR 3 |
250 | |
251 | /* default number of msg blk for inband SGL */ |
252 | #define BCM_VK_DEF_IB_SGL_BLK_LEN 16 |
253 | #define BCM_VK_IB_SGL_BLK_MAX 24 |
254 | |
255 | enum pci_barno { |
256 | BAR_0 = 0, |
257 | BAR_1, |
258 | BAR_2 |
259 | }; |
260 | |
261 | #ifdef CONFIG_BCM_VK_TTY |
262 | #define BCM_VK_NUM_TTY 2 |
263 | #else |
264 | #define BCM_VK_NUM_TTY 0 |
265 | #endif |
266 | |
267 | struct bcm_vk_tty { |
268 | struct tty_port port; |
269 | u32 to_offset; /* bar offset to use */ |
270 | u32 to_size; /* to VK buffer size */ |
271 | u32 wr; /* write offset shadow */ |
272 | u32 from_offset; /* bar offset to use */ |
273 | u32 from_size; /* from VK buffer size */ |
274 | u32 rd; /* read offset shadow */ |
275 | pid_t pid; |
276 | bool irq_enabled; |
277 | bool is_opened; /* tracks tty open/close */ |
278 | }; |
279 | |
280 | /* VK device max power state, supports 3, full, reduced and low */ |
281 | #define MAX_OPP 3 |
282 | #define MAX_CARD_INFO_TAG_SIZE 64 |
283 | |
284 | struct bcm_vk_card_info { |
285 | u32 version; |
286 | char os_tag[MAX_CARD_INFO_TAG_SIZE]; |
287 | char cmpt_tag[MAX_CARD_INFO_TAG_SIZE]; |
288 | u32 cpu_freq_mhz; |
289 | u32 cpu_scale[MAX_OPP]; |
290 | u32 ddr_freq_mhz; |
291 | u32 ddr_size_MB; |
292 | u32 video_core_freq_mhz; |
293 | }; |
294 | |
295 | /* DAUTH related info */ |
296 | struct bcm_vk_dauth_key { |
297 | char store[VK_BAR1_DAUTH_STORE_SIZE]; |
298 | char valid[VK_BAR1_DAUTH_VALID_SIZE]; |
299 | }; |
300 | |
301 | struct bcm_vk_dauth_info { |
302 | struct bcm_vk_dauth_key keys[VK_BAR1_DAUTH_MAX]; |
303 | }; |
304 | |
305 | /* |
306 | * Control structure of logging messages from the card. This |
307 | * buffer is for logmsg that comes from vk |
308 | */ |
309 | struct bcm_vk_peer_log { |
310 | u32 rd_idx; |
311 | u32 wr_idx; |
312 | u32 buf_size; |
313 | u32 mask; |
314 | char data[]; |
315 | }; |
316 | |
317 | /* max buf size allowed */ |
318 | #define BCM_VK_PEER_LOG_BUF_MAX SZ_16K |
319 | /* max size per line of peer log */ |
320 | #define BCM_VK_PEER_LOG_LINE_MAX 256 |
321 | |
322 | /* |
323 | * single entry for processing type + utilization |
324 | */ |
325 | #define BCM_VK_PROC_TYPE_TAG_LEN 8 |
326 | struct bcm_vk_proc_mon_entry_t { |
327 | char tag[BCM_VK_PROC_TYPE_TAG_LEN]; |
328 | u32 used; |
329 | u32 max; /**< max capacity */ |
330 | }; |
331 | |
332 | /** |
333 | * Structure for run time utilization |
334 | */ |
335 | #define BCM_VK_PROC_MON_MAX 8 /* max entries supported */ |
336 | struct bcm_vk_proc_mon_info { |
337 | u32 num; /**< no of entries */ |
338 | u32 entry_size; /**< per entry size */ |
339 | struct bcm_vk_proc_mon_entry_t entries[BCM_VK_PROC_MON_MAX]; |
340 | }; |
341 | |
342 | struct bcm_vk_hb_ctrl { |
343 | struct delayed_work work; |
344 | u32 last_uptime; |
345 | u32 lost_cnt; |
346 | }; |
347 | |
348 | struct bcm_vk_alert { |
349 | u16 flags; |
350 | u16 notfs; |
351 | }; |
352 | |
353 | /* some alert counters that the driver will keep track */ |
354 | struct bcm_vk_alert_cnts { |
355 | u16 ecc; |
356 | u16 uecc; |
357 | }; |
358 | |
359 | struct bcm_vk { |
360 | struct pci_dev *pdev; |
361 | void __iomem *bar[MAX_BAR]; |
362 | int num_irqs; |
363 | |
364 | struct bcm_vk_card_info card_info; |
365 | struct bcm_vk_proc_mon_info proc_mon_info; |
366 | struct bcm_vk_dauth_info dauth_info; |
367 | |
368 | /* mutex to protect the ioctls */ |
369 | struct mutex mutex; |
370 | struct miscdevice miscdev; |
371 | int devid; /* dev id allocated */ |
372 | |
373 | #ifdef CONFIG_BCM_VK_TTY |
374 | struct tty_driver *tty_drv; |
375 | struct timer_list serial_timer; |
376 | struct bcm_vk_tty tty[BCM_VK_NUM_TTY]; |
377 | struct workqueue_struct *tty_wq_thread; |
378 | struct work_struct tty_wq_work; |
379 | #endif |
380 | |
381 | /* Reference-counting to handle file operations */ |
382 | struct kref kref; |
383 | |
384 | spinlock_t msg_id_lock; /* Spinlock for msg_id */ |
385 | u16 msg_id; |
386 | DECLARE_BITMAP(bmap, VK_MSG_ID_BITMAP_SIZE); |
387 | spinlock_t ctx_lock; /* Spinlock for component context */ |
388 | struct bcm_vk_ctx ctx[VK_CMPT_CTX_MAX]; |
389 | struct bcm_vk_ht_entry pid_ht[VK_PID_HT_SZ]; |
390 | pid_t reset_pid; /* process that issue reset */ |
391 | |
392 | atomic_t msgq_inited; /* indicate if info has been synced with vk */ |
393 | struct bcm_vk_msg_chan to_v_msg_chan; |
394 | struct bcm_vk_msg_chan to_h_msg_chan; |
395 | |
396 | struct workqueue_struct *wq_thread; |
397 | struct work_struct wq_work; /* work queue for deferred job */ |
398 | unsigned long wq_offload[1]; /* various flags on wq requested */ |
399 | void *tdma_vaddr; /* test dma segment virtual addr */ |
400 | dma_addr_t tdma_addr; /* test dma segment bus addr */ |
401 | |
402 | struct notifier_block panic_nb; |
403 | u32 ib_sgl_size; /* size allocated for inband sgl insertion */ |
404 | |
405 | /* heart beat mechanism control structure */ |
406 | struct bcm_vk_hb_ctrl hb_ctrl; |
407 | /* house-keeping variable of error logs */ |
408 | spinlock_t host_alert_lock; /* protection to access host_alert struct */ |
409 | struct bcm_vk_alert host_alert; |
410 | struct bcm_vk_alert peer_alert; /* bits set by the card */ |
411 | struct bcm_vk_alert_cnts alert_cnts; |
412 | |
413 | /* offset of the peer log control in BAR2 */ |
414 | u32 peerlog_off; |
415 | struct bcm_vk_peer_log peerlog_info; /* record of peer log info */ |
416 | /* offset of processing monitoring info in BAR2 */ |
417 | u32 proc_mon_off; |
418 | }; |
419 | |
420 | /* wq offload work items bits definitions */ |
421 | enum bcm_vk_wq_offload_flags { |
422 | BCM_VK_WQ_DWNLD_PEND = 0, |
423 | BCM_VK_WQ_DWNLD_AUTO = 1, |
424 | BCM_VK_WQ_NOTF_PEND = 2, |
425 | }; |
426 | |
427 | /* a macro to get an individual field with mask and shift */ |
428 | #define (_field, _reg, _mask, _shift) \ |
429 | (_field = (((_reg) >> (_shift)) & (_mask))) |
430 | |
431 | struct bcm_vk_entry { |
432 | const u32 mask; |
433 | const u32 exp_val; |
434 | const char *str; |
435 | }; |
436 | |
437 | /* alerts that could be generated from peer */ |
438 | #define BCM_VK_PEER_ERR_NUM 12 |
439 | extern struct bcm_vk_entry const bcm_vk_peer_err[BCM_VK_PEER_ERR_NUM]; |
440 | /* alerts detected by the host */ |
441 | #define BCM_VK_HOST_ERR_NUM 3 |
442 | extern struct bcm_vk_entry const bcm_vk_host_err[BCM_VK_HOST_ERR_NUM]; |
443 | |
444 | /* |
445 | * check if PCIe interface is down on read. Use it when it is |
446 | * certain that _val should never be all ones. |
447 | */ |
448 | #define BCM_VK_INTF_IS_DOWN(val) ((val) == 0xffffffff) |
449 | |
450 | static inline u32 vkread32(struct bcm_vk *vk, enum pci_barno bar, u64 offset) |
451 | { |
452 | return readl(addr: vk->bar[bar] + offset); |
453 | } |
454 | |
455 | static inline void vkwrite32(struct bcm_vk *vk, |
456 | u32 value, |
457 | enum pci_barno bar, |
458 | u64 offset) |
459 | { |
460 | writel(val: value, addr: vk->bar[bar] + offset); |
461 | } |
462 | |
463 | static inline u8 vkread8(struct bcm_vk *vk, enum pci_barno bar, u64 offset) |
464 | { |
465 | return readb(addr: vk->bar[bar] + offset); |
466 | } |
467 | |
468 | static inline void vkwrite8(struct bcm_vk *vk, |
469 | u8 value, |
470 | enum pci_barno bar, |
471 | u64 offset) |
472 | { |
473 | writeb(val: value, addr: vk->bar[bar] + offset); |
474 | } |
475 | |
476 | static inline bool bcm_vk_msgq_marker_valid(struct bcm_vk *vk) |
477 | { |
478 | u32 rdy_marker = 0; |
479 | u32 fw_status; |
480 | |
481 | fw_status = vkread32(vk, bar: BAR_0, VK_BAR_FWSTS); |
482 | |
483 | if ((fw_status & VK_FWSTS_READY) == VK_FWSTS_READY) |
484 | rdy_marker = vkread32(vk, bar: BAR_1, VK_BAR1_MSGQ_DEF_RDY); |
485 | |
486 | return (rdy_marker == VK_BAR1_MSGQ_RDY_MARKER); |
487 | } |
488 | |
489 | int bcm_vk_open(struct inode *inode, struct file *p_file); |
490 | ssize_t bcm_vk_read(struct file *p_file, char __user *buf, size_t count, |
491 | loff_t *f_pos); |
492 | ssize_t bcm_vk_write(struct file *p_file, const char __user *buf, |
493 | size_t count, loff_t *f_pos); |
494 | __poll_t bcm_vk_poll(struct file *p_file, struct poll_table_struct *wait); |
495 | int bcm_vk_release(struct inode *inode, struct file *p_file); |
496 | void bcm_vk_release_data(struct kref *kref); |
497 | irqreturn_t bcm_vk_msgq_irqhandler(int irq, void *dev_id); |
498 | irqreturn_t bcm_vk_notf_irqhandler(int irq, void *dev_id); |
499 | irqreturn_t bcm_vk_tty_irqhandler(int irq, void *dev_id); |
500 | int bcm_vk_msg_init(struct bcm_vk *vk); |
501 | void bcm_vk_msg_remove(struct bcm_vk *vk); |
502 | void bcm_vk_drain_msg_on_reset(struct bcm_vk *vk); |
503 | int bcm_vk_sync_msgq(struct bcm_vk *vk, bool force_sync); |
504 | void bcm_vk_blk_drv_access(struct bcm_vk *vk); |
505 | s32 bcm_to_h_msg_dequeue(struct bcm_vk *vk); |
506 | int bcm_vk_send_shutdown_msg(struct bcm_vk *vk, u32 shut_type, |
507 | const pid_t pid, const u32 q_num); |
508 | void bcm_to_v_q_doorbell(struct bcm_vk *vk, u32 q_num, u32 db_val); |
509 | int bcm_vk_auto_load_all_images(struct bcm_vk *vk); |
510 | void bcm_vk_hb_init(struct bcm_vk *vk); |
511 | void bcm_vk_hb_deinit(struct bcm_vk *vk); |
512 | void bcm_vk_handle_notf(struct bcm_vk *vk); |
513 | bool bcm_vk_drv_access_ok(struct bcm_vk *vk); |
514 | void bcm_vk_set_host_alert(struct bcm_vk *vk, u32 bit_mask); |
515 | |
516 | #ifdef CONFIG_BCM_VK_TTY |
517 | int bcm_vk_tty_init(struct bcm_vk *vk, char *name); |
518 | void bcm_vk_tty_exit(struct bcm_vk *vk); |
519 | void bcm_vk_tty_terminate_tty_user(struct bcm_vk *vk); |
520 | void bcm_vk_tty_wq_exit(struct bcm_vk *vk); |
521 | |
522 | static inline void bcm_vk_tty_set_irq_enabled(struct bcm_vk *vk, int index) |
523 | { |
524 | vk->tty[index].irq_enabled = true; |
525 | } |
526 | #else |
527 | static inline int bcm_vk_tty_init(struct bcm_vk *vk, char *name) |
528 | { |
529 | return 0; |
530 | } |
531 | |
532 | static inline void bcm_vk_tty_exit(struct bcm_vk *vk) |
533 | { |
534 | } |
535 | |
536 | static inline void bcm_vk_tty_terminate_tty_user(struct bcm_vk *vk) |
537 | { |
538 | } |
539 | |
540 | static inline void bcm_vk_tty_wq_exit(struct bcm_vk *vk) |
541 | { |
542 | } |
543 | |
544 | static inline void bcm_vk_tty_set_irq_enabled(struct bcm_vk *vk, int index) |
545 | { |
546 | } |
547 | #endif /* CONFIG_BCM_VK_TTY */ |
548 | |
549 | #endif |
550 | |