1	// SPDX-License-Identifier: GPL-2.0
2	/* Realtek SMI subdriver for the Realtek RTL8366RB ethernet switch
3	*
4	* This is a sparsely documented chip, the only viable documentation seems
5	* to be a patched up code drop from the vendor that appear in various
6	* GPL source trees.
7	*
8	* Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
9	* Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
10	* Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
11	* Copyright (C) 2010 Roman Yeryomin <roman@advem.lv>
12	* Copyright (C) 2011 Colin Leitner <colin.leitner@googlemail.com>
13	*/
14
15	#include <linux/bitops.h>
16	#include <linux/etherdevice.h>
17	#include <linux/if_bridge.h>
18	#include <linux/if_vlan.h>
19	#include <linux/interrupt.h>
20	#include <linux/irqdomain.h>
21	#include <linux/irqchip/chained_irq.h>
22	#include <linux/of_irq.h>
23	#include <linux/regmap.h>
24
25	#include "realtek.h"
26	#include "realtek-smi.h"
27	#include "realtek-mdio.h"
28	#include "rtl83xx.h"
29
30	#define RTL8366RB_PORT_NUM_CPU 5
31	#define RTL8366RB_NUM_PORTS 6
32	#define RTL8366RB_PHY_NO_MAX 4
33	#define RTL8366RB_PHY_ADDR_MAX 31
34
35	/* Switch Global Configuration register */
36	#define RTL8366RB_SGCR 0x0000
37	#define RTL8366RB_SGCR_EN_BC_STORM_CTRL BIT(0)
38	#define RTL8366RB_SGCR_MAX_LENGTH(a) ((a) << 4)
39	#define RTL8366RB_SGCR_MAX_LENGTH_MASK RTL8366RB_SGCR_MAX_LENGTH(0x3)
40	#define RTL8366RB_SGCR_MAX_LENGTH_1522 RTL8366RB_SGCR_MAX_LENGTH(0x0)
41	#define RTL8366RB_SGCR_MAX_LENGTH_1536 RTL8366RB_SGCR_MAX_LENGTH(0x1)
42	#define RTL8366RB_SGCR_MAX_LENGTH_1552 RTL8366RB_SGCR_MAX_LENGTH(0x2)
43	#define RTL8366RB_SGCR_MAX_LENGTH_16000 RTL8366RB_SGCR_MAX_LENGTH(0x3)
44	#define RTL8366RB_SGCR_EN_VLAN BIT(13)
45	#define RTL8366RB_SGCR_EN_VLAN_4KTB BIT(14)
46
47	/* Port Enable Control register */
48	#define RTL8366RB_PECR 0x0001
49
50	/* Switch per-port learning disablement register */
51	#define RTL8366RB_PORT_LEARNDIS_CTRL 0x0002
52
53	/* Security control, actually aging register */
54	#define RTL8366RB_SECURITY_CTRL 0x0003
55
56	#define RTL8366RB_SSCR2 0x0004
57	#define RTL8366RB_SSCR2_DROP_UNKNOWN_DA BIT(0)
58
59	/* Port Mode Control registers */
60	#define RTL8366RB_PMC0 0x0005
61	#define RTL8366RB_PMC0_SPI BIT(0)
62	#define RTL8366RB_PMC0_EN_AUTOLOAD BIT(1)
63	#define RTL8366RB_PMC0_PROBE BIT(2)
64	#define RTL8366RB_PMC0_DIS_BISR BIT(3)
65	#define RTL8366RB_PMC0_ADCTEST BIT(4)
66	#define RTL8366RB_PMC0_SRAM_DIAG BIT(5)
67	#define RTL8366RB_PMC0_EN_SCAN BIT(6)
68	#define RTL8366RB_PMC0_P4_IOMODE_SHIFT 7
69	#define RTL8366RB_PMC0_P4_IOMODE_MASK GENMASK(9, 7)
70	#define RTL8366RB_PMC0_P5_IOMODE_SHIFT 10
71	#define RTL8366RB_PMC0_P5_IOMODE_MASK GENMASK(12, 10)
72	#define RTL8366RB_PMC0_SDSMODE_SHIFT 13
73	#define RTL8366RB_PMC0_SDSMODE_MASK GENMASK(15, 13)
74	#define RTL8366RB_PMC1 0x0006
75
76	/* Port Mirror Control Register */
77	#define RTL8366RB_PMCR 0x0007
78	#define RTL8366RB_PMCR_SOURCE_PORT(a) (a)
79	#define RTL8366RB_PMCR_SOURCE_PORT_MASK 0x000f
80	#define RTL8366RB_PMCR_MONITOR_PORT(a) ((a) << 4)
81	#define RTL8366RB_PMCR_MONITOR_PORT_MASK 0x00f0
82	#define RTL8366RB_PMCR_MIRROR_RX BIT(8)
83	#define RTL8366RB_PMCR_MIRROR_TX BIT(9)
84	#define RTL8366RB_PMCR_MIRROR_SPC BIT(10)
85	#define RTL8366RB_PMCR_MIRROR_ISO BIT(11)
86
87	/* bits 0..7 = port 0, bits 8..15 = port 1 */
88	#define RTL8366RB_PAACR0 0x0010
89	/* bits 0..7 = port 2, bits 8..15 = port 3 */
90	#define RTL8366RB_PAACR1 0x0011
91	/* bits 0..7 = port 4, bits 8..15 = port 5 */
92	#define RTL8366RB_PAACR2 0x0012
93	#define RTL8366RB_PAACR_SPEED_10M 0
94	#define RTL8366RB_PAACR_SPEED_100M 1
95	#define RTL8366RB_PAACR_SPEED_1000M 2
96	#define RTL8366RB_PAACR_FULL_DUPLEX BIT(2)
97	#define RTL8366RB_PAACR_LINK_UP BIT(4)
98	#define RTL8366RB_PAACR_TX_PAUSE BIT(5)
99	#define RTL8366RB_PAACR_RX_PAUSE BIT(6)
100	#define RTL8366RB_PAACR_AN BIT(7)
101
102	/* bits 0..7 = port 0, bits 8..15 = port 1 */
103	#define RTL8366RB_PSTAT0 0x0014
104	/* bits 0..7 = port 2, bits 8..15 = port 3 */
105	#define RTL8366RB_PSTAT1 0x0015
106	/* bits 0..7 = port 4, bits 8..15 = port 5 */
107	#define RTL8366RB_PSTAT2 0x0016
108
109	#define RTL8366RB_POWER_SAVING_REG 0x0021
110
111	/* Spanning tree status (STP) control, two bits per port per FID */
112	#define RTL8366RB_STP_STATE_BASE 0x0050 /* 0x0050..0x0057 */
113	#define RTL8366RB_STP_STATE_DISABLED 0x0
114	#define RTL8366RB_STP_STATE_BLOCKING 0x1
115	#define RTL8366RB_STP_STATE_LEARNING 0x2
116	#define RTL8366RB_STP_STATE_FORWARDING 0x3
117	#define RTL8366RB_STP_MASK GENMASK(1, 0)
118	#define RTL8366RB_STP_STATE(port, state) \
119	((state) << ((port) * 2))
120	#define RTL8366RB_STP_STATE_MASK(port) \
121	RTL8366RB_STP_STATE((port), RTL8366RB_STP_MASK)
122
123	/* CPU port control reg */
124	#define RTL8366RB_CPU_CTRL_REG 0x0061
125	#define RTL8366RB_CPU_PORTS_MSK 0x00FF
126	/* Disables inserting custom tag length/type 0x8899 */
127	#define RTL8366RB_CPU_NO_TAG BIT(15)
128	#define RTL8366RB_CPU_TAG_SIZE 4
129
130	#define RTL8366RB_SMAR0 0x0070 /* bits 0..15 */
131	#define RTL8366RB_SMAR1 0x0071 /* bits 16..31 */
132	#define RTL8366RB_SMAR2 0x0072 /* bits 32..47 */
133
134	#define RTL8366RB_RESET_CTRL_REG 0x0100
135	#define RTL8366RB_CHIP_CTRL_RESET_HW BIT(0)
136	#define RTL8366RB_CHIP_CTRL_RESET_SW BIT(1)
137
138	#define RTL8366RB_CHIP_ID_REG 0x0509
139	#define RTL8366RB_CHIP_ID_8366 0x5937
140	#define RTL8366RB_CHIP_VERSION_CTRL_REG 0x050A
141	#define RTL8366RB_CHIP_VERSION_MASK 0xf
142
143	/* PHY registers control */
144	#define RTL8366RB_PHY_ACCESS_CTRL_REG 0x8000
145	#define RTL8366RB_PHY_CTRL_READ BIT(0)
146	#define RTL8366RB_PHY_CTRL_WRITE 0
147	#define RTL8366RB_PHY_ACCESS_BUSY_REG 0x8001
148	#define RTL8366RB_PHY_INT_BUSY BIT(0)
149	#define RTL8366RB_PHY_EXT_BUSY BIT(4)
150	#define RTL8366RB_PHY_ACCESS_DATA_REG 0x8002
151	#define RTL8366RB_PHY_EXT_CTRL_REG 0x8010
152	#define RTL8366RB_PHY_EXT_WRDATA_REG 0x8011
153	#define RTL8366RB_PHY_EXT_RDDATA_REG 0x8012
154
155	#define RTL8366RB_PHY_REG_MASK 0x1f
156	#define RTL8366RB_PHY_PAGE_OFFSET 5
157	#define RTL8366RB_PHY_PAGE_MASK (0xf << 5)
158	#define RTL8366RB_PHY_NO_OFFSET 9
159	#define RTL8366RB_PHY_NO_MASK (0x1f << 9)
160
161	/* VLAN Ingress Control Register 1, one bit per port.
162	* bit 0 .. 5 will make the switch drop ingress frames without
163	* VID such as untagged or priority-tagged frames for respective
164	* port.
165	* bit 6 .. 11 will make the switch drop ingress frames carrying
166	* a C-tag with VID != 0 for respective port.
167	*/
168	#define RTL8366RB_VLAN_INGRESS_CTRL1_REG 0x037E
169	#define RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port) (BIT((port)) | BIT((port) + 6))
170
171	/* VLAN Ingress Control Register 2, one bit per port.
172	* bit0 .. bit5 will make the switch drop all ingress frames with
173	* a VLAN classification that does not include the port is in its
174	* member set.
175	*/
176	#define RTL8366RB_VLAN_INGRESS_CTRL2_REG 0x037f
177
178	/* LED control registers */
179	#define RTL8366RB_LED_BLINKRATE_REG 0x0430
180	#define RTL8366RB_LED_BLINKRATE_MASK 0x0007
181	#define RTL8366RB_LED_BLINKRATE_28MS 0x0000
182	#define RTL8366RB_LED_BLINKRATE_56MS 0x0001
183	#define RTL8366RB_LED_BLINKRATE_84MS 0x0002
184	#define RTL8366RB_LED_BLINKRATE_111MS 0x0003
185	#define RTL8366RB_LED_BLINKRATE_222MS 0x0004
186	#define RTL8366RB_LED_BLINKRATE_446MS 0x0005
187
188	#define RTL8366RB_LED_CTRL_REG 0x0431
189	#define RTL8366RB_LED_OFF 0x0
190	#define RTL8366RB_LED_DUP_COL 0x1
191	#define RTL8366RB_LED_LINK_ACT 0x2
192	#define RTL8366RB_LED_SPD1000 0x3
193	#define RTL8366RB_LED_SPD100 0x4
194	#define RTL8366RB_LED_SPD10 0x5
195	#define RTL8366RB_LED_SPD1000_ACT 0x6
196	#define RTL8366RB_LED_SPD100_ACT 0x7
197	#define RTL8366RB_LED_SPD10_ACT 0x8
198	#define RTL8366RB_LED_SPD100_10_ACT 0x9
199	#define RTL8366RB_LED_FIBER 0xa
200	#define RTL8366RB_LED_AN_FAULT 0xb
201	#define RTL8366RB_LED_LINK_RX 0xc
202	#define RTL8366RB_LED_LINK_TX 0xd
203	#define RTL8366RB_LED_MASTER 0xe
204	#define RTL8366RB_LED_FORCE 0xf
205	#define RTL8366RB_LED_0_1_CTRL_REG 0x0432
206	#define RTL8366RB_LED_1_OFFSET 6
207	#define RTL8366RB_LED_2_3_CTRL_REG 0x0433
208	#define RTL8366RB_LED_3_OFFSET 6
209
210	#define RTL8366RB_MIB_COUNT 33
211	#define RTL8366RB_GLOBAL_MIB_COUNT 1
212	#define RTL8366RB_MIB_COUNTER_PORT_OFFSET 0x0050
213	#define RTL8366RB_MIB_COUNTER_BASE 0x1000
214	#define RTL8366RB_MIB_CTRL_REG 0x13F0
215	#define RTL8366RB_MIB_CTRL_USER_MASK 0x0FFC
216	#define RTL8366RB_MIB_CTRL_BUSY_MASK BIT(0)
217	#define RTL8366RB_MIB_CTRL_RESET_MASK BIT(1)
218	#define RTL8366RB_MIB_CTRL_PORT_RESET(_p) BIT(2 + (_p))
219	#define RTL8366RB_MIB_CTRL_GLOBAL_RESET BIT(11)
220
221	#define RTL8366RB_PORT_VLAN_CTRL_BASE 0x0063
222	#define RTL8366RB_PORT_VLAN_CTRL_REG(_p) \
223	(RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
224	#define RTL8366RB_PORT_VLAN_CTRL_MASK 0xf
225	#define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
226
227	#define RTL8366RB_VLAN_TABLE_READ_BASE 0x018C
228	#define RTL8366RB_VLAN_TABLE_WRITE_BASE 0x0185
229
230	#define RTL8366RB_TABLE_ACCESS_CTRL_REG 0x0180
231	#define RTL8366RB_TABLE_VLAN_READ_CTRL 0x0E01
232	#define RTL8366RB_TABLE_VLAN_WRITE_CTRL 0x0F01
233
234	#define RTL8366RB_VLAN_MC_BASE(_x) (0x0020 + (_x) * 3)
235
236	#define RTL8366RB_PORT_LINK_STATUS_BASE 0x0014
237	#define RTL8366RB_PORT_STATUS_SPEED_MASK 0x0003
238	#define RTL8366RB_PORT_STATUS_DUPLEX_MASK 0x0004
239	#define RTL8366RB_PORT_STATUS_LINK_MASK 0x0010
240	#define RTL8366RB_PORT_STATUS_TXPAUSE_MASK 0x0020
241	#define RTL8366RB_PORT_STATUS_RXPAUSE_MASK 0x0040
242	#define RTL8366RB_PORT_STATUS_AN_MASK 0x0080
243
244	#define RTL8366RB_NUM_VLANS 16
245	#define RTL8366RB_NUM_LEDGROUPS 4
246	#define RTL8366RB_NUM_VIDS 4096
247	#define RTL8366RB_PRIORITYMAX 7
248	#define RTL8366RB_NUM_FIDS 8
249	#define RTL8366RB_FIDMAX 7
250
251	#define RTL8366RB_PORT_1 BIT(0) /* In userspace port 0 */
252	#define RTL8366RB_PORT_2 BIT(1) /* In userspace port 1 */
253	#define RTL8366RB_PORT_3 BIT(2) /* In userspace port 2 */
254	#define RTL8366RB_PORT_4 BIT(3) /* In userspace port 3 */
255	#define RTL8366RB_PORT_5 BIT(4) /* In userspace port 4 */
256
257	#define RTL8366RB_PORT_CPU BIT(5) /* CPU port */
258
259	#define RTL8366RB_PORT_ALL (RTL8366RB_PORT_1 | \
260	RTL8366RB_PORT_2 | \
261	RTL8366RB_PORT_3 | \
262	RTL8366RB_PORT_4 | \
263	RTL8366RB_PORT_5 | \
264	RTL8366RB_PORT_CPU)
265
266	#define RTL8366RB_PORT_ALL_BUT_CPU (RTL8366RB_PORT_1 | \
267	RTL8366RB_PORT_2 | \
268	RTL8366RB_PORT_3 | \
269	RTL8366RB_PORT_4 | \
270	RTL8366RB_PORT_5)
271
272	#define RTL8366RB_PORT_ALL_EXTERNAL (RTL8366RB_PORT_1 | \
273	RTL8366RB_PORT_2 | \
274	RTL8366RB_PORT_3 | \
275	RTL8366RB_PORT_4)
276
277	#define RTL8366RB_PORT_ALL_INTERNAL RTL8366RB_PORT_CPU
278
279	/* First configuration word per member config, VID and prio */
280	#define RTL8366RB_VLAN_VID_MASK 0xfff
281	#define RTL8366RB_VLAN_PRIORITY_SHIFT 12
282	#define RTL8366RB_VLAN_PRIORITY_MASK 0x7
283	/* Second configuration word per member config, member and untagged */
284	#define RTL8366RB_VLAN_UNTAG_SHIFT 8
285	#define RTL8366RB_VLAN_UNTAG_MASK 0xff
286	#define RTL8366RB_VLAN_MEMBER_MASK 0xff
287	/* Third config word per member config, STAG currently unused */
288	#define RTL8366RB_VLAN_STAG_MBR_MASK 0xff
289	#define RTL8366RB_VLAN_STAG_MBR_SHIFT 8
290	#define RTL8366RB_VLAN_STAG_IDX_MASK 0x7
291	#define RTL8366RB_VLAN_STAG_IDX_SHIFT 5
292	#define RTL8366RB_VLAN_FID_MASK 0x7
293
294	/* Port ingress bandwidth control */
295	#define RTL8366RB_IB_BASE 0x0200
296	#define RTL8366RB_IB_REG(pnum) (RTL8366RB_IB_BASE + (pnum))
297	#define RTL8366RB_IB_BDTH_MASK 0x3fff
298	#define RTL8366RB_IB_PREIFG BIT(14)
299
300	/* Port egress bandwidth control */
301	#define RTL8366RB_EB_BASE 0x02d1
302	#define RTL8366RB_EB_REG(pnum) (RTL8366RB_EB_BASE + (pnum))
303	#define RTL8366RB_EB_BDTH_MASK 0x3fff
304	#define RTL8366RB_EB_PREIFG_REG 0x02f8
305	#define RTL8366RB_EB_PREIFG BIT(9)
306
307	#define RTL8366RB_BDTH_SW_MAX 1048512 /* 1048576? */
308	#define RTL8366RB_BDTH_UNIT 64
309	#define RTL8366RB_BDTH_REG_DEFAULT 16383
310
311	/* QOS */
312	#define RTL8366RB_QOS BIT(15)
313	/* Include/Exclude Preamble and IFG (20 bytes). 0:Exclude, 1:Include. */
314	#define RTL8366RB_QOS_DEFAULT_PREIFG 1
315
316	/* Interrupt handling */
317	#define RTL8366RB_INTERRUPT_CONTROL_REG 0x0440
318	#define RTL8366RB_INTERRUPT_POLARITY BIT(0)
319	#define RTL8366RB_P4_RGMII_LED BIT(2)
320	#define RTL8366RB_INTERRUPT_MASK_REG 0x0441
321	#define RTL8366RB_INTERRUPT_LINK_CHGALL GENMASK(11, 0)
322	#define RTL8366RB_INTERRUPT_ACLEXCEED BIT(8)
323	#define RTL8366RB_INTERRUPT_STORMEXCEED BIT(9)
324	#define RTL8366RB_INTERRUPT_P4_FIBER BIT(12)
325	#define RTL8366RB_INTERRUPT_P4_UTP BIT(13)
326	#define RTL8366RB_INTERRUPT_VALID (RTL8366RB_INTERRUPT_LINK_CHGALL | \
327	RTL8366RB_INTERRUPT_ACLEXCEED | \
328	RTL8366RB_INTERRUPT_STORMEXCEED | \
329	RTL8366RB_INTERRUPT_P4_FIBER | \
330	RTL8366RB_INTERRUPT_P4_UTP)
331	#define RTL8366RB_INTERRUPT_STATUS_REG 0x0442
332	#define RTL8366RB_NUM_INTERRUPT 14 /* 0..13 */
333
334	/* Port isolation registers */
335	#define RTL8366RB_PORT_ISO_BASE 0x0F08
336	#define RTL8366RB_PORT_ISO(pnum) (RTL8366RB_PORT_ISO_BASE + (pnum))
337	#define RTL8366RB_PORT_ISO_EN BIT(0)
338	#define RTL8366RB_PORT_ISO_PORTS_MASK GENMASK(7, 1)
339	#define RTL8366RB_PORT_ISO_PORTS(pmask) ((pmask) << 1)
340
341	/* bits 0..5 enable force when cleared */
342	#define RTL8366RB_MAC_FORCE_CTRL_REG 0x0F11
343
344	#define RTL8366RB_OAM_PARSER_REG 0x0F14
345	#define RTL8366RB_OAM_MULTIPLEXER_REG 0x0F15
346
347	#define RTL8366RB_GREEN_FEATURE_REG 0x0F51
348	#define RTL8366RB_GREEN_FEATURE_MSK 0x0007
349	#define RTL8366RB_GREEN_FEATURE_TX BIT(0)
350	#define RTL8366RB_GREEN_FEATURE_RX BIT(2)
351
352	/**
353	* struct rtl8366rb - RTL8366RB-specific data
354	* @max_mtu: per-port max MTU setting
355	* @pvid_enabled: if PVID is set for respective port
356	*/
357	struct rtl8366rb {
358	unsigned int max_mtu[RTL8366RB_NUM_PORTS];
359	bool pvid_enabled[RTL8366RB_NUM_PORTS];
360	};
361
362	static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {
363	{ 0, 0, 4, "IfInOctets" },
364	{ 0, 4, 4, "EtherStatsOctets" },
365	{ 0, 8, 2, "EtherStatsUnderSizePkts" },
366	{ 0, 10, 2, "EtherFragments" },
367	{ 0, 12, 2, "EtherStatsPkts64Octets" },
368	{ 0, 14, 2, "EtherStatsPkts65to127Octets" },
369	{ 0, 16, 2, "EtherStatsPkts128to255Octets" },
370	{ 0, 18, 2, "EtherStatsPkts256to511Octets" },
371	{ 0, 20, 2, "EtherStatsPkts512to1023Octets" },
372	{ 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
373	{ 0, 24, 2, "EtherOversizeStats" },
374	{ 0, 26, 2, "EtherStatsJabbers" },
375	{ 0, 28, 2, "IfInUcastPkts" },
376	{ 0, 30, 2, "EtherStatsMulticastPkts" },
377	{ 0, 32, 2, "EtherStatsBroadcastPkts" },
378	{ 0, 34, 2, "EtherStatsDropEvents" },
379	{ 0, 36, 2, "Dot3StatsFCSErrors" },
380	{ 0, 38, 2, "Dot3StatsSymbolErrors" },
381	{ 0, 40, 2, "Dot3InPauseFrames" },
382	{ 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
383	{ 0, 44, 4, "IfOutOctets" },
384	{ 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
385	{ 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
386	{ 0, 52, 2, "Dot3sDeferredTransmissions" },
387	{ 0, 54, 2, "Dot3StatsLateCollisions" },
388	{ 0, 56, 2, "EtherStatsCollisions" },
389	{ 0, 58, 2, "Dot3StatsExcessiveCollisions" },
390	{ 0, 60, 2, "Dot3OutPauseFrames" },
391	{ 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
392	{ 0, 64, 2, "Dot1dTpPortInDiscards" },
393	{ 0, 66, 2, "IfOutUcastPkts" },
394	{ 0, 68, 2, "IfOutMulticastPkts" },
395	{ 0, 70, 2, "IfOutBroadcastPkts" },
396	};
397
398	static int rtl8366rb_get_mib_counter(struct realtek_priv *priv,
399	int port,
400	struct rtl8366_mib_counter *mib,
401	u64 *mibvalue)
402	{
403	u32 addr, val;
404	int ret;
405	int i;
406
407	addr = RTL8366RB_MIB_COUNTER_BASE +
408	RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
409	mib->offset;
410
411	/* Writing access counter address first
412	* then ASIC will prepare 64bits counter wait for being retrived
413	*/
414	ret = regmap_write(map: priv->map, reg: addr, val: 0); /* Write whatever */
415	if (ret)
416	return ret;
417
418	/* Read MIB control register */
419	ret = regmap_read(map: priv->map, RTL8366RB_MIB_CTRL_REG, val: &val);
420	if (ret)
421	return -EIO;
422
423	if (val & RTL8366RB_MIB_CTRL_BUSY_MASK)
424	return -EBUSY;
425
426	if (val & RTL8366RB_MIB_CTRL_RESET_MASK)
427	return -EIO;
428
429	/* Read each individual MIB 16 bits at the time */
430	*mibvalue = 0;
431	for (i = mib->length; i > 0; i--) {
432	ret = regmap_read(map: priv->map, reg: addr + (i - 1), val: &val);
433	if (ret)
434	return ret;
435	*mibvalue = (*mibvalue << 16) | (val & 0xFFFF);
436	}
437	return 0;
438	}
439
440	static u32 rtl8366rb_get_irqmask(struct irq_data *d)
441	{
442	int line = irqd_to_hwirq(d);
443	u32 val;
444
445	/* For line interrupts we combine link down in bits
446	* 6..11 with link up in bits 0..5 into one interrupt.
447	*/
448	if (line < 12)
449	val = BIT(line) | BIT(line + 6);
450	else
451	val = BIT(line);
452	return val;
453	}
454
455	static void rtl8366rb_mask_irq(struct irq_data *d)
456	{
457	struct realtek_priv *priv = irq_data_get_irq_chip_data(d);
458	int ret;
459
460	ret = regmap_update_bits(map: priv->map, RTL8366RB_INTERRUPT_MASK_REG,
461	mask: rtl8366rb_get_irqmask(d), val: 0);
462	if (ret)
463	dev_err(priv->dev, "could not mask IRQ\n");
464	}
465
466	static void rtl8366rb_unmask_irq(struct irq_data *d)
467	{
468	struct realtek_priv *priv = irq_data_get_irq_chip_data(d);
469	int ret;
470
471	ret = regmap_update_bits(map: priv->map, RTL8366RB_INTERRUPT_MASK_REG,
472	mask: rtl8366rb_get_irqmask(d),
473	val: rtl8366rb_get_irqmask(d));
474	if (ret)
475	dev_err(priv->dev, "could not unmask IRQ\n");
476	}
477
478	static irqreturn_t rtl8366rb_irq(int irq, void *data)
479	{
480	struct realtek_priv *priv = data;
481	u32 stat;
482	int ret;
483
484	/* This clears the IRQ status register */
485	ret = regmap_read(map: priv->map, RTL8366RB_INTERRUPT_STATUS_REG,
486	val: &stat);
487	if (ret) {
488	dev_err(priv->dev, "can't read interrupt status\n");
489	return IRQ_NONE;
490	}
491	stat &= RTL8366RB_INTERRUPT_VALID;
492	if (!stat)
493	return IRQ_NONE;
494	while (stat) {
495	int line = __ffs(stat);
496	int child_irq;
497
498	stat &= ~BIT(line);
499	/* For line interrupts we combine link down in bits
500	* 6..11 with link up in bits 0..5 into one interrupt.
501	*/
502	if (line < 12 && line > 5)
503	line -= 5;
504	child_irq = irq_find_mapping(domain: priv->irqdomain, hwirq: line);
505	handle_nested_irq(irq: child_irq);
506	}
507	return IRQ_HANDLED;
508	}
509
510	static struct irq_chip rtl8366rb_irq_chip = {
511	.name = "RTL8366RB",
512	.irq_mask = rtl8366rb_mask_irq,
513	.irq_unmask = rtl8366rb_unmask_irq,
514	};
515
516	static int rtl8366rb_irq_map(struct irq_domain *domain, unsigned int irq,
517	irq_hw_number_t hwirq)
518	{
519	irq_set_chip_data(irq, data: domain->host_data);
520	irq_set_chip_and_handler(irq, chip: &rtl8366rb_irq_chip, handle: handle_simple_irq);
521	irq_set_nested_thread(irq, nest: 1);
522	irq_set_noprobe(irq);
523
524	return 0;
525	}
526
527	static void rtl8366rb_irq_unmap(struct irq_domain *d, unsigned int irq)
528	{
529	irq_set_nested_thread(irq, nest: 0);
530	irq_set_chip_and_handler(irq, NULL, NULL);
531	irq_set_chip_data(irq, NULL);
532	}
533
534	static const struct irq_domain_ops rtl8366rb_irqdomain_ops = {
535	.map = rtl8366rb_irq_map,
536	.unmap = rtl8366rb_irq_unmap,
537	.xlate = irq_domain_xlate_onecell,
538	};
539
540	static int rtl8366rb_setup_cascaded_irq(struct realtek_priv *priv)
541	{
542	struct device_node *intc;
543	unsigned long irq_trig;
544	int irq;
545	int ret;
546	u32 val;
547	int i;
548
549	intc = of_get_child_by_name(node: priv->dev->of_node, name: "interrupt-controller");
550	if (!intc) {
551	dev_err(priv->dev, "missing child interrupt-controller node\n");
552	return -EINVAL;
553	}
554	/* RB8366RB IRQs cascade off this one */
555	irq = of_irq_get(dev: intc, index: 0);
556	if (irq <= 0) {
557	dev_err(priv->dev, "failed to get parent IRQ\n");
558	ret = irq ? irq : -EINVAL;
559	goto out_put_node;
560	}
561
562	/* This clears the IRQ status register */
563	ret = regmap_read(map: priv->map, RTL8366RB_INTERRUPT_STATUS_REG,
564	val: &val);
565	if (ret) {
566	dev_err(priv->dev, "can't read interrupt status\n");
567	goto out_put_node;
568	}
569
570	/* Fetch IRQ edge information from the descriptor */
571	irq_trig = irqd_get_trigger_type(d: irq_get_irq_data(irq));
572	switch (irq_trig) {
573	case IRQF_TRIGGER_RISING:
574	case IRQF_TRIGGER_HIGH:
575	dev_info(priv->dev, "active high/rising IRQ\n");
576	val = 0;
577	break;
578	case IRQF_TRIGGER_FALLING:
579	case IRQF_TRIGGER_LOW:
580	dev_info(priv->dev, "active low/falling IRQ\n");
581	val = RTL8366RB_INTERRUPT_POLARITY;
582	break;
583	}
584	ret = regmap_update_bits(map: priv->map, RTL8366RB_INTERRUPT_CONTROL_REG,
585	RTL8366RB_INTERRUPT_POLARITY,
586	val);
587	if (ret) {
588	dev_err(priv->dev, "could not configure IRQ polarity\n");
589	goto out_put_node;
590	}
591
592	ret = devm_request_threaded_irq(dev: priv->dev, irq, NULL,
593	thread_fn: rtl8366rb_irq, IRQF_ONESHOT,
594	devname: "RTL8366RB", dev_id: priv);
595	if (ret) {
596	dev_err(priv->dev, "unable to request irq: %d\n", ret);
597	goto out_put_node;
598	}
599	priv->irqdomain = irq_domain_add_linear(of_node: intc,
600	RTL8366RB_NUM_INTERRUPT,
601	ops: &rtl8366rb_irqdomain_ops,
602	host_data: priv);
603	if (!priv->irqdomain) {
604	dev_err(priv->dev, "failed to create IRQ domain\n");
605	ret = -EINVAL;
606	goto out_put_node;
607	}
608	for (i = 0; i < priv->num_ports; i++)
609	irq_set_parent(irq: irq_create_mapping(host: priv->irqdomain, hwirq: i), parent_irq: irq);
610
611	out_put_node:
612	of_node_put(node: intc);
613	return ret;
614	}
615
616	static int rtl8366rb_set_addr(struct realtek_priv *priv)
617	{
618	u8 addr[ETH_ALEN];
619	u16 val;
620	int ret;
621
622	eth_random_addr(addr);
623
624	dev_info(priv->dev, "set MAC: %02X:%02X:%02X:%02X:%02X:%02X\n",
625	addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
626	val = addr[0] << 8 | addr[1];
627	ret = regmap_write(map: priv->map, RTL8366RB_SMAR0, val);
628	if (ret)
629	return ret;
630	val = addr[2] << 8 | addr[3];
631	ret = regmap_write(map: priv->map, RTL8366RB_SMAR1, val);
632	if (ret)
633	return ret;
634	val = addr[4] << 8 | addr[5];
635	ret = regmap_write(map: priv->map, RTL8366RB_SMAR2, val);
636	if (ret)
637	return ret;
638
639	return 0;
640	}
641
642	/* Found in a vendor driver */
643
644	/* Struct for handling the jam tables' entries */
645	struct rtl8366rb_jam_tbl_entry {
646	u16 reg;
647	u16 val;
648	};
649
650	/* For the "version 0" early silicon, appear in most source releases */
651	static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_0[] = {
652	{0x000B, 0x0001}, {0x03A6, 0x0100}, {0x03A7, 0x0001}, {0x02D1, 0x3FFF},
653	{0x02D2, 0x3FFF}, {0x02D3, 0x3FFF}, {0x02D4, 0x3FFF}, {0x02D5, 0x3FFF},
654	{0x02D6, 0x3FFF}, {0x02D7, 0x3FFF}, {0x02D8, 0x3FFF}, {0x022B, 0x0688},
655	{0x022C, 0x0FAC}, {0x03D0, 0x4688}, {0x03D1, 0x01F5}, {0x0000, 0x0830},
656	{0x02F9, 0x0200}, {0x02F7, 0x7FFF}, {0x02F8, 0x03FF}, {0x0080, 0x03E8},
657	{0x0081, 0x00CE}, {0x0082, 0x00DA}, {0x0083, 0x0230}, {0xBE0F, 0x2000},
658	{0x0231, 0x422A}, {0x0232, 0x422A}, {0x0233, 0x422A}, {0x0234, 0x422A},
659	{0x0235, 0x422A}, {0x0236, 0x422A}, {0x0237, 0x422A}, {0x0238, 0x422A},
660	{0x0239, 0x422A}, {0x023A, 0x422A}, {0x023B, 0x422A}, {0x023C, 0x422A},
661	{0x023D, 0x422A}, {0x023E, 0x422A}, {0x023F, 0x422A}, {0x0240, 0x422A},
662	{0x0241, 0x422A}, {0x0242, 0x422A}, {0x0243, 0x422A}, {0x0244, 0x422A},
663	{0x0245, 0x422A}, {0x0246, 0x422A}, {0x0247, 0x422A}, {0x0248, 0x422A},
664	{0x0249, 0x0146}, {0x024A, 0x0146}, {0x024B, 0x0146}, {0xBE03, 0xC961},
665	{0x024D, 0x0146}, {0x024E, 0x0146}, {0x024F, 0x0146}, {0x0250, 0x0146},
666	{0xBE64, 0x0226}, {0x0252, 0x0146}, {0x0253, 0x0146}, {0x024C, 0x0146},
667	{0x0251, 0x0146}, {0x0254, 0x0146}, {0xBE62, 0x3FD0}, {0x0084, 0x0320},
668	{0x0255, 0x0146}, {0x0256, 0x0146}, {0x0257, 0x0146}, {0x0258, 0x0146},
669	{0x0259, 0x0146}, {0x025A, 0x0146}, {0x025B, 0x0146}, {0x025C, 0x0146},
670	{0x025D, 0x0146}, {0x025E, 0x0146}, {0x025F, 0x0146}, {0x0260, 0x0146},
671	{0x0261, 0xA23F}, {0x0262, 0x0294}, {0x0263, 0xA23F}, {0x0264, 0x0294},
672	{0x0265, 0xA23F}, {0x0266, 0x0294}, {0x0267, 0xA23F}, {0x0268, 0x0294},
673	{0x0269, 0xA23F}, {0x026A, 0x0294}, {0x026B, 0xA23F}, {0x026C, 0x0294},
674	{0x026D, 0xA23F}, {0x026E, 0x0294}, {0x026F, 0xA23F}, {0x0270, 0x0294},
675	{0x02F5, 0x0048}, {0xBE09, 0x0E00}, {0xBE1E, 0x0FA0}, {0xBE14, 0x8448},
676	{0xBE15, 0x1007}, {0xBE4A, 0xA284}, {0xC454, 0x3F0B}, {0xC474, 0x3F0B},
677	{0xBE48, 0x3672}, {0xBE4B, 0x17A7}, {0xBE4C, 0x0B15}, {0xBE52, 0x0EDD},
678	{0xBE49, 0x8C00}, {0xBE5B, 0x785C}, {0xBE5C, 0x785C}, {0xBE5D, 0x785C},
679	{0xBE61, 0x368A}, {0xBE63, 0x9B84}, {0xC456, 0xCC13}, {0xC476, 0xCC13},
680	{0xBE65, 0x307D}, {0xBE6D, 0x0005}, {0xBE6E, 0xE120}, {0xBE2E, 0x7BAF},
681	};
682
683	/* This v1 init sequence is from Belkin F5D8235 U-Boot release */
684	static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_1[] = {
685	{0x0000, 0x0830}, {0x0001, 0x8000}, {0x0400, 0x8130}, {0xBE78, 0x3C3C},
686	{0x0431, 0x5432}, {0xBE37, 0x0CE4}, {0x02FA, 0xFFDF}, {0x02FB, 0xFFE0},
687	{0xC44C, 0x1585}, {0xC44C, 0x1185}, {0xC44C, 0x1585}, {0xC46C, 0x1585},
688	{0xC46C, 0x1185}, {0xC46C, 0x1585}, {0xC451, 0x2135}, {0xC471, 0x2135},
689	{0xBE10, 0x8140}, {0xBE15, 0x0007}, {0xBE6E, 0xE120}, {0xBE69, 0xD20F},
690	{0xBE6B, 0x0320}, {0xBE24, 0xB000}, {0xBE23, 0xFF51}, {0xBE22, 0xDF20},
691	{0xBE21, 0x0140}, {0xBE20, 0x00BB}, {0xBE24, 0xB800}, {0xBE24, 0x0000},
692	{0xBE24, 0x7000}, {0xBE23, 0xFF51}, {0xBE22, 0xDF60}, {0xBE21, 0x0140},
693	{0xBE20, 0x0077}, {0xBE24, 0x7800}, {0xBE24, 0x0000}, {0xBE2E, 0x7B7A},
694	{0xBE36, 0x0CE4}, {0x02F5, 0x0048}, {0xBE77, 0x2940}, {0x000A, 0x83E0},
695	{0xBE79, 0x3C3C}, {0xBE00, 0x1340},
696	};
697
698	/* This v2 init sequence is from Belkin F5D8235 U-Boot release */
699	static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_2[] = {
700	{0x0450, 0x0000}, {0x0400, 0x8130}, {0x000A, 0x83ED}, {0x0431, 0x5432},
701	{0xC44F, 0x6250}, {0xC46F, 0x6250}, {0xC456, 0x0C14}, {0xC476, 0x0C14},
702	{0xC44C, 0x1C85}, {0xC44C, 0x1885}, {0xC44C, 0x1C85}, {0xC46C, 0x1C85},
703	{0xC46C, 0x1885}, {0xC46C, 0x1C85}, {0xC44C, 0x0885}, {0xC44C, 0x0881},
704	{0xC44C, 0x0885}, {0xC46C, 0x0885}, {0xC46C, 0x0881}, {0xC46C, 0x0885},
705	{0xBE2E, 0x7BA7}, {0xBE36, 0x1000}, {0xBE37, 0x1000}, {0x8000, 0x0001},
706	{0xBE69, 0xD50F}, {0x8000, 0x0000}, {0xBE69, 0xD50F}, {0xBE6E, 0x0320},
707	{0xBE77, 0x2940}, {0xBE78, 0x3C3C}, {0xBE79, 0x3C3C}, {0xBE6E, 0xE120},
708	{0x8000, 0x0001}, {0xBE15, 0x1007}, {0x8000, 0x0000}, {0xBE15, 0x1007},
709	{0xBE14, 0x0448}, {0xBE1E, 0x00A0}, {0xBE10, 0x8160}, {0xBE10, 0x8140},
710	{0xBE00, 0x1340}, {0x0F51, 0x0010},
711	};
712
713	/* Appears in a DDWRT code dump */
714	static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_3[] = {
715	{0x0000, 0x0830}, {0x0400, 0x8130}, {0x000A, 0x83ED}, {0x0431, 0x5432},
716	{0x0F51, 0x0017}, {0x02F5, 0x0048}, {0x02FA, 0xFFDF}, {0x02FB, 0xFFE0},
717	{0xC456, 0x0C14}, {0xC476, 0x0C14}, {0xC454, 0x3F8B}, {0xC474, 0x3F8B},
718	{0xC450, 0x2071}, {0xC470, 0x2071}, {0xC451, 0x226B}, {0xC471, 0x226B},
719	{0xC452, 0xA293}, {0xC472, 0xA293}, {0xC44C, 0x1585}, {0xC44C, 0x1185},
720	{0xC44C, 0x1585}, {0xC46C, 0x1585}, {0xC46C, 0x1185}, {0xC46C, 0x1585},
721	{0xC44C, 0x0185}, {0xC44C, 0x0181}, {0xC44C, 0x0185}, {0xC46C, 0x0185},
722	{0xC46C, 0x0181}, {0xC46C, 0x0185}, {0xBE24, 0xB000}, {0xBE23, 0xFF51},
723	{0xBE22, 0xDF20}, {0xBE21, 0x0140}, {0xBE20, 0x00BB}, {0xBE24, 0xB800},
724	{0xBE24, 0x0000}, {0xBE24, 0x7000}, {0xBE23, 0xFF51}, {0xBE22, 0xDF60},
725	{0xBE21, 0x0140}, {0xBE20, 0x0077}, {0xBE24, 0x7800}, {0xBE24, 0x0000},
726	{0xBE2E, 0x7BA7}, {0xBE36, 0x1000}, {0xBE37, 0x1000}, {0x8000, 0x0001},
727	{0xBE69, 0xD50F}, {0x8000, 0x0000}, {0xBE69, 0xD50F}, {0xBE6B, 0x0320},
728	{0xBE77, 0x2800}, {0xBE78, 0x3C3C}, {0xBE79, 0x3C3C}, {0xBE6E, 0xE120},
729	{0x8000, 0x0001}, {0xBE10, 0x8140}, {0x8000, 0x0000}, {0xBE10, 0x8140},
730	{0xBE15, 0x1007}, {0xBE14, 0x0448}, {0xBE1E, 0x00A0}, {0xBE10, 0x8160},
731	{0xBE10, 0x8140}, {0xBE00, 0x1340}, {0x0450, 0x0000}, {0x0401, 0x0000},
732	};
733
734	/* Belkin F5D8235 v1, "belkin,f5d8235-v1" */
735	static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_f5d8235[] = {
736	{0x0242, 0x02BF}, {0x0245, 0x02BF}, {0x0248, 0x02BF}, {0x024B, 0x02BF},
737	{0x024E, 0x02BF}, {0x0251, 0x02BF}, {0x0254, 0x0A3F}, {0x0256, 0x0A3F},
738	{0x0258, 0x0A3F}, {0x025A, 0x0A3F}, {0x025C, 0x0A3F}, {0x025E, 0x0A3F},
739	{0x0263, 0x007C}, {0x0100, 0x0004}, {0xBE5B, 0x3500}, {0x800E, 0x200F},
740	{0xBE1D, 0x0F00}, {0x8001, 0x5011}, {0x800A, 0xA2F4}, {0x800B, 0x17A3},
741	{0xBE4B, 0x17A3}, {0xBE41, 0x5011}, {0xBE17, 0x2100}, {0x8000, 0x8304},
742	{0xBE40, 0x8304}, {0xBE4A, 0xA2F4}, {0x800C, 0xA8D5}, {0x8014, 0x5500},
743	{0x8015, 0x0004}, {0xBE4C, 0xA8D5}, {0xBE59, 0x0008}, {0xBE09, 0x0E00},
744	{0xBE36, 0x1036}, {0xBE37, 0x1036}, {0x800D, 0x00FF}, {0xBE4D, 0x00FF},
745	};
746
747	/* DGN3500, "netgear,dgn3500", "netgear,dgn3500b" */
748	static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_dgn3500[] = {
749	{0x0000, 0x0830}, {0x0400, 0x8130}, {0x000A, 0x83ED}, {0x0F51, 0x0017},
750	{0x02F5, 0x0048}, {0x02FA, 0xFFDF}, {0x02FB, 0xFFE0}, {0x0450, 0x0000},
751	{0x0401, 0x0000}, {0x0431, 0x0960},
752	};
753
754	/* This jam table activates "green ethernet", which means low power mode
755	* and is claimed to detect the cable length and not use more power than
756	* necessary, and the ports should enter power saving mode 10 seconds after
757	* a cable is disconnected. Seems to always be the same.
758	*/
759	static const struct rtl8366rb_jam_tbl_entry rtl8366rb_green_jam[] = {
760	{0xBE78, 0x323C}, {0xBE77, 0x5000}, {0xBE2E, 0x7BA7},
761	{0xBE59, 0x3459}, {0xBE5A, 0x745A}, {0xBE5B, 0x785C},
762	{0xBE5C, 0x785C}, {0xBE6E, 0xE120}, {0xBE79, 0x323C},
763	};
764
765	/* Function that jams the tables in the proper registers */
766	static int rtl8366rb_jam_table(const struct rtl8366rb_jam_tbl_entry *jam_table,
767	int jam_size, struct realtek_priv *priv,
768	bool write_dbg)
769	{
770	u32 val;
771	int ret;
772	int i;
773
774	for (i = 0; i < jam_size; i++) {
775	if ((jam_table[i].reg & 0xBE00) == 0xBE00) {
776	ret = regmap_read(map: priv->map,
777	RTL8366RB_PHY_ACCESS_BUSY_REG,
778	val: &val);
779	if (ret)
780	return ret;
781	if (!(val & RTL8366RB_PHY_INT_BUSY)) {
782	ret = regmap_write(map: priv->map,
783	RTL8366RB_PHY_ACCESS_CTRL_REG,
784	RTL8366RB_PHY_CTRL_WRITE);
785	if (ret)
786	return ret;
787	}
788	}
789	if (write_dbg)
790	dev_dbg(priv->dev, "jam %04x into register %04x\n",
791	jam_table[i].val,
792	jam_table[i].reg);
793	ret = regmap_write(map: priv->map,
794	reg: jam_table[i].reg,
795	val: jam_table[i].val);
796	if (ret)
797	return ret;
798	}
799	return 0;
800	}
801
802	static int rtl8366rb_setup(struct dsa_switch *ds)
803	{
804	struct realtek_priv *priv = ds->priv;
805	const struct rtl8366rb_jam_tbl_entry *jam_table;
806	struct rtl8366rb *rb;
807	u32 chip_ver = 0;
808	u32 chip_id = 0;
809	int jam_size;
810	u32 val;
811	int ret;
812	int i;
813
814	rb = priv->chip_data;
815
816	ret = regmap_read(map: priv->map, RTL8366RB_CHIP_ID_REG, val: &chip_id);
817	if (ret) {
818	dev_err(priv->dev, "unable to read chip id\n");
819	return ret;
820	}
821
822	switch (chip_id) {
823	case RTL8366RB_CHIP_ID_8366:
824	break;
825	default:
826	dev_err(priv->dev, "unknown chip id (%04x)\n", chip_id);
827	return -ENODEV;
828	}
829
830	ret = regmap_read(map: priv->map, RTL8366RB_CHIP_VERSION_CTRL_REG,
831	val: &chip_ver);
832	if (ret) {
833	dev_err(priv->dev, "unable to read chip version\n");
834	return ret;
835	}
836
837	dev_info(priv->dev, "RTL%04x ver %u chip found\n",
838	chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
839
840	/* Do the init dance using the right jam table */
841	switch (chip_ver) {
842	case 0:
843	jam_table = rtl8366rb_init_jam_ver_0;
844	jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_0);
845	break;
846	case 1:
847	jam_table = rtl8366rb_init_jam_ver_1;
848	jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_1);
849	break;
850	case 2:
851	jam_table = rtl8366rb_init_jam_ver_2;
852	jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_2);
853	break;
854	default:
855	jam_table = rtl8366rb_init_jam_ver_3;
856	jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_3);
857	break;
858	}
859
860	/* Special jam tables for special routers
861	* TODO: are these necessary? Maintainers, please test
862	* without them, using just the off-the-shelf tables.
863	*/
864	if (of_machine_is_compatible(compat: "belkin,f5d8235-v1")) {
865	jam_table = rtl8366rb_init_jam_f5d8235;
866	jam_size = ARRAY_SIZE(rtl8366rb_init_jam_f5d8235);
867	}
868	if (of_machine_is_compatible(compat: "netgear,dgn3500") ||
869	of_machine_is_compatible(compat: "netgear,dgn3500b")) {
870	jam_table = rtl8366rb_init_jam_dgn3500;
871	jam_size = ARRAY_SIZE(rtl8366rb_init_jam_dgn3500);
872	}
873
874	ret = rtl8366rb_jam_table(jam_table, jam_size, priv, write_dbg: true);
875	if (ret)
876	return ret;
877
878	/* Isolate all user ports so they can only send packets to itself and the CPU port */
879	for (i = 0; i < RTL8366RB_PORT_NUM_CPU; i++) {
880	ret = regmap_write(map: priv->map, RTL8366RB_PORT_ISO(i),
881	RTL8366RB_PORT_ISO_PORTS(BIT(RTL8366RB_PORT_NUM_CPU)) |
882	RTL8366RB_PORT_ISO_EN);
883	if (ret)
884	return ret;
885	}
886	/* CPU port can send packets to all ports */
887	ret = regmap_write(map: priv->map, RTL8366RB_PORT_ISO(RTL8366RB_PORT_NUM_CPU),
888	RTL8366RB_PORT_ISO_PORTS(dsa_user_ports(ds)) |
889	RTL8366RB_PORT_ISO_EN);
890	if (ret)
891	return ret;
892
893	/* Set up the "green ethernet" feature */
894	ret = rtl8366rb_jam_table(jam_table: rtl8366rb_green_jam,
895	ARRAY_SIZE(rtl8366rb_green_jam), priv, write_dbg: false);
896	if (ret)
897	return ret;
898
899	ret = regmap_write(map: priv->map,
900	RTL8366RB_GREEN_FEATURE_REG,
901	val: (chip_ver == 1) ? 0x0007 : 0x0003);
902	if (ret)
903	return ret;
904
905	/* Vendor driver sets 0x240 in registers 0xc and 0xd (undocumented) */
906	ret = regmap_write(map: priv->map, reg: 0x0c, val: 0x240);
907	if (ret)
908	return ret;
909	ret = regmap_write(map: priv->map, reg: 0x0d, val: 0x240);
910	if (ret)
911	return ret;
912
913	/* Set some random MAC address */
914	ret = rtl8366rb_set_addr(priv);
915	if (ret)
916	return ret;
917
918	/* Enable CPU port with custom DSA tag 8899.
919	*
920	* If you set RTL8366RB_CPU_NO_TAG (bit 15) in this register
921	* the custom tag is turned off.
922	*/
923	ret = regmap_update_bits(map: priv->map, RTL8366RB_CPU_CTRL_REG,
924	mask: 0xFFFF,
925	BIT(priv->cpu_port));
926	if (ret)
927	return ret;
928
929	/* Make sure we default-enable the fixed CPU port */
930	ret = regmap_update_bits(map: priv->map, RTL8366RB_PECR,
931	BIT(priv->cpu_port),
932	val: 0);
933	if (ret)
934	return ret;
935
936	/* Set default maximum packet length to 1536 bytes */
937	ret = regmap_update_bits(map: priv->map, RTL8366RB_SGCR,
938	RTL8366RB_SGCR_MAX_LENGTH_MASK,
939	RTL8366RB_SGCR_MAX_LENGTH_1536);
940	if (ret)
941	return ret;
942	for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
943	if (i == priv->cpu_port)
944	/* CPU port need to also accept the tag */
945	rb->max_mtu[i] = ETH_DATA_LEN + RTL8366RB_CPU_TAG_SIZE;
946	else
947	rb->max_mtu[i] = ETH_DATA_LEN;
948	}
949
950	/* Disable learning for all ports */
951	ret = regmap_write(map: priv->map, RTL8366RB_PORT_LEARNDIS_CTRL,
952	RTL8366RB_PORT_ALL);
953	if (ret)
954	return ret;
955
956	/* Enable auto ageing for all ports */
957	ret = regmap_write(map: priv->map, RTL8366RB_SECURITY_CTRL, val: 0);
958	if (ret)
959	return ret;
960
961	/* Port 4 setup: this enables Port 4, usually the WAN port,
962	* common PHY IO mode is apparently mode 0, and this is not what
963	* the port is initialized to. There is no explanation of the
964	* IO modes in the Realtek source code, if your WAN port is
965	* connected to something exotic such as fiber, then this might
966	* be worth experimenting with.
967	*/
968	ret = regmap_update_bits(map: priv->map, RTL8366RB_PMC0,
969	RTL8366RB_PMC0_P4_IOMODE_MASK,
970	val: 0 << RTL8366RB_PMC0_P4_IOMODE_SHIFT);
971	if (ret)
972	return ret;
973
974	/* Accept all packets by default, we enable filtering on-demand */
975	ret = regmap_write(map: priv->map, RTL8366RB_VLAN_INGRESS_CTRL1_REG,
976	val: 0);
977	if (ret)
978	return ret;
979	ret = regmap_write(map: priv->map, RTL8366RB_VLAN_INGRESS_CTRL2_REG,
980	val: 0);
981	if (ret)
982	return ret;
983
984	/* Don't drop packets whose DA has not been learned */
985	ret = regmap_update_bits(map: priv->map, RTL8366RB_SSCR2,
986	RTL8366RB_SSCR2_DROP_UNKNOWN_DA, val: 0);
987	if (ret)
988	return ret;
989
990	/* Set blinking, TODO: make this configurable */
991	ret = regmap_update_bits(map: priv->map, RTL8366RB_LED_BLINKRATE_REG,
992	RTL8366RB_LED_BLINKRATE_MASK,
993	RTL8366RB_LED_BLINKRATE_56MS);
994	if (ret)
995	return ret;
996
997	/* Set up LED activity:
998	* Each port has 4 LEDs, we configure all ports to the same
999	* behaviour (no individual config) but we can set up each
1000	* LED separately.
1001	*/
1002	if (priv->leds_disabled) {
1003	/* Turn everything off */
1004	regmap_update_bits(map: priv->map,
1005	RTL8366RB_LED_0_1_CTRL_REG,
1006	mask: 0x0FFF, val: 0);
1007	regmap_update_bits(map: priv->map,
1008	RTL8366RB_LED_2_3_CTRL_REG,
1009	mask: 0x0FFF, val: 0);
1010	regmap_update_bits(map: priv->map,
1011	RTL8366RB_INTERRUPT_CONTROL_REG,
1012	RTL8366RB_P4_RGMII_LED,
1013	val: 0);
1014	val = RTL8366RB_LED_OFF;
1015	} else {
1016	/* TODO: make this configurable per LED */
1017	val = RTL8366RB_LED_FORCE;
1018	}
1019	for (i = 0; i < 4; i++) {
1020	ret = regmap_update_bits(map: priv->map,
1021	RTL8366RB_LED_CTRL_REG,
1022	mask: 0xf << (i * 4),
1023	val: val << (i * 4));
1024	if (ret)
1025	return ret;
1026	}
1027
1028	ret = rtl8366_reset_vlan(priv);
1029	if (ret)
1030	return ret;
1031
1032	ret = rtl8366rb_setup_cascaded_irq(priv);
1033	if (ret)
1034	dev_info(priv->dev, "no interrupt support\n");
1035
1036	ret = rtl83xx_setup_user_mdio(ds);
1037	if (ret) {
1038	dev_err(priv->dev, "could not set up MDIO bus\n");
1039	return -ENODEV;
1040	}
1041
1042	return 0;
1043	}
1044
1045	static enum dsa_tag_protocol rtl8366_get_tag_protocol(struct dsa_switch *ds,
1046	int port,
1047	enum dsa_tag_protocol mp)
1048	{
1049	/* This switch uses the 4 byte protocol A Realtek DSA tag */
1050	return DSA_TAG_PROTO_RTL4_A;
1051	}
1052
1053	static void rtl8366rb_phylink_get_caps(struct dsa_switch *ds, int port,
1054	struct phylink_config *config)
1055	{
1056	unsigned long *interfaces = config->supported_interfaces;
1057	struct realtek_priv *priv = ds->priv;
1058
1059	if (port == priv->cpu_port) {
1060	__set_bit(PHY_INTERFACE_MODE_MII, interfaces);
1061	__set_bit(PHY_INTERFACE_MODE_GMII, interfaces);
1062	/* REVMII only supports 100M FD */
1063	__set_bit(PHY_INTERFACE_MODE_REVMII, interfaces);
1064	/* RGMII only supports 1G FD */
1065	phy_interface_set_rgmii(intf: interfaces);
1066
1067	config->mac_capabilities = MAC_1000 | MAC_100 |
1068	MAC_SYM_PAUSE;
1069	} else {
1070	/* RSGMII port, but we don't have that, and we don't
1071	* specify in DT, so phylib uses the default of GMII
1072	*/
1073	__set_bit(PHY_INTERFACE_MODE_GMII, interfaces);
1074	config->mac_capabilities = MAC_1000 | MAC_100 | MAC_10 |
1075	MAC_SYM_PAUSE | MAC_ASYM_PAUSE;
1076	}
1077	}
1078
1079	static void
1080	rtl8366rb_mac_link_up(struct dsa_switch *ds, int port, unsigned int mode,
1081	phy_interface_t interface, struct phy_device *phydev,
1082	int speed, int duplex, bool tx_pause, bool rx_pause)
1083	{
1084	struct realtek_priv *priv = ds->priv;
1085	unsigned int val;
1086	int ret;
1087
1088	/* Allow forcing the mode on the fixed CPU port, no autonegotiation.
1089	* We assume autonegotiation works on the PHY-facing ports.
1090	*/
1091	if (port != priv->cpu_port)
1092	return;
1093
1094	dev_dbg(priv->dev, "MAC link up on CPU port (%d)\n", port);
1095
1096	ret = regmap_update_bits(map: priv->map, RTL8366RB_MAC_FORCE_CTRL_REG,
1097	BIT(port), BIT(port));
1098	if (ret) {
1099	dev_err(priv->dev, "failed to force CPU port\n");
1100	return;
1101	}
1102
1103	/* Conjure port config */
1104	switch (speed) {
1105	case SPEED_10:
1106	val = RTL8366RB_PAACR_SPEED_10M;
1107	break;
1108	case SPEED_100:
1109	val = RTL8366RB_PAACR_SPEED_100M;
1110	break;
1111	case SPEED_1000:
1112	val = RTL8366RB_PAACR_SPEED_1000M;
1113	break;
1114	default:
1115	val = RTL8366RB_PAACR_SPEED_1000M;
1116	break;
1117	}
1118
1119	if (duplex == DUPLEX_FULL)
1120	val |= RTL8366RB_PAACR_FULL_DUPLEX;
1121
1122	if (tx_pause)
1123	val |= RTL8366RB_PAACR_TX_PAUSE;
1124
1125	if (rx_pause)
1126	val |= RTL8366RB_PAACR_RX_PAUSE;
1127
1128	val |= RTL8366RB_PAACR_LINK_UP;
1129
1130	ret = regmap_update_bits(map: priv->map, RTL8366RB_PAACR2,
1131	mask: 0xFF00U,
1132	val: val << 8);
1133	if (ret) {
1134	dev_err(priv->dev, "failed to set PAACR on CPU port\n");
1135	return;
1136	}
1137
1138	dev_dbg(priv->dev, "set PAACR to %04x\n", val);
1139
1140	/* Enable the CPU port */
1141	ret = regmap_update_bits(map: priv->map, RTL8366RB_PECR, BIT(port),
1142	val: 0);
1143	if (ret) {
1144	dev_err(priv->dev, "failed to enable the CPU port\n");
1145	return;
1146	}
1147	}
1148
1149	static void
1150	rtl8366rb_mac_link_down(struct dsa_switch *ds, int port, unsigned int mode,
1151	phy_interface_t interface)
1152	{
1153	struct realtek_priv *priv = ds->priv;
1154	int ret;
1155
1156	if (port != priv->cpu_port)
1157	return;
1158
1159	dev_dbg(priv->dev, "MAC link down on CPU port (%d)\n", port);
1160
1161	/* Disable the CPU port */
1162	ret = regmap_update_bits(map: priv->map, RTL8366RB_PECR, BIT(port),
1163	BIT(port));
1164	if (ret) {
1165	dev_err(priv->dev, "failed to disable the CPU port\n");
1166	return;
1167	}
1168	}
1169
1170	static void rb8366rb_set_port_led(struct realtek_priv *priv,
1171	int port, bool enable)
1172	{
1173	u16 val = enable ? 0x3f : 0;
1174	int ret;
1175
1176	if (priv->leds_disabled)
1177	return;
1178
1179	switch (port) {
1180	case 0:
1181	ret = regmap_update_bits(map: priv->map,
1182	RTL8366RB_LED_0_1_CTRL_REG,
1183	mask: 0x3F, val);
1184	break;
1185	case 1:
1186	ret = regmap_update_bits(map: priv->map,
1187	RTL8366RB_LED_0_1_CTRL_REG,
1188	mask: 0x3F << RTL8366RB_LED_1_OFFSET,
1189	val: val << RTL8366RB_LED_1_OFFSET);
1190	break;
1191	case 2:
1192	ret = regmap_update_bits(map: priv->map,
1193	RTL8366RB_LED_2_3_CTRL_REG,
1194	mask: 0x3F, val);
1195	break;
1196	case 3:
1197	ret = regmap_update_bits(map: priv->map,
1198	RTL8366RB_LED_2_3_CTRL_REG,
1199	mask: 0x3F << RTL8366RB_LED_3_OFFSET,
1200	val: val << RTL8366RB_LED_3_OFFSET);
1201	break;
1202	case 4:
1203	ret = regmap_update_bits(map: priv->map,
1204	RTL8366RB_INTERRUPT_CONTROL_REG,
1205	RTL8366RB_P4_RGMII_LED,
1206	val: enable ? RTL8366RB_P4_RGMII_LED : 0);
1207	break;
1208	default:
1209	dev_err(priv->dev, "no LED for port %d\n", port);
1210	return;
1211	}
1212	if (ret)
1213	dev_err(priv->dev, "error updating LED on port %d\n", port);
1214	}
1215
1216	static int
1217	rtl8366rb_port_enable(struct dsa_switch *ds, int port,
1218	struct phy_device *phy)
1219	{
1220	struct realtek_priv *priv = ds->priv;
1221	int ret;
1222
1223	dev_dbg(priv->dev, "enable port %d\n", port);
1224	ret = regmap_update_bits(map: priv->map, RTL8366RB_PECR, BIT(port),
1225	val: 0);
1226	if (ret)
1227	return ret;
1228
1229	rb8366rb_set_port_led(priv, port, enable: true);
1230	return 0;
1231	}
1232
1233	static void
1234	rtl8366rb_port_disable(struct dsa_switch *ds, int port)
1235	{
1236	struct realtek_priv *priv = ds->priv;
1237	int ret;
1238
1239	dev_dbg(priv->dev, "disable port %d\n", port);
1240	ret = regmap_update_bits(map: priv->map, RTL8366RB_PECR, BIT(port),
1241	BIT(port));
1242	if (ret)
1243	return;
1244
1245	rb8366rb_set_port_led(priv, port, enable: false);
1246	}
1247
1248	static int
1249	rtl8366rb_port_bridge_join(struct dsa_switch *ds, int port,
1250	struct dsa_bridge bridge,
1251	bool *tx_fwd_offload,
1252	struct netlink_ext_ack *extack)
1253	{
1254	struct realtek_priv *priv = ds->priv;
1255	unsigned int port_bitmap = 0;
1256	int ret, i;
1257
1258	/* Loop over all other ports than the current one */
1259	for (i = 0; i < RTL8366RB_PORT_NUM_CPU; i++) {
1260	/* Current port handled last */
1261	if (i == port)
1262	continue;
1263	/* Not on this bridge */
1264	if (!dsa_port_offloads_bridge(dp: dsa_to_port(ds, p: i), bridge: &bridge))
1265	continue;
1266	/* Join this port to each other port on the bridge */
1267	ret = regmap_update_bits(map: priv->map, RTL8366RB_PORT_ISO(i),
1268	RTL8366RB_PORT_ISO_PORTS(BIT(port)),
1269	RTL8366RB_PORT_ISO_PORTS(BIT(port)));
1270	if (ret)
1271	dev_err(priv->dev, "failed to join port %d\n", port);
1272
1273	port_bitmap |= BIT(i);
1274	}
1275
1276	/* Set the bits for the ports we can access */
1277	return regmap_update_bits(map: priv->map, RTL8366RB_PORT_ISO(port),
1278	RTL8366RB_PORT_ISO_PORTS(port_bitmap),
1279	RTL8366RB_PORT_ISO_PORTS(port_bitmap));
1280	}
1281
1282	static void
1283	rtl8366rb_port_bridge_leave(struct dsa_switch *ds, int port,
1284	struct dsa_bridge bridge)
1285	{
1286	struct realtek_priv *priv = ds->priv;
1287	unsigned int port_bitmap = 0;
1288	int ret, i;
1289
1290	/* Loop over all other ports than this one */
1291	for (i = 0; i < RTL8366RB_PORT_NUM_CPU; i++) {
1292	/* Current port handled last */
1293	if (i == port)
1294	continue;
1295	/* Not on this bridge */
1296	if (!dsa_port_offloads_bridge(dp: dsa_to_port(ds, p: i), bridge: &bridge))
1297	continue;
1298	/* Remove this port from any other port on the bridge */
1299	ret = regmap_update_bits(map: priv->map, RTL8366RB_PORT_ISO(i),
1300	RTL8366RB_PORT_ISO_PORTS(BIT(port)), val: 0);
1301	if (ret)
1302	dev_err(priv->dev, "failed to leave port %d\n", port);
1303
1304	port_bitmap |= BIT(i);
1305	}
1306
1307	/* Clear the bits for the ports we can not access, leave ourselves */
1308	regmap_update_bits(map: priv->map, RTL8366RB_PORT_ISO(port),
1309	RTL8366RB_PORT_ISO_PORTS(port_bitmap), val: 0);
1310	}
1311
1312	/**
1313	* rtl8366rb_drop_untagged() - make the switch drop untagged and C-tagged frames
1314	* @priv: SMI state container
1315	* @port: the port to drop untagged and C-tagged frames on
1316	* @drop: whether to drop or pass untagged and C-tagged frames
1317	*
1318	* Return: zero for success, a negative number on error.
1319	*/
1320	static int rtl8366rb_drop_untagged(struct realtek_priv *priv, int port, bool drop)
1321	{
1322	return regmap_update_bits(map: priv->map, RTL8366RB_VLAN_INGRESS_CTRL1_REG,
1323	RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port),
1324	val: drop ? RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port) : 0);
1325	}
1326
1327	static int rtl8366rb_vlan_filtering(struct dsa_switch *ds, int port,
1328	bool vlan_filtering,
1329	struct netlink_ext_ack *extack)
1330	{
1331	struct realtek_priv *priv = ds->priv;
1332	struct rtl8366rb *rb;
1333	int ret;
1334
1335	rb = priv->chip_data;
1336
1337	dev_dbg(priv->dev, "port %d: %s VLAN filtering\n", port,
1338	vlan_filtering ? "enable" : "disable");
1339
1340	/* If the port is not in the member set, the frame will be dropped */
1341	ret = regmap_update_bits(map: priv->map, RTL8366RB_VLAN_INGRESS_CTRL2_REG,
1342	BIT(port), val: vlan_filtering ? BIT(port) : 0);
1343	if (ret)
1344	return ret;
1345
1346	/* If VLAN filtering is enabled and PVID is also enabled, we must
1347	* not drop any untagged or C-tagged frames. If we turn off VLAN
1348	* filtering on a port, we need to accept any frames.
1349	*/
1350	if (vlan_filtering)
1351	ret = rtl8366rb_drop_untagged(priv, port, drop: !rb->pvid_enabled[port]);
1352	else
1353	ret = rtl8366rb_drop_untagged(priv, port, drop: false);
1354
1355	return ret;
1356	}
1357
1358	static int
1359	rtl8366rb_port_pre_bridge_flags(struct dsa_switch *ds, int port,
1360	struct switchdev_brport_flags flags,
1361	struct netlink_ext_ack *extack)
1362	{
1363	/* We support enabling/disabling learning */
1364	if (flags.mask & ~(BR_LEARNING))
1365	return -EINVAL;
1366
1367	return 0;
1368	}
1369
1370	static int
1371	rtl8366rb_port_bridge_flags(struct dsa_switch *ds, int port,
1372	struct switchdev_brport_flags flags,
1373	struct netlink_ext_ack *extack)
1374	{
1375	struct realtek_priv *priv = ds->priv;
1376	int ret;
1377
1378	if (flags.mask & BR_LEARNING) {
1379	ret = regmap_update_bits(map: priv->map, RTL8366RB_PORT_LEARNDIS_CTRL,
1380	BIT(port),
1381	val: (flags.val & BR_LEARNING) ? 0 : BIT(port));
1382	if (ret)
1383	return ret;
1384	}
1385
1386	return 0;
1387	}
1388
1389	static void
1390	rtl8366rb_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1391	{
1392	struct realtek_priv *priv = ds->priv;
1393	u32 val;
1394	int i;
1395
1396	switch (state) {
1397	case BR_STATE_DISABLED:
1398	val = RTL8366RB_STP_STATE_DISABLED;
1399	break;
1400	case BR_STATE_BLOCKING:
1401	case BR_STATE_LISTENING:
1402	val = RTL8366RB_STP_STATE_BLOCKING;
1403	break;
1404	case BR_STATE_LEARNING:
1405	val = RTL8366RB_STP_STATE_LEARNING;
1406	break;
1407	case BR_STATE_FORWARDING:
1408	val = RTL8366RB_STP_STATE_FORWARDING;
1409	break;
1410	default:
1411	dev_err(priv->dev, "unknown bridge state requested\n");
1412	return;
1413	}
1414
1415	/* Set the same status for the port on all the FIDs */
1416	for (i = 0; i < RTL8366RB_NUM_FIDS; i++) {
1417	regmap_update_bits(map: priv->map, RTL8366RB_STP_STATE_BASE + i,
1418	RTL8366RB_STP_STATE_MASK(port),
1419	RTL8366RB_STP_STATE(port, val));
1420	}
1421	}
1422
1423	static void
1424	rtl8366rb_port_fast_age(struct dsa_switch *ds, int port)
1425	{
1426	struct realtek_priv *priv = ds->priv;
1427
1428	/* This will age out any learned L2 entries */
1429	regmap_update_bits(map: priv->map, RTL8366RB_SECURITY_CTRL,
1430	BIT(port), BIT(port));
1431	/* Restore the normal state of things */
1432	regmap_update_bits(map: priv->map, RTL8366RB_SECURITY_CTRL,
1433	BIT(port), val: 0);
1434	}
1435
1436	static int rtl8366rb_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
1437	{
1438	struct realtek_priv *priv = ds->priv;
1439	struct rtl8366rb *rb;
1440	unsigned int max_mtu;
1441	u32 len;
1442	int i;
1443
1444	/* Cache the per-port MTU setting */
1445	rb = priv->chip_data;
1446	rb->max_mtu[port] = new_mtu;
1447
1448	/* Roof out the MTU for the entire switch to the greatest
1449	* common denominator: the biggest set for any one port will
1450	* be the biggest MTU for the switch.
1451	*/
1452	max_mtu = ETH_DATA_LEN;
1453	for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
1454	if (rb->max_mtu[i] > max_mtu)
1455	max_mtu = rb->max_mtu[i];
1456	}
1457
1458	/* Translate to layer 2 size.
1459	* Add ethernet and (possible) VLAN headers, and checksum to the size.
1460	* For ETH_DATA_LEN (1500 bytes) this will add up to 1522 bytes.
1461	*/
1462	max_mtu += VLAN_ETH_HLEN;
1463	max_mtu += ETH_FCS_LEN;
1464
1465	if (max_mtu <= 1522)
1466	len = RTL8366RB_SGCR_MAX_LENGTH_1522;
1467	else if (max_mtu > 1522 && max_mtu <= 1536)
1468	/* This will be the most common default if using VLAN and
1469	* CPU tagging on a port as both VLAN and CPU tag will
1470	* result in 1518 + 4 + 4 = 1526 bytes.
1471	*/
1472	len = RTL8366RB_SGCR_MAX_LENGTH_1536;
1473	else if (max_mtu > 1536 && max_mtu <= 1552)
1474	len = RTL8366RB_SGCR_MAX_LENGTH_1552;
1475	else
1476	len = RTL8366RB_SGCR_MAX_LENGTH_16000;
1477
1478	return regmap_update_bits(map: priv->map, RTL8366RB_SGCR,
1479	RTL8366RB_SGCR_MAX_LENGTH_MASK,
1480	val: len);
1481	}
1482
1483	static int rtl8366rb_max_mtu(struct dsa_switch *ds, int port)
1484	{
1485	/* The max MTU is 16000 bytes, so we subtract the ethernet
1486	* headers with VLAN and checksum and arrive at
1487	* 16000 - 18 - 4 = 15978. This does not include the CPU tag
1488	* since that is added to the requested MTU by the DSA framework.
1489	*/
1490	return 16000 - VLAN_ETH_HLEN - ETH_FCS_LEN;
1491	}
1492
1493	static int rtl8366rb_get_vlan_4k(struct realtek_priv *priv, u32 vid,
1494	struct rtl8366_vlan_4k *vlan4k)
1495	{
1496	u32 data[3];
1497	int ret;
1498	int i;
1499
1500	memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
1501
1502	if (vid >= RTL8366RB_NUM_VIDS)
1503	return -EINVAL;
1504
1505	/* write VID */
1506	ret = regmap_write(map: priv->map, RTL8366RB_VLAN_TABLE_WRITE_BASE,
1507	val: vid & RTL8366RB_VLAN_VID_MASK);
1508	if (ret)
1509	return ret;
1510
1511	/* write table access control word */
1512	ret = regmap_write(map: priv->map, RTL8366RB_TABLE_ACCESS_CTRL_REG,
1513	RTL8366RB_TABLE_VLAN_READ_CTRL);
1514	if (ret)
1515	return ret;
1516
1517	for (i = 0; i < 3; i++) {
1518	ret = regmap_read(map: priv->map,
1519	RTL8366RB_VLAN_TABLE_READ_BASE + i,
1520	val: &data[i]);
1521	if (ret)
1522	return ret;
1523	}
1524
1525	vlan4k->vid = vid;
1526	vlan4k->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
1527	RTL8366RB_VLAN_UNTAG_MASK;
1528	vlan4k->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
1529	vlan4k->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
1530
1531	return 0;
1532	}
1533
1534	static int rtl8366rb_set_vlan_4k(struct realtek_priv *priv,
1535	const struct rtl8366_vlan_4k *vlan4k)
1536	{
1537	u32 data[3];
1538	int ret;
1539	int i;
1540
1541	if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
1542	vlan4k->member > RTL8366RB_VLAN_MEMBER_MASK ||
1543	vlan4k->untag > RTL8366RB_VLAN_UNTAG_MASK ||
1544	vlan4k->fid > RTL8366RB_FIDMAX)
1545	return -EINVAL;
1546
1547	data[0] = vlan4k->vid & RTL8366RB_VLAN_VID_MASK;
1548	data[1] = (vlan4k->member & RTL8366RB_VLAN_MEMBER_MASK) |
1549	((vlan4k->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
1550	RTL8366RB_VLAN_UNTAG_SHIFT);
1551	data[2] = vlan4k->fid & RTL8366RB_VLAN_FID_MASK;
1552
1553	for (i = 0; i < 3; i++) {
1554	ret = regmap_write(map: priv->map,
1555	RTL8366RB_VLAN_TABLE_WRITE_BASE + i,
1556	val: data[i]);
1557	if (ret)
1558	return ret;
1559	}
1560
1561	/* write table access control word */
1562	ret = regmap_write(map: priv->map, RTL8366RB_TABLE_ACCESS_CTRL_REG,
1563	RTL8366RB_TABLE_VLAN_WRITE_CTRL);
1564
1565	return ret;
1566	}
1567
1568	static int rtl8366rb_get_vlan_mc(struct realtek_priv *priv, u32 index,
1569	struct rtl8366_vlan_mc *vlanmc)
1570	{
1571	u32 data[3];
1572	int ret;
1573	int i;
1574
1575	memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
1576
1577	if (index >= RTL8366RB_NUM_VLANS)
1578	return -EINVAL;
1579
1580	for (i = 0; i < 3; i++) {
1581	ret = regmap_read(map: priv->map,
1582	RTL8366RB_VLAN_MC_BASE(index) + i,
1583	val: &data[i]);
1584	if (ret)
1585	return ret;
1586	}
1587
1588	vlanmc->vid = data[0] & RTL8366RB_VLAN_VID_MASK;
1589	vlanmc->priority = (data[0] >> RTL8366RB_VLAN_PRIORITY_SHIFT) &
1590	RTL8366RB_VLAN_PRIORITY_MASK;
1591	vlanmc->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
1592	RTL8366RB_VLAN_UNTAG_MASK;
1593	vlanmc->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
1594	vlanmc->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
1595
1596	return 0;
1597	}
1598
1599	static int rtl8366rb_set_vlan_mc(struct realtek_priv *priv, u32 index,
1600	const struct rtl8366_vlan_mc *vlanmc)
1601	{
1602	u32 data[3];
1603	int ret;
1604	int i;
1605
1606	if (index >= RTL8366RB_NUM_VLANS ||
1607	vlanmc->vid >= RTL8366RB_NUM_VIDS ||
1608	vlanmc->priority > RTL8366RB_PRIORITYMAX ||
1609	vlanmc->member > RTL8366RB_VLAN_MEMBER_MASK ||
1610	vlanmc->untag > RTL8366RB_VLAN_UNTAG_MASK ||
1611	vlanmc->fid > RTL8366RB_FIDMAX)
1612	return -EINVAL;
1613
1614	data[0] = (vlanmc->vid & RTL8366RB_VLAN_VID_MASK) |
1615	((vlanmc->priority & RTL8366RB_VLAN_PRIORITY_MASK) <<
1616	RTL8366RB_VLAN_PRIORITY_SHIFT);
1617	data[1] = (vlanmc->member & RTL8366RB_VLAN_MEMBER_MASK) |
1618	((vlanmc->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
1619	RTL8366RB_VLAN_UNTAG_SHIFT);
1620	data[2] = vlanmc->fid & RTL8366RB_VLAN_FID_MASK;
1621
1622	for (i = 0; i < 3; i++) {
1623	ret = regmap_write(map: priv->map,
1624	RTL8366RB_VLAN_MC_BASE(index) + i,
1625	val: data[i]);
1626	if (ret)
1627	return ret;
1628	}
1629
1630	return 0;
1631	}
1632
1633	static int rtl8366rb_get_mc_index(struct realtek_priv *priv, int port, int *val)
1634	{
1635	u32 data;
1636	int ret;
1637
1638	if (port >= priv->num_ports)
1639	return -EINVAL;
1640
1641	ret = regmap_read(map: priv->map, RTL8366RB_PORT_VLAN_CTRL_REG(port),
1642	val: &data);
1643	if (ret)
1644	return ret;
1645
1646	*val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
1647	RTL8366RB_PORT_VLAN_CTRL_MASK;
1648
1649	return 0;
1650	}
1651
1652	static int rtl8366rb_set_mc_index(struct realtek_priv *priv, int port, int index)
1653	{
1654	struct dsa_switch *ds = &priv->ds;
1655	struct rtl8366rb *rb;
1656	bool pvid_enabled;
1657	int ret;
1658
1659	rb = priv->chip_data;
1660	pvid_enabled = !!index;
1661
1662	if (port >= priv->num_ports || index >= RTL8366RB_NUM_VLANS)
1663	return -EINVAL;
1664
1665	ret = regmap_update_bits(map: priv->map, RTL8366RB_PORT_VLAN_CTRL_REG(port),
1666	RTL8366RB_PORT_VLAN_CTRL_MASK <<
1667	RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
1668	val: (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
1669	RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
1670	if (ret)
1671	return ret;
1672
1673	rb->pvid_enabled[port] = pvid_enabled;
1674
1675	/* If VLAN filtering is enabled and PVID is also enabled, we must
1676	* not drop any untagged or C-tagged frames. Make sure to update the
1677	* filtering setting.
1678	*/
1679	if (dsa_port_is_vlan_filtering(dp: dsa_to_port(ds, p: port)))
1680	ret = rtl8366rb_drop_untagged(priv, port, drop: !pvid_enabled);
1681
1682	return ret;
1683	}
1684
1685	static bool rtl8366rb_is_vlan_valid(struct realtek_priv *priv, unsigned int vlan)
1686	{
1687	unsigned int max = RTL8366RB_NUM_VLANS - 1;
1688
1689	if (priv->vlan4k_enabled)
1690	max = RTL8366RB_NUM_VIDS - 1;
1691
1692	if (vlan > max)
1693	return false;
1694
1695	return true;
1696	}
1697
1698	static int rtl8366rb_enable_vlan(struct realtek_priv *priv, bool enable)
1699	{
1700	dev_dbg(priv->dev, "%s VLAN\n", enable ? "enable" : "disable");
1701	return regmap_update_bits(map: priv->map,
1702	RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN,
1703	val: enable ? RTL8366RB_SGCR_EN_VLAN : 0);
1704	}
1705
1706	static int rtl8366rb_enable_vlan4k(struct realtek_priv *priv, bool enable)
1707	{
1708	dev_dbg(priv->dev, "%s VLAN 4k\n", enable ? "enable" : "disable");
1709	return regmap_update_bits(map: priv->map, RTL8366RB_SGCR,
1710	RTL8366RB_SGCR_EN_VLAN_4KTB,
1711	val: enable ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0);
1712	}
1713
1714	static int rtl8366rb_phy_read(struct realtek_priv *priv, int phy, int regnum)
1715	{
1716	u32 val;
1717	u32 reg;
1718	int ret;
1719
1720	if (phy > RTL8366RB_PHY_NO_MAX)
1721	return -EINVAL;
1722
1723	rtl83xx_lock(ctx: priv);
1724
1725	ret = regmap_write(map: priv->map_nolock, RTL8366RB_PHY_ACCESS_CTRL_REG,
1726	RTL8366RB_PHY_CTRL_READ);
1727	if (ret)
1728	goto out;
1729
1730	reg = 0x8000 | (1 << (phy + RTL8366RB_PHY_NO_OFFSET)) | regnum;
1731
1732	ret = regmap_write(map: priv->map_nolock, reg, val: 0);
1733	if (ret) {
1734	dev_err(priv->dev,
1735	"failed to write PHY%d reg %04x @ %04x, ret %d\n",
1736	phy, regnum, reg, ret);
1737	goto out;
1738	}
1739
1740	ret = regmap_read(map: priv->map_nolock, RTL8366RB_PHY_ACCESS_DATA_REG,
1741	val: &val);
1742	if (ret)
1743	goto out;
1744
1745	ret = val;
1746
1747	dev_dbg(priv->dev, "read PHY%d register 0x%04x @ %08x, val <- %04x\n",
1748	phy, regnum, reg, val);
1749
1750	out:
1751	rtl83xx_unlock(ctx: priv);
1752
1753	return ret;
1754	}
1755
1756	static int rtl8366rb_phy_write(struct realtek_priv *priv, int phy, int regnum,
1757	u16 val)
1758	{
1759	u32 reg;
1760	int ret;
1761
1762	if (phy > RTL8366RB_PHY_NO_MAX)
1763	return -EINVAL;
1764
1765	rtl83xx_lock(ctx: priv);
1766
1767	ret = regmap_write(map: priv->map_nolock, RTL8366RB_PHY_ACCESS_CTRL_REG,
1768	RTL8366RB_PHY_CTRL_WRITE);
1769	if (ret)
1770	goto out;
1771
1772	reg = 0x8000 | (1 << (phy + RTL8366RB_PHY_NO_OFFSET)) | regnum;
1773
1774	dev_dbg(priv->dev, "write PHY%d register 0x%04x @ %04x, val -> %04x\n",
1775	phy, regnum, reg, val);
1776
1777	ret = regmap_write(map: priv->map_nolock, reg, val);
1778	if (ret)
1779	goto out;
1780
1781	out:
1782	rtl83xx_unlock(ctx: priv);
1783
1784	return ret;
1785	}
1786
1787	static int rtl8366rb_reset_chip(struct realtek_priv *priv)
1788	{
1789	int timeout = 10;
1790	u32 val;
1791	int ret;
1792
1793	priv->write_reg_noack(priv, RTL8366RB_RESET_CTRL_REG,
1794	RTL8366RB_CHIP_CTRL_RESET_HW);
1795	do {
1796	usleep_range(min: 20000, max: 25000);
1797	ret = regmap_read(map: priv->map, RTL8366RB_RESET_CTRL_REG, val: &val);
1798	if (ret)
1799	return ret;
1800
1801	if (!(val & RTL8366RB_CHIP_CTRL_RESET_HW))
1802	break;
1803	} while (--timeout);
1804
1805	if (!timeout) {
1806	dev_err(priv->dev, "timeout waiting for the switch to reset\n");
1807	return -EIO;
1808	}
1809
1810	return 0;
1811	}
1812
1813	static int rtl8366rb_detect(struct realtek_priv *priv)
1814	{
1815	struct device *dev = priv->dev;
1816	int ret;
1817	u32 val;
1818
1819	/* Detect device */
1820	ret = regmap_read(map: priv->map, reg: 0x5c, val: &val);
1821	if (ret) {
1822	dev_err(dev, "can't get chip ID (%d)\n", ret);
1823	return ret;
1824	}
1825
1826	switch (val) {
1827	case 0x6027:
1828	dev_info(dev, "found an RTL8366S switch\n");
1829	dev_err(dev, "this switch is not yet supported, submit patches!\n");
1830	return -ENODEV;
1831	case 0x5937:
1832	dev_info(dev, "found an RTL8366RB switch\n");
1833	priv->cpu_port = RTL8366RB_PORT_NUM_CPU;
1834	priv->num_ports = RTL8366RB_NUM_PORTS;
1835	priv->num_vlan_mc = RTL8366RB_NUM_VLANS;
1836	priv->mib_counters = rtl8366rb_mib_counters;
1837	priv->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters);
1838	break;
1839	default:
1840	dev_info(dev, "found an Unknown Realtek switch (id=0x%04x)\n",
1841	val);
1842	break;
1843	}
1844
1845	ret = rtl8366rb_reset_chip(priv);
1846	if (ret)
1847	return ret;
1848
1849	return 0;
1850	}
1851
1852	static const struct dsa_switch_ops rtl8366rb_switch_ops = {
1853	.get_tag_protocol = rtl8366_get_tag_protocol,
1854	.setup = rtl8366rb_setup,
1855	.phylink_get_caps = rtl8366rb_phylink_get_caps,
1856	.phylink_mac_link_up = rtl8366rb_mac_link_up,
1857	.phylink_mac_link_down = rtl8366rb_mac_link_down,
1858	.get_strings = rtl8366_get_strings,
1859	.get_ethtool_stats = rtl8366_get_ethtool_stats,
1860	.get_sset_count = rtl8366_get_sset_count,
1861	.port_bridge_join = rtl8366rb_port_bridge_join,
1862	.port_bridge_leave = rtl8366rb_port_bridge_leave,
1863	.port_vlan_filtering = rtl8366rb_vlan_filtering,
1864	.port_vlan_add = rtl8366_vlan_add,
1865	.port_vlan_del = rtl8366_vlan_del,
1866	.port_enable = rtl8366rb_port_enable,
1867	.port_disable = rtl8366rb_port_disable,
1868	.port_pre_bridge_flags = rtl8366rb_port_pre_bridge_flags,
1869	.port_bridge_flags = rtl8366rb_port_bridge_flags,
1870	.port_stp_state_set = rtl8366rb_port_stp_state_set,
1871	.port_fast_age = rtl8366rb_port_fast_age,
1872	.port_change_mtu = rtl8366rb_change_mtu,
1873	.port_max_mtu = rtl8366rb_max_mtu,
1874	};
1875
1876	static const struct realtek_ops rtl8366rb_ops = {
1877	.detect = rtl8366rb_detect,
1878	.get_vlan_mc = rtl8366rb_get_vlan_mc,
1879	.set_vlan_mc = rtl8366rb_set_vlan_mc,
1880	.get_vlan_4k = rtl8366rb_get_vlan_4k,
1881	.set_vlan_4k = rtl8366rb_set_vlan_4k,
1882	.get_mc_index = rtl8366rb_get_mc_index,
1883	.set_mc_index = rtl8366rb_set_mc_index,
1884	.get_mib_counter = rtl8366rb_get_mib_counter,
1885	.is_vlan_valid = rtl8366rb_is_vlan_valid,
1886	.enable_vlan = rtl8366rb_enable_vlan,
1887	.enable_vlan4k = rtl8366rb_enable_vlan4k,
1888	.phy_read = rtl8366rb_phy_read,
1889	.phy_write = rtl8366rb_phy_write,
1890	};
1891
1892	const struct realtek_variant rtl8366rb_variant = {
1893	.ds_ops = &rtl8366rb_switch_ops,
1894	.ops = &rtl8366rb_ops,
1895	.clk_delay = 10,
1896	.cmd_read = 0xa9,
1897	.cmd_write = 0xa8,
1898	.chip_data_sz = sizeof(struct rtl8366rb),
1899	};
1900
1901	static const struct of_device_id rtl8366rb_of_match[] = {
1902	{ .compatible = "realtek,rtl8366rb", .data = &rtl8366rb_variant, },
1903	{ /* sentinel */ },
1904	};
1905	MODULE_DEVICE_TABLE(of, rtl8366rb_of_match);
1906
1907	static struct platform_driver rtl8366rb_smi_driver = {
1908	.driver = {
1909	.name = "rtl8366rb-smi",
1910	.of_match_table = rtl8366rb_of_match,
1911	},
1912	.probe = realtek_smi_probe,
1913	.remove_new = realtek_smi_remove,
1914	.shutdown = realtek_smi_shutdown,
1915	};
1916
1917	static struct mdio_driver rtl8366rb_mdio_driver = {
1918	.mdiodrv.driver = {
1919	.name = "rtl8366rb-mdio",
1920	.of_match_table = rtl8366rb_of_match,
1921	},
1922	.probe = realtek_mdio_probe,
1923	.remove = realtek_mdio_remove,
1924	.shutdown = realtek_mdio_shutdown,
1925	};
1926
1927	static int rtl8366rb_init(void)
1928	{
1929	int ret;
1930
1931	ret = realtek_mdio_driver_register(drv: &rtl8366rb_mdio_driver);
1932	if (ret)
1933	return ret;
1934
1935	ret = realtek_smi_driver_register(drv: &rtl8366rb_smi_driver);
1936	if (ret) {
1937	realtek_mdio_driver_unregister(drv: &rtl8366rb_mdio_driver);
1938	return ret;
1939	}
1940
1941	return 0;
1942	}
1943	module_init(rtl8366rb_init);
1944
1945	static void __exit rtl8366rb_exit(void)
1946	{
1947	realtek_smi_driver_unregister(drv: &rtl8366rb_smi_driver);
1948	realtek_mdio_driver_unregister(drv: &rtl8366rb_mdio_driver);
1949	}
1950	module_exit(rtl8366rb_exit);
1951
1952	MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
1953	MODULE_DESCRIPTION("Driver for RTL8366RB ethernet switch");
1954	MODULE_LICENSE("GPL");
1955	MODULE_IMPORT_NS(REALTEK_DSA);
1956