1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH |
3 | * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com> |
4 | */ |
5 | #ifndef _SJA1105_H |
6 | #define _SJA1105_H |
7 | |
8 | #include <linux/ptp_clock_kernel.h> |
9 | #include <linux/timecounter.h> |
10 | #include <linux/dsa/sja1105.h> |
11 | #include <linux/dsa/8021q.h> |
12 | #include <net/dsa.h> |
13 | #include <linux/mutex.h> |
14 | #include "sja1105_static_config.h" |
15 | |
16 | #define SJA1105ET_FDB_BIN_SIZE 4 |
17 | /* The hardware value is in multiples of 10 ms. |
18 | * The passed parameter is in multiples of 1 ms. |
19 | */ |
20 | #define SJA1105_AGEING_TIME_MS(ms) ((ms) / 10) |
21 | #define SJA1105_NUM_L2_POLICERS SJA1110_MAX_L2_POLICING_COUNT |
22 | |
23 | /* Calculated assuming 1Gbps, where the clock has 125 MHz (8 ns period) |
24 | * To avoid floating point operations, we'll multiply the degrees by 10 |
25 | * to get a "phase" and get 1 decimal point precision. |
26 | */ |
27 | #define SJA1105_RGMII_DELAY_PS_TO_PHASE(ps) \ |
28 | (((ps) * 360) / 800) |
29 | #define SJA1105_RGMII_DELAY_PHASE_TO_PS(phase) \ |
30 | ((800 * (phase)) / 360) |
31 | #define SJA1105_RGMII_DELAY_PHASE_TO_HW(phase) \ |
32 | (((phase) - 738) / 9) |
33 | #define SJA1105_RGMII_DELAY_PS_TO_HW(ps) \ |
34 | SJA1105_RGMII_DELAY_PHASE_TO_HW(SJA1105_RGMII_DELAY_PS_TO_PHASE(ps)) |
35 | |
36 | /* Valid range in degrees is a value between 73.8 and 101.7 |
37 | * in 0.9 degree increments |
38 | */ |
39 | #define SJA1105_RGMII_DELAY_MIN_PS \ |
40 | SJA1105_RGMII_DELAY_PHASE_TO_PS(738) |
41 | #define SJA1105_RGMII_DELAY_MAX_PS \ |
42 | SJA1105_RGMII_DELAY_PHASE_TO_PS(1017) |
43 | |
44 | typedef enum { |
45 | SPI_READ = 0, |
46 | SPI_WRITE = 1, |
47 | } sja1105_spi_rw_mode_t; |
48 | |
49 | #include "sja1105_tas.h" |
50 | #include "sja1105_ptp.h" |
51 | |
52 | enum sja1105_stats_area { |
53 | MAC, |
54 | HL1, |
55 | HL2, |
56 | ETHER, |
57 | __MAX_SJA1105_STATS_AREA, |
58 | }; |
59 | |
60 | /* Keeps the different addresses between E/T and P/Q/R/S */ |
61 | struct sja1105_regs { |
62 | u64 device_id; |
63 | u64 prod_id; |
64 | u64 status; |
65 | u64 port_control; |
66 | u64 rgu; |
67 | u64 vl_status; |
68 | u64 config; |
69 | u64 rmii_pll1; |
70 | u64 ptppinst; |
71 | u64 ptppindur; |
72 | u64 ptp_control; |
73 | u64 ptpclkval; |
74 | u64 ptpclkrate; |
75 | u64 ptpclkcorp; |
76 | u64 ptpsyncts; |
77 | u64 ptpschtm; |
78 | u64 ptpegr_ts[SJA1105_MAX_NUM_PORTS]; |
79 | u64 pad_mii_tx[SJA1105_MAX_NUM_PORTS]; |
80 | u64 pad_mii_rx[SJA1105_MAX_NUM_PORTS]; |
81 | u64 pad_mii_id[SJA1105_MAX_NUM_PORTS]; |
82 | u64 cgu_idiv[SJA1105_MAX_NUM_PORTS]; |
83 | u64 mii_tx_clk[SJA1105_MAX_NUM_PORTS]; |
84 | u64 mii_rx_clk[SJA1105_MAX_NUM_PORTS]; |
85 | u64 mii_ext_tx_clk[SJA1105_MAX_NUM_PORTS]; |
86 | u64 mii_ext_rx_clk[SJA1105_MAX_NUM_PORTS]; |
87 | u64 rgmii_tx_clk[SJA1105_MAX_NUM_PORTS]; |
88 | u64 rmii_ref_clk[SJA1105_MAX_NUM_PORTS]; |
89 | u64 rmii_ext_tx_clk[SJA1105_MAX_NUM_PORTS]; |
90 | u64 stats[__MAX_SJA1105_STATS_AREA][SJA1105_MAX_NUM_PORTS]; |
91 | u64 mdio_100base_tx; |
92 | u64 mdio_100base_t1; |
93 | u64 pcs_base[SJA1105_MAX_NUM_PORTS]; |
94 | }; |
95 | |
96 | struct sja1105_mdio_private { |
97 | struct sja1105_private *priv; |
98 | }; |
99 | |
100 | enum { |
101 | SJA1105_SPEED_AUTO, |
102 | SJA1105_SPEED_10MBPS, |
103 | SJA1105_SPEED_100MBPS, |
104 | SJA1105_SPEED_1000MBPS, |
105 | SJA1105_SPEED_2500MBPS, |
106 | SJA1105_SPEED_MAX, |
107 | }; |
108 | |
109 | enum sja1105_internal_phy_t { |
110 | SJA1105_NO_PHY = 0, |
111 | SJA1105_PHY_BASE_TX, |
112 | SJA1105_PHY_BASE_T1, |
113 | }; |
114 | |
115 | struct sja1105_info { |
116 | u64 device_id; |
117 | /* Needed for distinction between P and R, and between Q and S |
118 | * (since the parts with/without SGMII share the same |
119 | * switch core and device_id) |
120 | */ |
121 | u64 part_no; |
122 | /* E/T and P/Q/R/S have partial timestamps of different sizes. |
123 | * They must be reconstructed on both families anyway to get the full |
124 | * 64-bit values back. |
125 | */ |
126 | int ptp_ts_bits; |
127 | /* Also SPI commands are of different sizes to retrieve |
128 | * the egress timestamps. |
129 | */ |
130 | int ptpegr_ts_bytes; |
131 | int num_cbs_shapers; |
132 | int max_frame_mem; |
133 | int num_ports; |
134 | bool multiple_cascade_ports; |
135 | /* Every {port, TXQ} has its own CBS shaper */ |
136 | bool fixed_cbs_mapping; |
137 | enum dsa_tag_protocol tag_proto; |
138 | const struct sja1105_dynamic_table_ops *dyn_ops; |
139 | const struct sja1105_table_ops *static_ops; |
140 | const struct sja1105_regs *regs; |
141 | bool can_limit_mcast_flood; |
142 | int (*reset_cmd)(struct dsa_switch *ds); |
143 | int (*setup_rgmii_delay)(const void *ctx, int port); |
144 | /* Prototypes from include/net/dsa.h */ |
145 | int (*fdb_add_cmd)(struct dsa_switch *ds, int port, |
146 | const unsigned char *addr, u16 vid); |
147 | int (*fdb_del_cmd)(struct dsa_switch *ds, int port, |
148 | const unsigned char *addr, u16 vid); |
149 | void (*ptp_cmd_packing)(u8 *buf, struct sja1105_ptp_cmd *cmd, |
150 | enum packing_op op); |
151 | bool (*rxtstamp)(struct dsa_switch *ds, int port, struct sk_buff *skb); |
152 | void (*txtstamp)(struct dsa_switch *ds, int port, struct sk_buff *skb); |
153 | int (*clocking_setup)(struct sja1105_private *priv); |
154 | int (*pcs_mdio_read_c45)(struct mii_bus *bus, int phy, int mmd, |
155 | int reg); |
156 | int (*pcs_mdio_write_c45)(struct mii_bus *bus, int phy, int mmd, |
157 | int reg, u16 val); |
158 | int (*disable_microcontroller)(struct sja1105_private *priv); |
159 | const char *name; |
160 | bool supports_mii[SJA1105_MAX_NUM_PORTS]; |
161 | bool supports_rmii[SJA1105_MAX_NUM_PORTS]; |
162 | bool supports_rgmii[SJA1105_MAX_NUM_PORTS]; |
163 | bool supports_sgmii[SJA1105_MAX_NUM_PORTS]; |
164 | bool supports_2500basex[SJA1105_MAX_NUM_PORTS]; |
165 | enum sja1105_internal_phy_t internal_phy[SJA1105_MAX_NUM_PORTS]; |
166 | const u64 port_speed[SJA1105_SPEED_MAX]; |
167 | }; |
168 | |
169 | enum sja1105_key_type { |
170 | SJA1105_KEY_BCAST, |
171 | SJA1105_KEY_TC, |
172 | SJA1105_KEY_VLAN_UNAWARE_VL, |
173 | SJA1105_KEY_VLAN_AWARE_VL, |
174 | }; |
175 | |
176 | struct sja1105_key { |
177 | enum sja1105_key_type type; |
178 | |
179 | union { |
180 | /* SJA1105_KEY_TC */ |
181 | struct { |
182 | int pcp; |
183 | } tc; |
184 | |
185 | /* SJA1105_KEY_VLAN_UNAWARE_VL */ |
186 | /* SJA1105_KEY_VLAN_AWARE_VL */ |
187 | struct { |
188 | u64 dmac; |
189 | u16 vid; |
190 | u16 pcp; |
191 | } vl; |
192 | }; |
193 | }; |
194 | |
195 | enum sja1105_rule_type { |
196 | SJA1105_RULE_BCAST_POLICER, |
197 | SJA1105_RULE_TC_POLICER, |
198 | SJA1105_RULE_VL, |
199 | }; |
200 | |
201 | enum sja1105_vl_type { |
202 | SJA1105_VL_NONCRITICAL, |
203 | SJA1105_VL_RATE_CONSTRAINED, |
204 | SJA1105_VL_TIME_TRIGGERED, |
205 | }; |
206 | |
207 | struct sja1105_rule { |
208 | struct list_head list; |
209 | unsigned long cookie; |
210 | unsigned long port_mask; |
211 | struct sja1105_key key; |
212 | enum sja1105_rule_type type; |
213 | |
214 | /* Action */ |
215 | union { |
216 | /* SJA1105_RULE_BCAST_POLICER */ |
217 | struct { |
218 | int sharindx; |
219 | } bcast_pol; |
220 | |
221 | /* SJA1105_RULE_TC_POLICER */ |
222 | struct { |
223 | int sharindx; |
224 | } tc_pol; |
225 | |
226 | /* SJA1105_RULE_VL */ |
227 | struct { |
228 | enum sja1105_vl_type type; |
229 | unsigned long destports; |
230 | int sharindx; |
231 | int maxlen; |
232 | int ipv; |
233 | u64 base_time; |
234 | u64 cycle_time; |
235 | int num_entries; |
236 | struct action_gate_entry *entries; |
237 | struct flow_stats stats; |
238 | } vl; |
239 | }; |
240 | }; |
241 | |
242 | struct sja1105_flow_block { |
243 | struct list_head rules; |
244 | bool l2_policer_used[SJA1105_NUM_L2_POLICERS]; |
245 | int num_virtual_links; |
246 | }; |
247 | |
248 | struct sja1105_private { |
249 | struct sja1105_static_config static_config; |
250 | int rgmii_rx_delay_ps[SJA1105_MAX_NUM_PORTS]; |
251 | int rgmii_tx_delay_ps[SJA1105_MAX_NUM_PORTS]; |
252 | phy_interface_t phy_mode[SJA1105_MAX_NUM_PORTS]; |
253 | bool fixed_link[SJA1105_MAX_NUM_PORTS]; |
254 | unsigned long ucast_egress_floods; |
255 | unsigned long bcast_egress_floods; |
256 | unsigned long hwts_tx_en; |
257 | unsigned long hwts_rx_en; |
258 | const struct sja1105_info *info; |
259 | size_t max_xfer_len; |
260 | struct spi_device *spidev; |
261 | struct dsa_switch *ds; |
262 | u16 bridge_pvid[SJA1105_MAX_NUM_PORTS]; |
263 | u16 tag_8021q_pvid[SJA1105_MAX_NUM_PORTS]; |
264 | struct sja1105_flow_block flow_block; |
265 | /* Serializes transmission of management frames so that |
266 | * the switch doesn't confuse them with one another. |
267 | */ |
268 | struct mutex mgmt_lock; |
269 | /* Serializes accesses to the FDB */ |
270 | struct mutex fdb_lock; |
271 | /* PTP two-step TX timestamp ID, and its serialization lock */ |
272 | spinlock_t ts_id_lock; |
273 | u8 ts_id; |
274 | /* Serializes access to the dynamic config interface */ |
275 | struct mutex dynamic_config_lock; |
276 | struct devlink_region **regions; |
277 | struct sja1105_cbs_entry *cbs; |
278 | struct mii_bus *mdio_base_t1; |
279 | struct mii_bus *mdio_base_tx; |
280 | struct mii_bus *mdio_pcs; |
281 | struct dw_xpcs *xpcs[SJA1105_MAX_NUM_PORTS]; |
282 | struct sja1105_ptp_data ptp_data; |
283 | struct sja1105_tas_data tas_data; |
284 | }; |
285 | |
286 | #include "sja1105_dynamic_config.h" |
287 | |
288 | struct sja1105_spi_message { |
289 | u64 access; |
290 | u64 read_count; |
291 | u64 address; |
292 | }; |
293 | |
294 | /* From sja1105_main.c */ |
295 | enum sja1105_reset_reason { |
296 | SJA1105_VLAN_FILTERING = 0, |
297 | SJA1105_AGEING_TIME, |
298 | SJA1105_SCHEDULING, |
299 | SJA1105_BEST_EFFORT_POLICING, |
300 | SJA1105_VIRTUAL_LINKS, |
301 | }; |
302 | |
303 | int sja1105_static_config_reload(struct sja1105_private *priv, |
304 | enum sja1105_reset_reason reason); |
305 | int sja1105_vlan_filtering(struct dsa_switch *ds, int port, bool enabled, |
306 | struct netlink_ext_ack *extack); |
307 | void sja1105_frame_memory_partitioning(struct sja1105_private *priv); |
308 | |
309 | /* From sja1105_mdio.c */ |
310 | int sja1105_mdiobus_register(struct dsa_switch *ds); |
311 | void sja1105_mdiobus_unregister(struct dsa_switch *ds); |
312 | int sja1105_pcs_mdio_read_c45(struct mii_bus *bus, int phy, int mmd, int reg); |
313 | int sja1105_pcs_mdio_write_c45(struct mii_bus *bus, int phy, int mmd, int reg, |
314 | u16 val); |
315 | int sja1110_pcs_mdio_read_c45(struct mii_bus *bus, int phy, int mmd, int reg); |
316 | int sja1110_pcs_mdio_write_c45(struct mii_bus *bus, int phy, int mmd, int reg, |
317 | u16 val); |
318 | |
319 | /* From sja1105_devlink.c */ |
320 | int sja1105_devlink_setup(struct dsa_switch *ds); |
321 | void sja1105_devlink_teardown(struct dsa_switch *ds); |
322 | int sja1105_devlink_info_get(struct dsa_switch *ds, |
323 | struct devlink_info_req *req, |
324 | struct netlink_ext_ack *extack); |
325 | |
326 | /* From sja1105_spi.c */ |
327 | int sja1105_xfer_buf(const struct sja1105_private *priv, |
328 | sja1105_spi_rw_mode_t rw, u64 reg_addr, |
329 | u8 *buf, size_t len); |
330 | int sja1105_xfer_u32(const struct sja1105_private *priv, |
331 | sja1105_spi_rw_mode_t rw, u64 reg_addr, u32 *value, |
332 | struct ptp_system_timestamp *ptp_sts); |
333 | int sja1105_xfer_u64(const struct sja1105_private *priv, |
334 | sja1105_spi_rw_mode_t rw, u64 reg_addr, u64 *value, |
335 | struct ptp_system_timestamp *ptp_sts); |
336 | int static_config_buf_prepare_for_upload(struct sja1105_private *priv, |
337 | void *config_buf, int buf_len); |
338 | int sja1105_static_config_upload(struct sja1105_private *priv); |
339 | int sja1105_inhibit_tx(const struct sja1105_private *priv, |
340 | unsigned long port_bitmap, bool tx_inhibited); |
341 | |
342 | extern const struct sja1105_info sja1105e_info; |
343 | extern const struct sja1105_info sja1105t_info; |
344 | extern const struct sja1105_info sja1105p_info; |
345 | extern const struct sja1105_info sja1105q_info; |
346 | extern const struct sja1105_info sja1105r_info; |
347 | extern const struct sja1105_info sja1105s_info; |
348 | extern const struct sja1105_info sja1110a_info; |
349 | extern const struct sja1105_info sja1110b_info; |
350 | extern const struct sja1105_info sja1110c_info; |
351 | extern const struct sja1105_info sja1110d_info; |
352 | |
353 | /* From sja1105_clocking.c */ |
354 | |
355 | typedef enum { |
356 | XMII_MAC = 0, |
357 | XMII_PHY = 1, |
358 | } sja1105_mii_role_t; |
359 | |
360 | typedef enum { |
361 | XMII_MODE_MII = 0, |
362 | XMII_MODE_RMII = 1, |
363 | XMII_MODE_RGMII = 2, |
364 | XMII_MODE_SGMII = 3, |
365 | } sja1105_phy_interface_t; |
366 | |
367 | int sja1105pqrs_setup_rgmii_delay(const void *ctx, int port); |
368 | int sja1110_setup_rgmii_delay(const void *ctx, int port); |
369 | int sja1105_clocking_setup_port(struct sja1105_private *priv, int port); |
370 | int sja1105_clocking_setup(struct sja1105_private *priv); |
371 | int sja1110_disable_microcontroller(struct sja1105_private *priv); |
372 | |
373 | /* From sja1105_ethtool.c */ |
374 | void sja1105_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data); |
375 | void sja1105_get_strings(struct dsa_switch *ds, int port, |
376 | u32 stringset, u8 *data); |
377 | int sja1105_get_sset_count(struct dsa_switch *ds, int port, int sset); |
378 | |
379 | /* From sja1105_dynamic_config.c */ |
380 | int sja1105_dynamic_config_read(struct sja1105_private *priv, |
381 | enum sja1105_blk_idx blk_idx, |
382 | int index, void *entry); |
383 | int sja1105_dynamic_config_write(struct sja1105_private *priv, |
384 | enum sja1105_blk_idx blk_idx, |
385 | int index, void *entry, bool keep); |
386 | |
387 | enum sja1105_iotag { |
388 | SJA1105_C_TAG = 0, /* Inner VLAN header */ |
389 | SJA1105_S_TAG = 1, /* Outer VLAN header */ |
390 | }; |
391 | |
392 | enum sja1110_vlan_type { |
393 | SJA1110_VLAN_INVALID = 0, |
394 | SJA1110_VLAN_C_TAG = 1, /* Single inner VLAN tag */ |
395 | SJA1110_VLAN_S_TAG = 2, /* Single outer VLAN tag */ |
396 | SJA1110_VLAN_D_TAG = 3, /* Double tagged, use outer tag for lookup */ |
397 | }; |
398 | |
399 | enum sja1110_shaper_type { |
400 | SJA1110_LEAKY_BUCKET_SHAPER = 0, |
401 | SJA1110_CBS_SHAPER = 1, |
402 | }; |
403 | |
404 | u8 sja1105et_fdb_hash(struct sja1105_private *priv, const u8 *addr, u16 vid); |
405 | int sja1105et_fdb_add(struct dsa_switch *ds, int port, |
406 | const unsigned char *addr, u16 vid); |
407 | int sja1105et_fdb_del(struct dsa_switch *ds, int port, |
408 | const unsigned char *addr, u16 vid); |
409 | int sja1105pqrs_fdb_add(struct dsa_switch *ds, int port, |
410 | const unsigned char *addr, u16 vid); |
411 | int sja1105pqrs_fdb_del(struct dsa_switch *ds, int port, |
412 | const unsigned char *addr, u16 vid); |
413 | |
414 | /* From sja1105_flower.c */ |
415 | int sja1105_cls_flower_del(struct dsa_switch *ds, int port, |
416 | struct flow_cls_offload *cls, bool ingress); |
417 | int sja1105_cls_flower_add(struct dsa_switch *ds, int port, |
418 | struct flow_cls_offload *cls, bool ingress); |
419 | int sja1105_cls_flower_stats(struct dsa_switch *ds, int port, |
420 | struct flow_cls_offload *cls, bool ingress); |
421 | void sja1105_flower_setup(struct dsa_switch *ds); |
422 | void sja1105_flower_teardown(struct dsa_switch *ds); |
423 | struct sja1105_rule *sja1105_rule_find(struct sja1105_private *priv, |
424 | unsigned long cookie); |
425 | |
426 | #endif |
427 | |