1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* Copyright (C) 2022, Intel Corporation. */ |
3 | |
4 | #ifndef _ICE_DPLL_H_ |
5 | #define _ICE_DPLL_H_ |
6 | |
7 | #include "ice.h" |
8 | |
9 | #define ICE_DPLL_PRIO_MAX 0xF |
10 | #define ICE_DPLL_RCLK_NUM_MAX 4 |
11 | |
12 | /** ice_dpll_pin - store info about pins |
13 | * @pin: dpll pin structure |
14 | * @pf: pointer to pf, which has registered the dpll_pin |
15 | * @idx: ice pin private idx |
16 | * @num_parents: hols number of parent pins |
17 | * @parent_idx: hold indexes of parent pins |
18 | * @flags: pin flags returned from HW |
19 | * @state: state of a pin |
20 | * @prop: pin properties |
21 | * @freq: current frequency of a pin |
22 | * @phase_adjust: current phase adjust value |
23 | */ |
24 | struct ice_dpll_pin { |
25 | struct dpll_pin *pin; |
26 | struct ice_pf *pf; |
27 | u8 idx; |
28 | u8 num_parents; |
29 | u8 parent_idx[ICE_DPLL_RCLK_NUM_MAX]; |
30 | u8 flags[ICE_DPLL_RCLK_NUM_MAX]; |
31 | u8 state[ICE_DPLL_RCLK_NUM_MAX]; |
32 | struct dpll_pin_properties prop; |
33 | u32 freq; |
34 | s32 phase_adjust; |
35 | }; |
36 | |
37 | /** ice_dpll - store info required for DPLL control |
38 | * @dpll: pointer to dpll dev |
39 | * @pf: pointer to pf, which has registered the dpll_device |
40 | * @dpll_idx: index of dpll on the NIC |
41 | * @input_idx: currently selected input index |
42 | * @prev_input_idx: previously selected input index |
43 | * @ref_state: state of dpll reference signals |
44 | * @eec_mode: eec_mode dpll is configured for |
45 | * @phase_offset: phase offset of active pin vs dpll signal |
46 | * @prev_phase_offset: previous phase offset of active pin vs dpll signal |
47 | * @input_prio: priorities of each input |
48 | * @dpll_state: current dpll sync state |
49 | * @prev_dpll_state: last dpll sync state |
50 | * @active_input: pointer to active input pin |
51 | * @prev_input: pointer to previous active input pin |
52 | */ |
53 | struct ice_dpll { |
54 | struct dpll_device *dpll; |
55 | struct ice_pf *pf; |
56 | u8 dpll_idx; |
57 | u8 input_idx; |
58 | u8 prev_input_idx; |
59 | u8 ref_state; |
60 | u8 eec_mode; |
61 | s64 phase_offset; |
62 | s64 prev_phase_offset; |
63 | u8 *input_prio; |
64 | enum dpll_lock_status dpll_state; |
65 | enum dpll_lock_status prev_dpll_state; |
66 | enum dpll_mode mode; |
67 | struct dpll_pin *active_input; |
68 | struct dpll_pin *prev_input; |
69 | }; |
70 | |
71 | /** ice_dplls - store info required for CCU (clock controlling unit) |
72 | * @kworker: periodic worker |
73 | * @work: periodic work |
74 | * @lock: locks access to configuration of a dpll |
75 | * @eec: pointer to EEC dpll dev |
76 | * @pps: pointer to PPS dpll dev |
77 | * @inputs: input pins pointer |
78 | * @outputs: output pins pointer |
79 | * @rclk: recovered pins pointer |
80 | * @num_inputs: number of input pins available on dpll |
81 | * @num_outputs: number of output pins available on dpll |
82 | * @cgu_state_acq_err_num: number of errors returned during periodic work |
83 | * @base_rclk_idx: idx of first pin used for clock revocery pins |
84 | * @clock_id: clock_id of dplls |
85 | * @input_phase_adj_max: max phase adjust value for an input pins |
86 | * @output_phase_adj_max: max phase adjust value for an output pins |
87 | */ |
88 | struct ice_dplls { |
89 | struct kthread_worker *kworker; |
90 | struct kthread_delayed_work work; |
91 | struct mutex lock; |
92 | struct ice_dpll eec; |
93 | struct ice_dpll pps; |
94 | struct ice_dpll_pin *inputs; |
95 | struct ice_dpll_pin *outputs; |
96 | struct ice_dpll_pin rclk; |
97 | u8 num_inputs; |
98 | u8 num_outputs; |
99 | int cgu_state_acq_err_num; |
100 | u8 base_rclk_idx; |
101 | u64 clock_id; |
102 | s32 input_phase_adj_max; |
103 | s32 output_phase_adj_max; |
104 | }; |
105 | |
106 | #if IS_ENABLED(CONFIG_PTP_1588_CLOCK) |
107 | void ice_dpll_init(struct ice_pf *pf); |
108 | void ice_dpll_deinit(struct ice_pf *pf); |
109 | #else |
110 | static inline void ice_dpll_init(struct ice_pf *pf) { } |
111 | static inline void ice_dpll_deinit(struct ice_pf *pf) { } |
112 | #endif |
113 | |
114 | #endif |
115 | |