1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Header Parser definitions for Marvell PPv2 Network Controller
4 *
5 * Copyright (C) 2014 Marvell
6 *
7 * Marcin Wojtas <mw@semihalf.com>
8 */
9#ifndef _MVPP2_PRS_H_
10#define _MVPP2_PRS_H_
11
12#include <linux/kernel.h>
13#include <linux/netdevice.h>
14#include <linux/platform_device.h>
15
16#include "mvpp2.h"
17
18/* Parser constants */
19#define MVPP2_PRS_TCAM_SRAM_SIZE 256
20#define MVPP2_PRS_TCAM_WORDS 6
21#define MVPP2_PRS_SRAM_WORDS 4
22#define MVPP2_PRS_FLOW_ID_SIZE 64
23#define MVPP2_PRS_FLOW_ID_MASK 0x3f
24#define MVPP2_PRS_TCAM_ENTRY_INVALID 1
25#define MVPP2_PRS_TCAM_DSA_TAGGED_BIT BIT(5)
26#define MVPP2_PRS_IPV4_HEAD 0x40
27#define MVPP2_PRS_IPV4_HEAD_MASK 0xf0
28#define MVPP2_PRS_IPV4_MC 0xe0
29#define MVPP2_PRS_IPV4_MC_MASK 0xf0
30#define MVPP2_PRS_IPV4_BC_MASK 0xff
31#define MVPP2_PRS_IPV4_IHL_MIN 0x5
32#define MVPP2_PRS_IPV4_IHL_MAX 0xf
33#define MVPP2_PRS_IPV4_IHL_MASK 0xf
34#define MVPP2_PRS_IPV6_MC 0xff
35#define MVPP2_PRS_IPV6_MC_MASK 0xff
36#define MVPP2_PRS_IPV6_HOP_MASK 0xff
37#define MVPP2_PRS_TCAM_PROTO_MASK 0xff
38#define MVPP2_PRS_TCAM_PROTO_MASK_L 0x3f
39#define MVPP2_PRS_DBL_VLANS_MAX 100
40#define MVPP2_PRS_CAST_MASK BIT(0)
41#define MVPP2_PRS_MCAST_VAL BIT(0)
42#define MVPP2_PRS_UCAST_VAL 0x0
43
44/* Tcam structure:
45 * - lookup ID - 4 bits
46 * - port ID - 1 byte
47 * - additional information - 1 byte
48 * - header data - 8 bytes
49 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(5)->(0).
50 */
51#define MVPP2_PRS_AI_BITS 8
52#define MVPP2_PRS_AI_MASK 0xff
53#define MVPP2_PRS_PORT_MASK 0xff
54#define MVPP2_PRS_LU_MASK 0xf
55
56/* TCAM entries in registers are accessed using 16 data bits + 16 enable bits */
57#define MVPP2_PRS_BYTE_TO_WORD(byte) ((byte) / 2)
58#define MVPP2_PRS_BYTE_IN_WORD(byte) ((byte) % 2)
59
60#define MVPP2_PRS_TCAM_EN(data) ((data) << 16)
61#define MVPP2_PRS_TCAM_AI_WORD 4
62#define MVPP2_PRS_TCAM_AI(ai) (ai)
63#define MVPP2_PRS_TCAM_AI_EN(ai) MVPP2_PRS_TCAM_EN(MVPP2_PRS_TCAM_AI(ai))
64#define MVPP2_PRS_TCAM_PORT_WORD 4
65#define MVPP2_PRS_TCAM_PORT(p) ((p) << 8)
66#define MVPP2_PRS_TCAM_PORT_EN(p) MVPP2_PRS_TCAM_EN(MVPP2_PRS_TCAM_PORT(p))
67#define MVPP2_PRS_TCAM_LU_WORD 5
68#define MVPP2_PRS_TCAM_LU(lu) (lu)
69#define MVPP2_PRS_TCAM_LU_EN(lu) MVPP2_PRS_TCAM_EN(MVPP2_PRS_TCAM_LU(lu))
70#define MVPP2_PRS_TCAM_INV_WORD 5
71
72#define MVPP2_PRS_VID_TCAM_BYTE 2
73
74/* TCAM range for unicast and multicast filtering. We have 25 entries per port,
75 * with 4 dedicated to UC filtering and the rest to multicast filtering.
76 * Additionnally we reserve one entry for the broadcast address, and one for
77 * each port's own address.
78 */
79#define MVPP2_PRS_MAC_UC_MC_FILT_MAX 25
80#define MVPP2_PRS_MAC_RANGE_SIZE 80
81
82/* Number of entries per port dedicated to UC and MC filtering */
83#define MVPP2_PRS_MAC_UC_FILT_MAX 4
84#define MVPP2_PRS_MAC_MC_FILT_MAX (MVPP2_PRS_MAC_UC_MC_FILT_MAX - \
85 MVPP2_PRS_MAC_UC_FILT_MAX)
86
87/* There is a TCAM range reserved for VLAN filtering entries, range size is 33
88 * 10 VLAN ID filter entries per port
89 * 1 default VLAN filter entry per port
90 * It is assumed that there are 3 ports for filter, not including loopback port
91 */
92#define MVPP2_PRS_VLAN_FILT_MAX 11
93#define MVPP2_PRS_VLAN_FILT_RANGE_SIZE 33
94
95#define MVPP2_PRS_VLAN_FILT_MAX_ENTRY (MVPP2_PRS_VLAN_FILT_MAX - 2)
96#define MVPP2_PRS_VLAN_FILT_DFLT_ENTRY (MVPP2_PRS_VLAN_FILT_MAX - 1)
97
98/* Tcam entries ID */
99#define MVPP2_PE_DROP_ALL 0
100#define MVPP2_PE_FIRST_FREE_TID 1
101
102/* MAC filtering range */
103#define MVPP2_PE_MAC_RANGE_END (MVPP2_PE_VID_FILT_RANGE_START - 1)
104#define MVPP2_PE_MAC_RANGE_START (MVPP2_PE_MAC_RANGE_END - \
105 MVPP2_PRS_MAC_RANGE_SIZE + 1)
106/* VLAN filtering range */
107#define MVPP2_PE_VID_FILT_RANGE_END (MVPP2_PRS_TCAM_SRAM_SIZE - 32)
108#define MVPP2_PE_VID_FILT_RANGE_START (MVPP2_PE_VID_FILT_RANGE_END - \
109 MVPP2_PRS_VLAN_FILT_RANGE_SIZE + 1)
110#define MVPP2_PE_LAST_FREE_TID (MVPP2_PE_MAC_RANGE_START - 1)
111#define MVPP2_PE_MH_SKIP_PRS (MVPP2_PRS_TCAM_SRAM_SIZE - 31)
112#define MVPP2_PE_IP6_EXT_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 30)
113#define MVPP2_PE_IP6_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 29)
114#define MVPP2_PE_IP4_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 28)
115#define MVPP2_PE_LAST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 27)
116#define MVPP2_PE_FIRST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 22)
117#define MVPP2_PE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 21)
118#define MVPP2_PE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 20)
119#define MVPP2_PE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 19)
120#define MVPP2_PE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 18)
121#define MVPP2_PE_ETYPE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 17)
122#define MVPP2_PE_ETYPE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 16)
123#define MVPP2_PE_ETYPE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 15)
124#define MVPP2_PE_ETYPE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 14)
125#define MVPP2_PE_MH_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 13)
126#define MVPP2_PE_DSA_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 12)
127#define MVPP2_PE_IP6_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 11)
128#define MVPP2_PE_IP4_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 10)
129#define MVPP2_PE_ETH_TYPE_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 9)
130#define MVPP2_PE_VID_FLTR_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 8)
131#define MVPP2_PE_VID_EDSA_FLTR_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 7)
132#define MVPP2_PE_VLAN_DBL (MVPP2_PRS_TCAM_SRAM_SIZE - 6)
133#define MVPP2_PE_VLAN_NONE (MVPP2_PRS_TCAM_SRAM_SIZE - 5)
134#define MVPP2_PE_FC_DROP (MVPP2_PRS_TCAM_SRAM_SIZE - 4)
135#define MVPP2_PE_MAC_MC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 3)
136#define MVPP2_PE_MAC_UC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 2)
137#define MVPP2_PE_MAC_NON_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 1)
138
139#define MVPP2_PRS_VID_PORT_FIRST(port) (MVPP2_PE_VID_FILT_RANGE_START + \
140 ((port) * MVPP2_PRS_VLAN_FILT_MAX))
141#define MVPP2_PRS_VID_PORT_LAST(port) (MVPP2_PRS_VID_PORT_FIRST(port) \
142 + MVPP2_PRS_VLAN_FILT_MAX_ENTRY)
143/* Index of default vid filter for given port */
144#define MVPP2_PRS_VID_PORT_DFLT(port) (MVPP2_PRS_VID_PORT_FIRST(port) \
145 + MVPP2_PRS_VLAN_FILT_DFLT_ENTRY)
146
147/* Sram structure
148 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(3)->(0).
149 */
150#define MVPP2_PRS_SRAM_RI_OFFS 0
151#define MVPP2_PRS_SRAM_RI_WORD 0
152#define MVPP2_PRS_SRAM_RI_CTRL_OFFS 32
153#define MVPP2_PRS_SRAM_RI_CTRL_WORD 1
154#define MVPP2_PRS_SRAM_RI_CTRL_BITS 32
155#define MVPP2_PRS_SRAM_SHIFT_OFFS 64
156#define MVPP2_PRS_SRAM_SHIFT_SIGN_BIT 72
157#define MVPP2_PRS_SRAM_SHIFT_MASK 0xff
158#define MVPP2_PRS_SRAM_UDF_OFFS 73
159#define MVPP2_PRS_SRAM_UDF_BITS 8
160#define MVPP2_PRS_SRAM_UDF_MASK 0xff
161#define MVPP2_PRS_SRAM_UDF_SIGN_BIT 81
162#define MVPP2_PRS_SRAM_UDF_TYPE_OFFS 82
163#define MVPP2_PRS_SRAM_UDF_TYPE_MASK 0x7
164#define MVPP2_PRS_SRAM_UDF_TYPE_L3 1
165#define MVPP2_PRS_SRAM_UDF_TYPE_L4 4
166#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS 85
167#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK 0x3
168#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD 1
169#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP4_ADD 2
170#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP6_ADD 3
171#define MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS 87
172#define MVPP2_PRS_SRAM_OP_SEL_UDF_BITS 2
173#define MVPP2_PRS_SRAM_OP_SEL_UDF_MASK 0x3
174#define MVPP2_PRS_SRAM_OP_SEL_UDF_ADD 0
175#define MVPP2_PRS_SRAM_OP_SEL_UDF_IP4_ADD 2
176#define MVPP2_PRS_SRAM_OP_SEL_UDF_IP6_ADD 3
177#define MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS 89
178#define MVPP2_PRS_SRAM_AI_OFFS 90
179#define MVPP2_PRS_SRAM_AI_CTRL_OFFS 98
180#define MVPP2_PRS_SRAM_AI_CTRL_BITS 8
181#define MVPP2_PRS_SRAM_AI_MASK 0xff
182#define MVPP2_PRS_SRAM_NEXT_LU_OFFS 106
183#define MVPP2_PRS_SRAM_NEXT_LU_MASK 0xf
184#define MVPP2_PRS_SRAM_LU_DONE_BIT 110
185#define MVPP2_PRS_SRAM_LU_GEN_BIT 111
186
187/* Sram result info bits assignment */
188#define MVPP2_PRS_RI_MAC_ME_MASK 0x1
189#define MVPP2_PRS_RI_DSA_MASK 0x2
190#define MVPP2_PRS_RI_VLAN_MASK (BIT(2) | BIT(3))
191#define MVPP2_PRS_RI_VLAN_NONE 0x0
192#define MVPP2_PRS_RI_VLAN_SINGLE BIT(2)
193#define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3)
194#define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3))
195#define MVPP2_PRS_RI_CPU_CODE_MASK 0x70
196#define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4)
197#define MVPP2_PRS_RI_L2_CAST_MASK (BIT(9) | BIT(10))
198#define MVPP2_PRS_RI_L2_UCAST 0x0
199#define MVPP2_PRS_RI_L2_MCAST BIT(9)
200#define MVPP2_PRS_RI_L2_BCAST BIT(10)
201#define MVPP2_PRS_RI_PPPOE_MASK 0x800
202#define MVPP2_PRS_RI_L3_PROTO_MASK (BIT(12) | BIT(13) | BIT(14))
203#define MVPP2_PRS_RI_L3_UN 0x0
204#define MVPP2_PRS_RI_L3_IP4 BIT(12)
205#define MVPP2_PRS_RI_L3_IP4_OPT BIT(13)
206#define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13))
207#define MVPP2_PRS_RI_L3_IP6 BIT(14)
208#define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14))
209#define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14))
210#define MVPP2_PRS_RI_L3_ADDR_MASK (BIT(15) | BIT(16))
211#define MVPP2_PRS_RI_L3_UCAST 0x0
212#define MVPP2_PRS_RI_L3_MCAST BIT(15)
213#define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16))
214#define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000
215#define MVPP2_PRS_RI_IP_FRAG_TRUE BIT(17)
216#define MVPP2_PRS_RI_UDF3_MASK 0x300000
217#define MVPP2_PRS_RI_UDF3_RX_SPECIAL BIT(21)
218#define MVPP2_PRS_RI_L4_PROTO_MASK 0x1c00000
219#define MVPP2_PRS_RI_L4_TCP BIT(22)
220#define MVPP2_PRS_RI_L4_UDP BIT(23)
221#define MVPP2_PRS_RI_L4_OTHER (BIT(22) | BIT(23))
222#define MVPP2_PRS_RI_UDF7_MASK 0x60000000
223#define MVPP2_PRS_RI_UDF7_IP6_LITE BIT(29)
224#define MVPP2_PRS_RI_DROP_MASK 0x80000000
225
226#define MVPP2_PRS_IP_MASK (MVPP2_PRS_RI_L3_PROTO_MASK | \
227 MVPP2_PRS_RI_IP_FRAG_MASK | \
228 MVPP2_PRS_RI_L4_PROTO_MASK)
229
230/* Sram additional info bits assignment */
231#define MVPP2_PRS_IPV4_DIP_AI_BIT BIT(0)
232#define MVPP2_PRS_IPV6_NO_EXT_AI_BIT BIT(0)
233#define MVPP2_PRS_IPV6_EXT_AI_BIT BIT(1)
234#define MVPP2_PRS_IPV6_EXT_AH_AI_BIT BIT(2)
235#define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT BIT(3)
236#define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT BIT(4)
237#define MVPP2_PRS_SINGLE_VLAN_AI 0
238#define MVPP2_PRS_DBL_VLAN_AI_BIT BIT(7)
239#define MVPP2_PRS_EDSA_VID_AI_BIT BIT(0)
240
241/* DSA/EDSA type */
242#define MVPP2_PRS_TAGGED true
243#define MVPP2_PRS_UNTAGGED false
244#define MVPP2_PRS_EDSA true
245#define MVPP2_PRS_DSA false
246
247/* MAC entries, shadow udf */
248enum mvpp2_prs_udf {
249 MVPP2_PRS_UDF_MAC_DEF,
250 MVPP2_PRS_UDF_MAC_RANGE,
251 MVPP2_PRS_UDF_L2_DEF,
252 MVPP2_PRS_UDF_L2_DEF_COPY,
253 MVPP2_PRS_UDF_L2_USER,
254};
255
256/* Lookup ID */
257enum mvpp2_prs_lookup {
258 MVPP2_PRS_LU_MH,
259 MVPP2_PRS_LU_MAC,
260 MVPP2_PRS_LU_DSA,
261 MVPP2_PRS_LU_VLAN,
262 MVPP2_PRS_LU_VID,
263 MVPP2_PRS_LU_L2,
264 MVPP2_PRS_LU_PPPOE,
265 MVPP2_PRS_LU_IP4,
266 MVPP2_PRS_LU_IP6,
267 MVPP2_PRS_LU_FLOWS,
268 MVPP2_PRS_LU_LAST,
269};
270
271struct mvpp2_prs_entry {
272 u32 index;
273 u32 tcam[MVPP2_PRS_TCAM_WORDS];
274 u32 sram[MVPP2_PRS_SRAM_WORDS];
275};
276
277struct mvpp2_prs_result_info {
278 u32 ri;
279 u32 ri_mask;
280};
281
282struct mvpp2_prs_shadow {
283 bool valid;
284 bool finish;
285
286 /* Lookup ID */
287 int lu;
288
289 /* User defined offset */
290 int udf;
291
292 /* Result info */
293 u32 ri;
294 u32 ri_mask;
295};
296
297int mvpp2_prs_default_init(struct platform_device *pdev, struct mvpp2 *priv);
298
299int mvpp2_prs_init_from_hw(struct mvpp2 *priv, struct mvpp2_prs_entry *pe,
300 int tid);
301
302unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe);
303
304void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe,
305 unsigned int offs, unsigned char *byte,
306 unsigned char *enable);
307
308int mvpp2_prs_mac_da_accept(struct mvpp2_port *port, const u8 *da, bool add);
309
310int mvpp2_prs_tag_mode_set(struct mvpp2 *priv, int port, int type);
311
312int mvpp2_prs_add_flow(struct mvpp2 *priv, int flow, u32 ri, u32 ri_mask);
313
314int mvpp2_prs_def_flow(struct mvpp2_port *port);
315
316void mvpp2_prs_vid_enable_filtering(struct mvpp2_port *port);
317
318void mvpp2_prs_vid_disable_filtering(struct mvpp2_port *port);
319
320int mvpp2_prs_vid_entry_add(struct mvpp2_port *port, u16 vid);
321
322void mvpp2_prs_vid_entry_remove(struct mvpp2_port *port, u16 vid);
323
324void mvpp2_prs_vid_remove_all(struct mvpp2_port *port);
325
326void mvpp2_prs_mac_promisc_set(struct mvpp2 *priv, int port,
327 enum mvpp2_prs_l2_cast l2_cast, bool add);
328
329void mvpp2_prs_mac_del_all(struct mvpp2_port *port);
330
331int mvpp2_prs_update_mac_da(struct net_device *dev, const u8 *da);
332
333int mvpp2_prs_hits(struct mvpp2 *priv, int index);
334
335#endif
336

source code of linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h