1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* |
3 | * Driver for Analog Devices Industrial Ethernet PHYs |
4 | * |
5 | * Copyright 2019 Analog Devices Inc. |
6 | */ |
7 | #include <linux/kernel.h> |
8 | #include <linux/bitfield.h> |
9 | #include <linux/delay.h> |
10 | #include <linux/errno.h> |
11 | #include <linux/ethtool_netlink.h> |
12 | #include <linux/init.h> |
13 | #include <linux/module.h> |
14 | #include <linux/mii.h> |
15 | #include <linux/phy.h> |
16 | #include <linux/property.h> |
17 | |
18 | #define PHY_ID_ADIN1200 0x0283bc20 |
19 | #define PHY_ID_ADIN1300 0x0283bc30 |
20 | |
21 | #define ADIN1300_MII_EXT_REG_PTR 0x0010 |
22 | #define ADIN1300_MII_EXT_REG_DATA 0x0011 |
23 | |
24 | #define ADIN1300_PHY_CTRL1 0x0012 |
25 | #define ADIN1300_AUTO_MDI_EN BIT(10) |
26 | #define ADIN1300_MAN_MDIX_EN BIT(9) |
27 | #define ADIN1300_DIAG_CLK_EN BIT(2) |
28 | |
29 | #define ADIN1300_RX_ERR_CNT 0x0014 |
30 | |
31 | #define ADIN1300_PHY_CTRL_STATUS2 0x0015 |
32 | #define ADIN1300_NRG_PD_EN BIT(3) |
33 | #define ADIN1300_NRG_PD_TX_EN BIT(2) |
34 | #define ADIN1300_NRG_PD_STATUS BIT(1) |
35 | |
36 | #define ADIN1300_PHY_CTRL2 0x0016 |
37 | #define ADIN1300_DOWNSPEED_AN_100_EN BIT(11) |
38 | #define ADIN1300_DOWNSPEED_AN_10_EN BIT(10) |
39 | #define ADIN1300_GROUP_MDIO_EN BIT(6) |
40 | #define ADIN1300_DOWNSPEEDS_EN \ |
41 | (ADIN1300_DOWNSPEED_AN_100_EN | ADIN1300_DOWNSPEED_AN_10_EN) |
42 | |
43 | #define ADIN1300_PHY_CTRL3 0x0017 |
44 | #define ADIN1300_LINKING_EN BIT(13) |
45 | #define ADIN1300_DOWNSPEED_RETRIES_MSK GENMASK(12, 10) |
46 | |
47 | #define ADIN1300_INT_MASK_REG 0x0018 |
48 | #define ADIN1300_INT_MDIO_SYNC_EN BIT(9) |
49 | #define ADIN1300_INT_ANEG_STAT_CHNG_EN BIT(8) |
50 | #define ADIN1300_INT_ANEG_PAGE_RX_EN BIT(6) |
51 | #define ADIN1300_INT_IDLE_ERR_CNT_EN BIT(5) |
52 | #define ADIN1300_INT_MAC_FIFO_OU_EN BIT(4) |
53 | #define ADIN1300_INT_RX_STAT_CHNG_EN BIT(3) |
54 | #define ADIN1300_INT_LINK_STAT_CHNG_EN BIT(2) |
55 | #define ADIN1300_INT_SPEED_CHNG_EN BIT(1) |
56 | #define ADIN1300_INT_HW_IRQ_EN BIT(0) |
57 | #define ADIN1300_INT_MASK_EN \ |
58 | (ADIN1300_INT_LINK_STAT_CHNG_EN | ADIN1300_INT_HW_IRQ_EN) |
59 | #define ADIN1300_INT_STATUS_REG 0x0019 |
60 | |
61 | #define ADIN1300_PHY_STATUS1 0x001a |
62 | #define ADIN1300_PAIR_01_SWAP BIT(11) |
63 | |
64 | /* EEE register addresses, accessible via Clause 22 access using |
65 | * ADIN1300_MII_EXT_REG_PTR & ADIN1300_MII_EXT_REG_DATA. |
66 | * The bit-fields are the same as specified by IEEE for EEE. |
67 | */ |
68 | #define ADIN1300_EEE_CAP_REG 0x8000 |
69 | #define ADIN1300_EEE_ADV_REG 0x8001 |
70 | #define ADIN1300_EEE_LPABLE_REG 0x8002 |
71 | #define ADIN1300_CLOCK_STOP_REG 0x9400 |
72 | #define ADIN1300_LPI_WAKE_ERR_CNT_REG 0xa000 |
73 | |
74 | #define ADIN1300_CDIAG_RUN 0xba1b |
75 | #define ADIN1300_CDIAG_RUN_EN BIT(0) |
76 | |
77 | /* |
78 | * The XSIM3/2/1 and XSHRT3/2/1 are actually relative. |
79 | * For CDIAG_DTLD_RSLTS(0) it's ADIN1300_CDIAG_RSLT_XSIM3/2/1 |
80 | * For CDIAG_DTLD_RSLTS(1) it's ADIN1300_CDIAG_RSLT_XSIM3/2/0 |
81 | * For CDIAG_DTLD_RSLTS(2) it's ADIN1300_CDIAG_RSLT_XSIM3/1/0 |
82 | * For CDIAG_DTLD_RSLTS(3) it's ADIN1300_CDIAG_RSLT_XSIM2/1/0 |
83 | */ |
84 | #define ADIN1300_CDIAG_DTLD_RSLTS(x) (0xba1d + (x)) |
85 | #define ADIN1300_CDIAG_RSLT_BUSY BIT(10) |
86 | #define ADIN1300_CDIAG_RSLT_XSIM3 BIT(9) |
87 | #define ADIN1300_CDIAG_RSLT_XSIM2 BIT(8) |
88 | #define ADIN1300_CDIAG_RSLT_XSIM1 BIT(7) |
89 | #define ADIN1300_CDIAG_RSLT_SIM BIT(6) |
90 | #define ADIN1300_CDIAG_RSLT_XSHRT3 BIT(5) |
91 | #define ADIN1300_CDIAG_RSLT_XSHRT2 BIT(4) |
92 | #define ADIN1300_CDIAG_RSLT_XSHRT1 BIT(3) |
93 | #define ADIN1300_CDIAG_RSLT_SHRT BIT(2) |
94 | #define ADIN1300_CDIAG_RSLT_OPEN BIT(1) |
95 | #define ADIN1300_CDIAG_RSLT_GOOD BIT(0) |
96 | |
97 | #define ADIN1300_CDIAG_FLT_DIST(x) (0xba21 + (x)) |
98 | |
99 | #define ADIN1300_GE_SOFT_RESET_REG 0xff0c |
100 | #define ADIN1300_GE_SOFT_RESET BIT(0) |
101 | |
102 | #define ADIN1300_GE_CLK_CFG_REG 0xff1f |
103 | #define ADIN1300_GE_CLK_CFG_MASK GENMASK(5, 0) |
104 | #define ADIN1300_GE_CLK_CFG_RCVR_125 BIT(5) |
105 | #define ADIN1300_GE_CLK_CFG_FREE_125 BIT(4) |
106 | #define ADIN1300_GE_CLK_CFG_REF_EN BIT(3) |
107 | #define ADIN1300_GE_CLK_CFG_HRT_RCVR BIT(2) |
108 | #define ADIN1300_GE_CLK_CFG_HRT_FREE BIT(1) |
109 | #define ADIN1300_GE_CLK_CFG_25 BIT(0) |
110 | |
111 | #define ADIN1300_GE_RGMII_CFG_REG 0xff23 |
112 | #define ADIN1300_GE_RGMII_RX_MSK GENMASK(8, 6) |
113 | #define ADIN1300_GE_RGMII_RX_SEL(x) \ |
114 | FIELD_PREP(ADIN1300_GE_RGMII_RX_MSK, x) |
115 | #define ADIN1300_GE_RGMII_GTX_MSK GENMASK(5, 3) |
116 | #define ADIN1300_GE_RGMII_GTX_SEL(x) \ |
117 | FIELD_PREP(ADIN1300_GE_RGMII_GTX_MSK, x) |
118 | #define ADIN1300_GE_RGMII_RXID_EN BIT(2) |
119 | #define ADIN1300_GE_RGMII_TXID_EN BIT(1) |
120 | #define ADIN1300_GE_RGMII_EN BIT(0) |
121 | |
122 | /* RGMII internal delay settings for rx and tx for ADIN1300 */ |
123 | #define ADIN1300_RGMII_1_60_NS 0x0001 |
124 | #define ADIN1300_RGMII_1_80_NS 0x0002 |
125 | #define ADIN1300_RGMII_2_00_NS 0x0000 |
126 | #define ADIN1300_RGMII_2_20_NS 0x0006 |
127 | #define ADIN1300_RGMII_2_40_NS 0x0007 |
128 | |
129 | #define ADIN1300_GE_RMII_CFG_REG 0xff24 |
130 | #define ADIN1300_GE_RMII_FIFO_DEPTH_MSK GENMASK(6, 4) |
131 | #define ADIN1300_GE_RMII_FIFO_DEPTH_SEL(x) \ |
132 | FIELD_PREP(ADIN1300_GE_RMII_FIFO_DEPTH_MSK, x) |
133 | #define ADIN1300_GE_RMII_EN BIT(0) |
134 | |
135 | /* RMII fifo depth values */ |
136 | #define ADIN1300_RMII_4_BITS 0x0000 |
137 | #define ADIN1300_RMII_8_BITS 0x0001 |
138 | #define ADIN1300_RMII_12_BITS 0x0002 |
139 | #define ADIN1300_RMII_16_BITS 0x0003 |
140 | #define ADIN1300_RMII_20_BITS 0x0004 |
141 | #define ADIN1300_RMII_24_BITS 0x0005 |
142 | |
143 | /** |
144 | * struct adin_cfg_reg_map - map a config value to aregister value |
145 | * @cfg: value in device configuration |
146 | * @reg: value in the register |
147 | */ |
148 | struct adin_cfg_reg_map { |
149 | int cfg; |
150 | int reg; |
151 | }; |
152 | |
153 | static const struct adin_cfg_reg_map adin_rgmii_delays[] = { |
154 | { 1600, ADIN1300_RGMII_1_60_NS }, |
155 | { 1800, ADIN1300_RGMII_1_80_NS }, |
156 | { 2000, ADIN1300_RGMII_2_00_NS }, |
157 | { 2200, ADIN1300_RGMII_2_20_NS }, |
158 | { 2400, ADIN1300_RGMII_2_40_NS }, |
159 | { }, |
160 | }; |
161 | |
162 | static const struct adin_cfg_reg_map adin_rmii_fifo_depths[] = { |
163 | { 4, ADIN1300_RMII_4_BITS }, |
164 | { 8, ADIN1300_RMII_8_BITS }, |
165 | { 12, ADIN1300_RMII_12_BITS }, |
166 | { 16, ADIN1300_RMII_16_BITS }, |
167 | { 20, ADIN1300_RMII_20_BITS }, |
168 | { 24, ADIN1300_RMII_24_BITS }, |
169 | { }, |
170 | }; |
171 | |
172 | /** |
173 | * struct adin_clause45_mmd_map - map to convert Clause 45 regs to Clause 22 |
174 | * @devad: device address used in Clause 45 access |
175 | * @cl45_regnum: register address defined by Clause 45 |
176 | * @adin_regnum: equivalent register address accessible via Clause 22 |
177 | */ |
178 | struct adin_clause45_mmd_map { |
179 | int devad; |
180 | u16 cl45_regnum; |
181 | u16 adin_regnum; |
182 | }; |
183 | |
184 | static const struct adin_clause45_mmd_map adin_clause45_mmd_map[] = { |
185 | { MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE, ADIN1300_EEE_CAP_REG }, |
186 | { MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, ADIN1300_EEE_LPABLE_REG }, |
187 | { MDIO_MMD_AN, MDIO_AN_EEE_ADV, ADIN1300_EEE_ADV_REG }, |
188 | { MDIO_MMD_PCS, MDIO_CTRL1, ADIN1300_CLOCK_STOP_REG }, |
189 | { MDIO_MMD_PCS, MDIO_PCS_EEE_WK_ERR, ADIN1300_LPI_WAKE_ERR_CNT_REG }, |
190 | }; |
191 | |
192 | struct adin_hw_stat { |
193 | const char *string; |
194 | u16 reg1; |
195 | u16 reg2; |
196 | }; |
197 | |
198 | static const struct adin_hw_stat adin_hw_stats[] = { |
199 | { "total_frames_checked_count" , 0x940A, 0x940B }, /* hi + lo */ |
200 | { "length_error_frames_count" , 0x940C }, |
201 | { "alignment_error_frames_count" , 0x940D }, |
202 | { "symbol_error_count" , 0x940E }, |
203 | { "oversized_frames_count" , 0x940F }, |
204 | { "undersized_frames_count" , 0x9410 }, |
205 | { "odd_nibble_frames_count" , 0x9411 }, |
206 | { "odd_preamble_packet_count" , 0x9412 }, |
207 | { "dribble_bits_frames_count" , 0x9413 }, |
208 | { "false_carrier_events_count" , 0x9414 }, |
209 | }; |
210 | |
211 | /** |
212 | * struct adin_priv - ADIN PHY driver private data |
213 | * @stats: statistic counters for the PHY |
214 | */ |
215 | struct adin_priv { |
216 | u64 stats[ARRAY_SIZE(adin_hw_stats)]; |
217 | }; |
218 | |
219 | static int adin_lookup_reg_value(const struct adin_cfg_reg_map *tbl, int cfg) |
220 | { |
221 | size_t i; |
222 | |
223 | for (i = 0; tbl[i].cfg; i++) { |
224 | if (tbl[i].cfg == cfg) |
225 | return tbl[i].reg; |
226 | } |
227 | |
228 | return -EINVAL; |
229 | } |
230 | |
231 | static u32 adin_get_reg_value(struct phy_device *phydev, |
232 | const char *prop_name, |
233 | const struct adin_cfg_reg_map *tbl, |
234 | u32 dflt) |
235 | { |
236 | struct device *dev = &phydev->mdio.dev; |
237 | u32 val; |
238 | int rc; |
239 | |
240 | if (device_property_read_u32(dev, propname: prop_name, val: &val)) |
241 | return dflt; |
242 | |
243 | rc = adin_lookup_reg_value(tbl, cfg: val); |
244 | if (rc < 0) { |
245 | phydev_warn(phydev, |
246 | "Unsupported value %u for %s using default (%u)\n" , |
247 | val, prop_name, dflt); |
248 | return dflt; |
249 | } |
250 | |
251 | return rc; |
252 | } |
253 | |
254 | static int adin_config_rgmii_mode(struct phy_device *phydev) |
255 | { |
256 | u32 val; |
257 | int reg; |
258 | |
259 | if (!phy_interface_is_rgmii(phydev)) |
260 | return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
261 | ADIN1300_GE_RGMII_CFG_REG, |
262 | ADIN1300_GE_RGMII_EN); |
263 | |
264 | reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RGMII_CFG_REG); |
265 | if (reg < 0) |
266 | return reg; |
267 | |
268 | reg |= ADIN1300_GE_RGMII_EN; |
269 | |
270 | if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || |
271 | phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { |
272 | reg |= ADIN1300_GE_RGMII_RXID_EN; |
273 | |
274 | val = adin_get_reg_value(phydev, prop_name: "adi,rx-internal-delay-ps" , |
275 | tbl: adin_rgmii_delays, |
276 | ADIN1300_RGMII_2_00_NS); |
277 | reg &= ~ADIN1300_GE_RGMII_RX_MSK; |
278 | reg |= ADIN1300_GE_RGMII_RX_SEL(val); |
279 | } else { |
280 | reg &= ~ADIN1300_GE_RGMII_RXID_EN; |
281 | } |
282 | |
283 | if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || |
284 | phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { |
285 | reg |= ADIN1300_GE_RGMII_TXID_EN; |
286 | |
287 | val = adin_get_reg_value(phydev, prop_name: "adi,tx-internal-delay-ps" , |
288 | tbl: adin_rgmii_delays, |
289 | ADIN1300_RGMII_2_00_NS); |
290 | reg &= ~ADIN1300_GE_RGMII_GTX_MSK; |
291 | reg |= ADIN1300_GE_RGMII_GTX_SEL(val); |
292 | } else { |
293 | reg &= ~ADIN1300_GE_RGMII_TXID_EN; |
294 | } |
295 | |
296 | return phy_write_mmd(phydev, MDIO_MMD_VEND1, |
297 | ADIN1300_GE_RGMII_CFG_REG, val: reg); |
298 | } |
299 | |
300 | static int adin_config_rmii_mode(struct phy_device *phydev) |
301 | { |
302 | u32 val; |
303 | int reg; |
304 | |
305 | if (phydev->interface != PHY_INTERFACE_MODE_RMII) |
306 | return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
307 | ADIN1300_GE_RMII_CFG_REG, |
308 | ADIN1300_GE_RMII_EN); |
309 | |
310 | reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RMII_CFG_REG); |
311 | if (reg < 0) |
312 | return reg; |
313 | |
314 | reg |= ADIN1300_GE_RMII_EN; |
315 | |
316 | val = adin_get_reg_value(phydev, prop_name: "adi,fifo-depth-bits" , |
317 | tbl: adin_rmii_fifo_depths, |
318 | ADIN1300_RMII_8_BITS); |
319 | |
320 | reg &= ~ADIN1300_GE_RMII_FIFO_DEPTH_MSK; |
321 | reg |= ADIN1300_GE_RMII_FIFO_DEPTH_SEL(val); |
322 | |
323 | return phy_write_mmd(phydev, MDIO_MMD_VEND1, |
324 | ADIN1300_GE_RMII_CFG_REG, val: reg); |
325 | } |
326 | |
327 | static int adin_get_downshift(struct phy_device *phydev, u8 *data) |
328 | { |
329 | int val, cnt, enable; |
330 | |
331 | val = phy_read(phydev, ADIN1300_PHY_CTRL2); |
332 | if (val < 0) |
333 | return val; |
334 | |
335 | cnt = phy_read(phydev, ADIN1300_PHY_CTRL3); |
336 | if (cnt < 0) |
337 | return cnt; |
338 | |
339 | enable = FIELD_GET(ADIN1300_DOWNSPEEDS_EN, val); |
340 | cnt = FIELD_GET(ADIN1300_DOWNSPEED_RETRIES_MSK, cnt); |
341 | |
342 | *data = (enable && cnt) ? cnt : DOWNSHIFT_DEV_DISABLE; |
343 | |
344 | return 0; |
345 | } |
346 | |
347 | static int adin_set_downshift(struct phy_device *phydev, u8 cnt) |
348 | { |
349 | u16 val; |
350 | int rc; |
351 | |
352 | if (cnt == DOWNSHIFT_DEV_DISABLE) |
353 | return phy_clear_bits(phydev, ADIN1300_PHY_CTRL2, |
354 | ADIN1300_DOWNSPEEDS_EN); |
355 | |
356 | if (cnt > 7) |
357 | return -E2BIG; |
358 | |
359 | val = FIELD_PREP(ADIN1300_DOWNSPEED_RETRIES_MSK, cnt); |
360 | |
361 | rc = phy_modify(phydev, ADIN1300_PHY_CTRL3, |
362 | ADIN1300_DOWNSPEED_RETRIES_MSK, |
363 | set: val); |
364 | if (rc < 0) |
365 | return rc; |
366 | |
367 | return phy_set_bits(phydev, ADIN1300_PHY_CTRL2, |
368 | ADIN1300_DOWNSPEEDS_EN); |
369 | } |
370 | |
371 | static int adin_get_edpd(struct phy_device *phydev, u16 *tx_interval) |
372 | { |
373 | int val; |
374 | |
375 | val = phy_read(phydev, ADIN1300_PHY_CTRL_STATUS2); |
376 | if (val < 0) |
377 | return val; |
378 | |
379 | if (ADIN1300_NRG_PD_EN & val) { |
380 | if (val & ADIN1300_NRG_PD_TX_EN) |
381 | /* default is 1 second */ |
382 | *tx_interval = ETHTOOL_PHY_EDPD_DFLT_TX_MSECS; |
383 | else |
384 | *tx_interval = ETHTOOL_PHY_EDPD_NO_TX; |
385 | } else { |
386 | *tx_interval = ETHTOOL_PHY_EDPD_DISABLE; |
387 | } |
388 | |
389 | return 0; |
390 | } |
391 | |
392 | static int adin_set_edpd(struct phy_device *phydev, u16 tx_interval) |
393 | { |
394 | u16 val; |
395 | |
396 | if (tx_interval == ETHTOOL_PHY_EDPD_DISABLE) |
397 | return phy_clear_bits(phydev, ADIN1300_PHY_CTRL_STATUS2, |
398 | val: (ADIN1300_NRG_PD_EN | ADIN1300_NRG_PD_TX_EN)); |
399 | |
400 | val = ADIN1300_NRG_PD_EN; |
401 | |
402 | switch (tx_interval) { |
403 | case 1000: /* 1 second */ |
404 | fallthrough; |
405 | case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS: |
406 | val |= ADIN1300_NRG_PD_TX_EN; |
407 | fallthrough; |
408 | case ETHTOOL_PHY_EDPD_NO_TX: |
409 | break; |
410 | default: |
411 | return -EINVAL; |
412 | } |
413 | |
414 | return phy_modify(phydev, ADIN1300_PHY_CTRL_STATUS2, |
415 | mask: (ADIN1300_NRG_PD_EN | ADIN1300_NRG_PD_TX_EN), |
416 | set: val); |
417 | } |
418 | |
419 | static int adin_get_tunable(struct phy_device *phydev, |
420 | struct ethtool_tunable *tuna, void *data) |
421 | { |
422 | switch (tuna->id) { |
423 | case ETHTOOL_PHY_DOWNSHIFT: |
424 | return adin_get_downshift(phydev, data); |
425 | case ETHTOOL_PHY_EDPD: |
426 | return adin_get_edpd(phydev, tx_interval: data); |
427 | default: |
428 | return -EOPNOTSUPP; |
429 | } |
430 | } |
431 | |
432 | static int adin_set_tunable(struct phy_device *phydev, |
433 | struct ethtool_tunable *tuna, const void *data) |
434 | { |
435 | switch (tuna->id) { |
436 | case ETHTOOL_PHY_DOWNSHIFT: |
437 | return adin_set_downshift(phydev, cnt: *(const u8 *)data); |
438 | case ETHTOOL_PHY_EDPD: |
439 | return adin_set_edpd(phydev, tx_interval: *(const u16 *)data); |
440 | default: |
441 | return -EOPNOTSUPP; |
442 | } |
443 | } |
444 | |
445 | static int adin_config_clk_out(struct phy_device *phydev) |
446 | { |
447 | struct device *dev = &phydev->mdio.dev; |
448 | const char *val = NULL; |
449 | u8 sel = 0; |
450 | |
451 | device_property_read_string(dev, propname: "adi,phy-output-clock" , val: &val); |
452 | if (!val) { |
453 | /* property not present, do not enable GP_CLK pin */ |
454 | } else if (strcmp(val, "25mhz-reference" ) == 0) { |
455 | sel |= ADIN1300_GE_CLK_CFG_25; |
456 | } else if (strcmp(val, "125mhz-free-running" ) == 0) { |
457 | sel |= ADIN1300_GE_CLK_CFG_FREE_125; |
458 | } else if (strcmp(val, "adaptive-free-running" ) == 0) { |
459 | sel |= ADIN1300_GE_CLK_CFG_HRT_FREE; |
460 | } else { |
461 | phydev_err(phydev, "invalid adi,phy-output-clock\n" ); |
462 | return -EINVAL; |
463 | } |
464 | |
465 | if (device_property_read_bool(dev, propname: "adi,phy-output-reference-clock" )) |
466 | sel |= ADIN1300_GE_CLK_CFG_REF_EN; |
467 | |
468 | return phy_modify_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_CLK_CFG_REG, |
469 | ADIN1300_GE_CLK_CFG_MASK, set: sel); |
470 | } |
471 | |
472 | static int adin_config_init(struct phy_device *phydev) |
473 | { |
474 | int rc; |
475 | |
476 | phydev->mdix_ctrl = ETH_TP_MDI_AUTO; |
477 | |
478 | rc = adin_config_rgmii_mode(phydev); |
479 | if (rc < 0) |
480 | return rc; |
481 | |
482 | rc = adin_config_rmii_mode(phydev); |
483 | if (rc < 0) |
484 | return rc; |
485 | |
486 | rc = adin_set_downshift(phydev, cnt: 4); |
487 | if (rc < 0) |
488 | return rc; |
489 | |
490 | rc = adin_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS); |
491 | if (rc < 0) |
492 | return rc; |
493 | |
494 | rc = adin_config_clk_out(phydev); |
495 | if (rc < 0) |
496 | return rc; |
497 | |
498 | phydev_dbg(phydev, "PHY is using mode '%s'\n" , |
499 | phy_modes(phydev->interface)); |
500 | |
501 | return 0; |
502 | } |
503 | |
504 | static int adin_phy_ack_intr(struct phy_device *phydev) |
505 | { |
506 | /* Clear pending interrupts */ |
507 | int rc = phy_read(phydev, ADIN1300_INT_STATUS_REG); |
508 | |
509 | return rc < 0 ? rc : 0; |
510 | } |
511 | |
512 | static int adin_phy_config_intr(struct phy_device *phydev) |
513 | { |
514 | int err; |
515 | |
516 | if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { |
517 | err = adin_phy_ack_intr(phydev); |
518 | if (err) |
519 | return err; |
520 | |
521 | err = phy_set_bits(phydev, ADIN1300_INT_MASK_REG, |
522 | ADIN1300_INT_MASK_EN); |
523 | } else { |
524 | err = phy_clear_bits(phydev, ADIN1300_INT_MASK_REG, |
525 | ADIN1300_INT_MASK_EN); |
526 | if (err) |
527 | return err; |
528 | |
529 | err = adin_phy_ack_intr(phydev); |
530 | } |
531 | |
532 | return err; |
533 | } |
534 | |
535 | static irqreturn_t adin_phy_handle_interrupt(struct phy_device *phydev) |
536 | { |
537 | int irq_status; |
538 | |
539 | irq_status = phy_read(phydev, ADIN1300_INT_STATUS_REG); |
540 | if (irq_status < 0) { |
541 | phy_error(phydev); |
542 | return IRQ_NONE; |
543 | } |
544 | |
545 | if (!(irq_status & ADIN1300_INT_LINK_STAT_CHNG_EN)) |
546 | return IRQ_NONE; |
547 | |
548 | phy_trigger_machine(phydev); |
549 | |
550 | return IRQ_HANDLED; |
551 | } |
552 | |
553 | static int adin_cl45_to_adin_reg(struct phy_device *phydev, int devad, |
554 | u16 cl45_regnum) |
555 | { |
556 | const struct adin_clause45_mmd_map *m; |
557 | int i; |
558 | |
559 | if (devad == MDIO_MMD_VEND1) |
560 | return cl45_regnum; |
561 | |
562 | for (i = 0; i < ARRAY_SIZE(adin_clause45_mmd_map); i++) { |
563 | m = &adin_clause45_mmd_map[i]; |
564 | if (m->devad == devad && m->cl45_regnum == cl45_regnum) |
565 | return m->adin_regnum; |
566 | } |
567 | |
568 | phydev_err(phydev, |
569 | "No translation available for devad: %d reg: %04x\n" , |
570 | devad, cl45_regnum); |
571 | |
572 | return -EINVAL; |
573 | } |
574 | |
575 | static int adin_read_mmd(struct phy_device *phydev, int devad, u16 regnum) |
576 | { |
577 | struct mii_bus *bus = phydev->mdio.bus; |
578 | int phy_addr = phydev->mdio.addr; |
579 | int adin_regnum; |
580 | int err; |
581 | |
582 | adin_regnum = adin_cl45_to_adin_reg(phydev, devad, cl45_regnum: regnum); |
583 | if (adin_regnum < 0) |
584 | return adin_regnum; |
585 | |
586 | err = __mdiobus_write(bus, addr: phy_addr, ADIN1300_MII_EXT_REG_PTR, |
587 | val: adin_regnum); |
588 | if (err) |
589 | return err; |
590 | |
591 | return __mdiobus_read(bus, addr: phy_addr, ADIN1300_MII_EXT_REG_DATA); |
592 | } |
593 | |
594 | static int adin_write_mmd(struct phy_device *phydev, int devad, u16 regnum, |
595 | u16 val) |
596 | { |
597 | struct mii_bus *bus = phydev->mdio.bus; |
598 | int phy_addr = phydev->mdio.addr; |
599 | int adin_regnum; |
600 | int err; |
601 | |
602 | adin_regnum = adin_cl45_to_adin_reg(phydev, devad, cl45_regnum: regnum); |
603 | if (adin_regnum < 0) |
604 | return adin_regnum; |
605 | |
606 | err = __mdiobus_write(bus, addr: phy_addr, ADIN1300_MII_EXT_REG_PTR, |
607 | val: adin_regnum); |
608 | if (err) |
609 | return err; |
610 | |
611 | return __mdiobus_write(bus, addr: phy_addr, ADIN1300_MII_EXT_REG_DATA, val); |
612 | } |
613 | |
614 | static int adin_config_mdix(struct phy_device *phydev) |
615 | { |
616 | bool auto_en, mdix_en; |
617 | int reg; |
618 | |
619 | mdix_en = false; |
620 | auto_en = false; |
621 | switch (phydev->mdix_ctrl) { |
622 | case ETH_TP_MDI: |
623 | break; |
624 | case ETH_TP_MDI_X: |
625 | mdix_en = true; |
626 | break; |
627 | case ETH_TP_MDI_AUTO: |
628 | auto_en = true; |
629 | break; |
630 | default: |
631 | return -EINVAL; |
632 | } |
633 | |
634 | reg = phy_read(phydev, ADIN1300_PHY_CTRL1); |
635 | if (reg < 0) |
636 | return reg; |
637 | |
638 | if (mdix_en) |
639 | reg |= ADIN1300_MAN_MDIX_EN; |
640 | else |
641 | reg &= ~ADIN1300_MAN_MDIX_EN; |
642 | |
643 | if (auto_en) |
644 | reg |= ADIN1300_AUTO_MDI_EN; |
645 | else |
646 | reg &= ~ADIN1300_AUTO_MDI_EN; |
647 | |
648 | return phy_write(phydev, ADIN1300_PHY_CTRL1, val: reg); |
649 | } |
650 | |
651 | static int adin_config_aneg(struct phy_device *phydev) |
652 | { |
653 | int ret; |
654 | |
655 | ret = phy_clear_bits(phydev, ADIN1300_PHY_CTRL1, ADIN1300_DIAG_CLK_EN); |
656 | if (ret < 0) |
657 | return ret; |
658 | |
659 | ret = phy_set_bits(phydev, ADIN1300_PHY_CTRL3, ADIN1300_LINKING_EN); |
660 | if (ret < 0) |
661 | return ret; |
662 | |
663 | ret = adin_config_mdix(phydev); |
664 | if (ret) |
665 | return ret; |
666 | |
667 | return genphy_config_aneg(phydev); |
668 | } |
669 | |
670 | static int adin_mdix_update(struct phy_device *phydev) |
671 | { |
672 | bool auto_en, mdix_en; |
673 | bool swapped; |
674 | int reg; |
675 | |
676 | reg = phy_read(phydev, ADIN1300_PHY_CTRL1); |
677 | if (reg < 0) |
678 | return reg; |
679 | |
680 | auto_en = !!(reg & ADIN1300_AUTO_MDI_EN); |
681 | mdix_en = !!(reg & ADIN1300_MAN_MDIX_EN); |
682 | |
683 | /* If MDI/MDIX is forced, just read it from the control reg */ |
684 | if (!auto_en) { |
685 | if (mdix_en) |
686 | phydev->mdix = ETH_TP_MDI_X; |
687 | else |
688 | phydev->mdix = ETH_TP_MDI; |
689 | return 0; |
690 | } |
691 | |
692 | /** |
693 | * Otherwise, we need to deduce it from the PHY status2 reg. |
694 | * When Auto-MDI is enabled, the ADIN1300_MAN_MDIX_EN bit implies |
695 | * a preference for MDIX when it is set. |
696 | */ |
697 | reg = phy_read(phydev, ADIN1300_PHY_STATUS1); |
698 | if (reg < 0) |
699 | return reg; |
700 | |
701 | swapped = !!(reg & ADIN1300_PAIR_01_SWAP); |
702 | |
703 | if (mdix_en != swapped) |
704 | phydev->mdix = ETH_TP_MDI_X; |
705 | else |
706 | phydev->mdix = ETH_TP_MDI; |
707 | |
708 | return 0; |
709 | } |
710 | |
711 | static int adin_read_status(struct phy_device *phydev) |
712 | { |
713 | int ret; |
714 | |
715 | ret = adin_mdix_update(phydev); |
716 | if (ret < 0) |
717 | return ret; |
718 | |
719 | return genphy_read_status(phydev); |
720 | } |
721 | |
722 | static int adin_soft_reset(struct phy_device *phydev) |
723 | { |
724 | int rc; |
725 | |
726 | /* The reset bit is self-clearing, set it and wait */ |
727 | rc = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, |
728 | ADIN1300_GE_SOFT_RESET_REG, |
729 | ADIN1300_GE_SOFT_RESET); |
730 | if (rc < 0) |
731 | return rc; |
732 | |
733 | msleep(msecs: 20); |
734 | |
735 | /* If we get a read error something may be wrong */ |
736 | rc = phy_read_mmd(phydev, MDIO_MMD_VEND1, |
737 | ADIN1300_GE_SOFT_RESET_REG); |
738 | |
739 | return rc < 0 ? rc : 0; |
740 | } |
741 | |
742 | static int adin_get_sset_count(struct phy_device *phydev) |
743 | { |
744 | return ARRAY_SIZE(adin_hw_stats); |
745 | } |
746 | |
747 | static void adin_get_strings(struct phy_device *phydev, u8 *data) |
748 | { |
749 | int i; |
750 | |
751 | for (i = 0; i < ARRAY_SIZE(adin_hw_stats); i++) { |
752 | strscpy(p: &data[i * ETH_GSTRING_LEN], |
753 | q: adin_hw_stats[i].string, ETH_GSTRING_LEN); |
754 | } |
755 | } |
756 | |
757 | static int adin_read_mmd_stat_regs(struct phy_device *phydev, |
758 | const struct adin_hw_stat *stat, |
759 | u32 *val) |
760 | { |
761 | int ret; |
762 | |
763 | ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, regnum: stat->reg1); |
764 | if (ret < 0) |
765 | return ret; |
766 | |
767 | *val = (ret & 0xffff); |
768 | |
769 | if (stat->reg2 == 0) |
770 | return 0; |
771 | |
772 | ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, regnum: stat->reg2); |
773 | if (ret < 0) |
774 | return ret; |
775 | |
776 | *val <<= 16; |
777 | *val |= (ret & 0xffff); |
778 | |
779 | return 0; |
780 | } |
781 | |
782 | static u64 adin_get_stat(struct phy_device *phydev, int i) |
783 | { |
784 | const struct adin_hw_stat *stat = &adin_hw_stats[i]; |
785 | struct adin_priv *priv = phydev->priv; |
786 | u32 val; |
787 | int ret; |
788 | |
789 | if (stat->reg1 > 0x1f) { |
790 | ret = adin_read_mmd_stat_regs(phydev, stat, val: &val); |
791 | if (ret < 0) |
792 | return (u64)(~0); |
793 | } else { |
794 | ret = phy_read(phydev, regnum: stat->reg1); |
795 | if (ret < 0) |
796 | return (u64)(~0); |
797 | val = (ret & 0xffff); |
798 | } |
799 | |
800 | priv->stats[i] += val; |
801 | |
802 | return priv->stats[i]; |
803 | } |
804 | |
805 | static void adin_get_stats(struct phy_device *phydev, |
806 | struct ethtool_stats *stats, u64 *data) |
807 | { |
808 | int i, rc; |
809 | |
810 | /* latch copies of all the frame-checker counters */ |
811 | rc = phy_read(phydev, ADIN1300_RX_ERR_CNT); |
812 | if (rc < 0) |
813 | return; |
814 | |
815 | for (i = 0; i < ARRAY_SIZE(adin_hw_stats); i++) |
816 | data[i] = adin_get_stat(phydev, i); |
817 | } |
818 | |
819 | static int adin_probe(struct phy_device *phydev) |
820 | { |
821 | struct device *dev = &phydev->mdio.dev; |
822 | struct adin_priv *priv; |
823 | |
824 | priv = devm_kzalloc(dev, size: sizeof(*priv), GFP_KERNEL); |
825 | if (!priv) |
826 | return -ENOMEM; |
827 | |
828 | phydev->priv = priv; |
829 | |
830 | return 0; |
831 | } |
832 | |
833 | static int adin_cable_test_start(struct phy_device *phydev) |
834 | { |
835 | int ret; |
836 | |
837 | ret = phy_clear_bits(phydev, ADIN1300_PHY_CTRL3, ADIN1300_LINKING_EN); |
838 | if (ret < 0) |
839 | return ret; |
840 | |
841 | ret = phy_clear_bits(phydev, ADIN1300_PHY_CTRL1, ADIN1300_DIAG_CLK_EN); |
842 | if (ret < 0) |
843 | return ret; |
844 | |
845 | /* wait a bit for the clock to stabilize */ |
846 | msleep(msecs: 50); |
847 | |
848 | return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_CDIAG_RUN, |
849 | ADIN1300_CDIAG_RUN_EN); |
850 | } |
851 | |
852 | static int adin_cable_test_report_trans(int result) |
853 | { |
854 | int mask; |
855 | |
856 | if (result & ADIN1300_CDIAG_RSLT_GOOD) |
857 | return ETHTOOL_A_CABLE_RESULT_CODE_OK; |
858 | if (result & ADIN1300_CDIAG_RSLT_OPEN) |
859 | return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; |
860 | |
861 | /* short with other pairs */ |
862 | mask = ADIN1300_CDIAG_RSLT_XSHRT3 | |
863 | ADIN1300_CDIAG_RSLT_XSHRT2 | |
864 | ADIN1300_CDIAG_RSLT_XSHRT1; |
865 | if (result & mask) |
866 | return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT; |
867 | |
868 | if (result & ADIN1300_CDIAG_RSLT_SHRT) |
869 | return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; |
870 | |
871 | return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; |
872 | } |
873 | |
874 | static int adin_cable_test_report_pair(struct phy_device *phydev, |
875 | unsigned int pair) |
876 | { |
877 | int fault_rslt; |
878 | int ret; |
879 | |
880 | ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, |
881 | ADIN1300_CDIAG_DTLD_RSLTS(pair)); |
882 | if (ret < 0) |
883 | return ret; |
884 | |
885 | fault_rslt = adin_cable_test_report_trans(result: ret); |
886 | |
887 | ret = ethnl_cable_test_result(phydev, pair, result: fault_rslt); |
888 | if (ret < 0) |
889 | return ret; |
890 | |
891 | ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, |
892 | ADIN1300_CDIAG_FLT_DIST(pair)); |
893 | if (ret < 0) |
894 | return ret; |
895 | |
896 | switch (fault_rslt) { |
897 | case ETHTOOL_A_CABLE_RESULT_CODE_OPEN: |
898 | case ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT: |
899 | case ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT: |
900 | return ethnl_cable_test_fault_length(phydev, pair, cm: ret * 100); |
901 | default: |
902 | return 0; |
903 | } |
904 | } |
905 | |
906 | static int adin_cable_test_report(struct phy_device *phydev) |
907 | { |
908 | unsigned int pair; |
909 | int ret; |
910 | |
911 | for (pair = ETHTOOL_A_CABLE_PAIR_A; pair <= ETHTOOL_A_CABLE_PAIR_D; pair++) { |
912 | ret = adin_cable_test_report_pair(phydev, pair); |
913 | if (ret < 0) |
914 | return ret; |
915 | } |
916 | |
917 | return 0; |
918 | } |
919 | |
920 | static int adin_cable_test_get_status(struct phy_device *phydev, |
921 | bool *finished) |
922 | { |
923 | int ret; |
924 | |
925 | *finished = false; |
926 | |
927 | ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_CDIAG_RUN); |
928 | if (ret < 0) |
929 | return ret; |
930 | |
931 | if (ret & ADIN1300_CDIAG_RUN_EN) |
932 | return 0; |
933 | |
934 | *finished = true; |
935 | |
936 | return adin_cable_test_report(phydev); |
937 | } |
938 | |
939 | static struct phy_driver adin_driver[] = { |
940 | { |
941 | PHY_ID_MATCH_MODEL(PHY_ID_ADIN1200), |
942 | .name = "ADIN1200" , |
943 | .flags = PHY_POLL_CABLE_TEST, |
944 | .probe = adin_probe, |
945 | .config_init = adin_config_init, |
946 | .soft_reset = adin_soft_reset, |
947 | .config_aneg = adin_config_aneg, |
948 | .read_status = adin_read_status, |
949 | .get_tunable = adin_get_tunable, |
950 | .set_tunable = adin_set_tunable, |
951 | .config_intr = adin_phy_config_intr, |
952 | .handle_interrupt = adin_phy_handle_interrupt, |
953 | .get_sset_count = adin_get_sset_count, |
954 | .get_strings = adin_get_strings, |
955 | .get_stats = adin_get_stats, |
956 | .resume = genphy_resume, |
957 | .suspend = genphy_suspend, |
958 | .read_mmd = adin_read_mmd, |
959 | .write_mmd = adin_write_mmd, |
960 | .cable_test_start = adin_cable_test_start, |
961 | .cable_test_get_status = adin_cable_test_get_status, |
962 | }, |
963 | { |
964 | PHY_ID_MATCH_MODEL(PHY_ID_ADIN1300), |
965 | .name = "ADIN1300" , |
966 | .flags = PHY_POLL_CABLE_TEST, |
967 | .probe = adin_probe, |
968 | .config_init = adin_config_init, |
969 | .soft_reset = adin_soft_reset, |
970 | .config_aneg = adin_config_aneg, |
971 | .read_status = adin_read_status, |
972 | .get_tunable = adin_get_tunable, |
973 | .set_tunable = adin_set_tunable, |
974 | .config_intr = adin_phy_config_intr, |
975 | .handle_interrupt = adin_phy_handle_interrupt, |
976 | .get_sset_count = adin_get_sset_count, |
977 | .get_strings = adin_get_strings, |
978 | .get_stats = adin_get_stats, |
979 | .resume = genphy_resume, |
980 | .suspend = genphy_suspend, |
981 | .read_mmd = adin_read_mmd, |
982 | .write_mmd = adin_write_mmd, |
983 | .cable_test_start = adin_cable_test_start, |
984 | .cable_test_get_status = adin_cable_test_get_status, |
985 | }, |
986 | }; |
987 | |
988 | module_phy_driver(adin_driver); |
989 | |
990 | static struct mdio_device_id __maybe_unused adin_tbl[] = { |
991 | { PHY_ID_MATCH_MODEL(PHY_ID_ADIN1200) }, |
992 | { PHY_ID_MATCH_MODEL(PHY_ID_ADIN1300) }, |
993 | { } |
994 | }; |
995 | |
996 | MODULE_DEVICE_TABLE(mdio, adin_tbl); |
997 | MODULE_DESCRIPTION("Analog Devices Industrial Ethernet PHY driver" ); |
998 | MODULE_LICENSE("GPL" ); |
999 | |