1 | /* SPDX-License-Identifier: GPL-2.0-only |
2 | * |
3 | * Copyright (c) 2021, MediaTek Inc. |
4 | * Copyright (c) 2021-2022, Intel Corporation. |
5 | * |
6 | * Authors: |
7 | * Amir Hanania <amir.hanania@intel.com> |
8 | * Haijun Liu <haijun.liu@mediatek.com> |
9 | * Moises Veleta <moises.veleta@intel.com> |
10 | * Ricardo Martinez <ricardo.martinez@linux.intel.com> |
11 | * |
12 | * Contributors: |
13 | * Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com> |
14 | * Eliot Lee <eliot.lee@intel.com> |
15 | * Sreehari Kancharla <sreehari.kancharla@intel.com> |
16 | */ |
17 | |
18 | #ifndef __T7XX_HIF_DPMAIF_H__ |
19 | #define __T7XX_HIF_DPMAIF_H__ |
20 | |
21 | #include <linux/bitmap.h> |
22 | #include <linux/mm_types.h> |
23 | #include <linux/netdevice.h> |
24 | #include <linux/sched.h> |
25 | #include <linux/skbuff.h> |
26 | #include <linux/spinlock.h> |
27 | #include <linux/types.h> |
28 | #include <linux/wait.h> |
29 | #include <linux/workqueue.h> |
30 | |
31 | #include "t7xx_dpmaif.h" |
32 | #include "t7xx_pci.h" |
33 | #include "t7xx_state_monitor.h" |
34 | |
35 | /* SKB control buffer */ |
36 | struct t7xx_skb_cb { |
37 | u8 netif_idx; |
38 | u8 txq_number; |
39 | u8 rx_pkt_type; |
40 | }; |
41 | |
42 | #define T7XX_SKB_CB(__skb) ((struct t7xx_skb_cb *)(__skb)->cb) |
43 | |
44 | enum dpmaif_rdwr { |
45 | DPMAIF_READ, |
46 | DPMAIF_WRITE, |
47 | }; |
48 | |
49 | /* Structure of DL BAT */ |
50 | struct dpmaif_cur_rx_skb_info { |
51 | bool msg_pit_received; |
52 | struct sk_buff *cur_skb; |
53 | unsigned int cur_chn_idx; |
54 | unsigned int check_sum; |
55 | unsigned int pit_dp; |
56 | unsigned int pkt_type; |
57 | int err_payload; |
58 | }; |
59 | |
60 | struct dpmaif_bat { |
61 | unsigned int p_buffer_addr; |
62 | unsigned int buffer_addr_ext; |
63 | }; |
64 | |
65 | struct dpmaif_bat_skb { |
66 | struct sk_buff *skb; |
67 | dma_addr_t data_bus_addr; |
68 | unsigned int data_len; |
69 | }; |
70 | |
71 | struct dpmaif_bat_page { |
72 | struct page *page; |
73 | dma_addr_t data_bus_addr; |
74 | unsigned int offset; |
75 | unsigned int data_len; |
76 | }; |
77 | |
78 | enum bat_type { |
79 | BAT_TYPE_NORMAL, |
80 | BAT_TYPE_FRAG, |
81 | }; |
82 | |
83 | struct dpmaif_bat_request { |
84 | void *bat_base; |
85 | dma_addr_t bat_bus_addr; |
86 | unsigned int bat_size_cnt; |
87 | unsigned int bat_wr_idx; |
88 | unsigned int bat_release_rd_idx; |
89 | void *bat_skb; |
90 | unsigned int pkt_buf_sz; |
91 | unsigned long *bat_bitmap; |
92 | atomic_t refcnt; |
93 | spinlock_t mask_lock; /* Protects BAT mask */ |
94 | enum bat_type type; |
95 | }; |
96 | |
97 | struct dpmaif_rx_queue { |
98 | unsigned int index; |
99 | bool que_started; |
100 | unsigned int budget; |
101 | |
102 | void *pit_base; |
103 | dma_addr_t pit_bus_addr; |
104 | unsigned int pit_size_cnt; |
105 | |
106 | unsigned int pit_rd_idx; |
107 | unsigned int pit_wr_idx; |
108 | unsigned int pit_release_rd_idx; |
109 | |
110 | struct dpmaif_bat_request *bat_req; |
111 | struct dpmaif_bat_request *bat_frag; |
112 | |
113 | atomic_t rx_processing; |
114 | |
115 | struct dpmaif_ctrl *dpmaif_ctrl; |
116 | unsigned int expect_pit_seq; |
117 | unsigned int pit_remain_release_cnt; |
118 | struct dpmaif_cur_rx_skb_info rx_data_info; |
119 | struct napi_struct napi; |
120 | bool sleep_lock_pending; |
121 | }; |
122 | |
123 | struct dpmaif_tx_queue { |
124 | unsigned int index; |
125 | bool que_started; |
126 | atomic_t tx_budget; |
127 | void *drb_base; |
128 | dma_addr_t drb_bus_addr; |
129 | unsigned int drb_size_cnt; |
130 | unsigned int drb_wr_idx; |
131 | unsigned int drb_rd_idx; |
132 | unsigned int drb_release_rd_idx; |
133 | void *drb_skb_base; |
134 | wait_queue_head_t req_wq; |
135 | struct workqueue_struct *worker; |
136 | struct work_struct dpmaif_tx_work; |
137 | spinlock_t tx_lock; /* Protects txq DRB */ |
138 | atomic_t tx_processing; |
139 | |
140 | struct dpmaif_ctrl *dpmaif_ctrl; |
141 | struct sk_buff_head tx_skb_head; |
142 | }; |
143 | |
144 | struct dpmaif_isr_para { |
145 | struct dpmaif_ctrl *dpmaif_ctrl; |
146 | unsigned char pcie_int; |
147 | unsigned char dlq_id; |
148 | }; |
149 | |
150 | enum dpmaif_state { |
151 | DPMAIF_STATE_MIN, |
152 | DPMAIF_STATE_PWROFF, |
153 | DPMAIF_STATE_PWRON, |
154 | DPMAIF_STATE_EXCEPTION, |
155 | DPMAIF_STATE_MAX |
156 | }; |
157 | |
158 | enum dpmaif_txq_state { |
159 | DMPAIF_TXQ_STATE_IRQ, |
160 | DMPAIF_TXQ_STATE_FULL, |
161 | }; |
162 | |
163 | struct dpmaif_callbacks { |
164 | void (*state_notify)(struct t7xx_pci_dev *t7xx_dev, |
165 | enum dpmaif_txq_state state, int txq_number); |
166 | void (*recv_skb)(struct t7xx_ccmni_ctrl *ccmni_ctlb, struct sk_buff *skb, |
167 | struct napi_struct *napi); |
168 | }; |
169 | |
170 | struct dpmaif_ctrl { |
171 | struct device *dev; |
172 | struct t7xx_pci_dev *t7xx_dev; |
173 | struct md_pm_entity dpmaif_pm_entity; |
174 | enum dpmaif_state state; |
175 | bool dpmaif_sw_init_done; |
176 | struct dpmaif_hw_info hw_info; |
177 | struct dpmaif_tx_queue txq[DPMAIF_TXQ_NUM]; |
178 | struct dpmaif_rx_queue rxq[DPMAIF_RXQ_NUM]; |
179 | |
180 | unsigned char rxq_int_mapping[DPMAIF_RXQ_NUM]; |
181 | struct dpmaif_isr_para isr_para[DPMAIF_RXQ_NUM]; |
182 | |
183 | struct dpmaif_bat_request bat_req; |
184 | struct dpmaif_bat_request bat_frag; |
185 | struct workqueue_struct *bat_release_wq; |
186 | struct work_struct bat_release_work; |
187 | |
188 | wait_queue_head_t tx_wq; |
189 | struct task_struct *tx_thread; |
190 | |
191 | struct dpmaif_callbacks *callbacks; |
192 | }; |
193 | |
194 | struct dpmaif_ctrl *t7xx_dpmaif_hif_init(struct t7xx_pci_dev *t7xx_dev, |
195 | struct dpmaif_callbacks *callbacks); |
196 | void t7xx_dpmaif_hif_exit(struct dpmaif_ctrl *dpmaif_ctrl); |
197 | int t7xx_dpmaif_md_state_callback(struct dpmaif_ctrl *dpmaif_ctrl, enum md_state state); |
198 | unsigned int t7xx_ring_buf_get_next_wr_idx(unsigned int buf_len, unsigned int buf_idx); |
199 | unsigned int t7xx_ring_buf_rd_wr_count(unsigned int total_cnt, unsigned int rd_idx, |
200 | unsigned int wr_idx, enum dpmaif_rdwr); |
201 | |
202 | #endif /* __T7XX_HIF_DPMAIF_H__ */ |
203 | |