1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* |
3 | * PCIe host controller driver for Xilinx AXI PCIe Bridge |
4 | * |
5 | * Copyright (c) 2012 - 2014 Xilinx, Inc. |
6 | * |
7 | * Based on the Tegra PCIe driver |
8 | * |
9 | * Bits taken from Synopsys DesignWare Host controller driver and |
10 | * ARM PCI Host generic driver. |
11 | */ |
12 | |
13 | #include <linux/interrupt.h> |
14 | #include <linux/irq.h> |
15 | #include <linux/irqdomain.h> |
16 | #include <linux/kernel.h> |
17 | #include <linux/init.h> |
18 | #include <linux/msi.h> |
19 | #include <linux/of_address.h> |
20 | #include <linux/of_pci.h> |
21 | #include <linux/of_platform.h> |
22 | #include <linux/of_irq.h> |
23 | #include <linux/pci.h> |
24 | #include <linux/pci-ecam.h> |
25 | #include <linux/platform_device.h> |
26 | |
27 | #include "../pci.h" |
28 | |
29 | /* Register definitions */ |
30 | #define XILINX_PCIE_REG_BIR 0x00000130 |
31 | #define XILINX_PCIE_REG_IDR 0x00000138 |
32 | #define XILINX_PCIE_REG_IMR 0x0000013c |
33 | #define XILINX_PCIE_REG_PSCR 0x00000144 |
34 | #define XILINX_PCIE_REG_RPSC 0x00000148 |
35 | #define XILINX_PCIE_REG_MSIBASE1 0x0000014c |
36 | #define XILINX_PCIE_REG_MSIBASE2 0x00000150 |
37 | #define XILINX_PCIE_REG_RPEFR 0x00000154 |
38 | #define XILINX_PCIE_REG_RPIFR1 0x00000158 |
39 | #define XILINX_PCIE_REG_RPIFR2 0x0000015c |
40 | |
41 | /* Interrupt registers definitions */ |
42 | #define XILINX_PCIE_INTR_LINK_DOWN BIT(0) |
43 | #define XILINX_PCIE_INTR_ECRC_ERR BIT(1) |
44 | #define XILINX_PCIE_INTR_STR_ERR BIT(2) |
45 | #define XILINX_PCIE_INTR_HOT_RESET BIT(3) |
46 | #define XILINX_PCIE_INTR_CFG_TIMEOUT BIT(8) |
47 | #define XILINX_PCIE_INTR_CORRECTABLE BIT(9) |
48 | #define XILINX_PCIE_INTR_NONFATAL BIT(10) |
49 | #define XILINX_PCIE_INTR_FATAL BIT(11) |
50 | #define XILINX_PCIE_INTR_INTX BIT(16) |
51 | #define XILINX_PCIE_INTR_MSI BIT(17) |
52 | #define XILINX_PCIE_INTR_SLV_UNSUPP BIT(20) |
53 | #define XILINX_PCIE_INTR_SLV_UNEXP BIT(21) |
54 | #define XILINX_PCIE_INTR_SLV_COMPL BIT(22) |
55 | #define XILINX_PCIE_INTR_SLV_ERRP BIT(23) |
56 | #define XILINX_PCIE_INTR_SLV_CMPABT BIT(24) |
57 | #define XILINX_PCIE_INTR_SLV_ILLBUR BIT(25) |
58 | #define XILINX_PCIE_INTR_MST_DECERR BIT(26) |
59 | #define XILINX_PCIE_INTR_MST_SLVERR BIT(27) |
60 | #define XILINX_PCIE_INTR_MST_ERRP BIT(28) |
61 | #define XILINX_PCIE_IMR_ALL_MASK 0x1FF30FED |
62 | #define XILINX_PCIE_IMR_ENABLE_MASK 0x1FF30F0D |
63 | #define XILINX_PCIE_IDR_ALL_MASK 0xFFFFFFFF |
64 | |
65 | /* Root Port Error FIFO Read Register definitions */ |
66 | #define XILINX_PCIE_RPEFR_ERR_VALID BIT(18) |
67 | #define XILINX_PCIE_RPEFR_REQ_ID GENMASK(15, 0) |
68 | #define XILINX_PCIE_RPEFR_ALL_MASK 0xFFFFFFFF |
69 | |
70 | /* Root Port Interrupt FIFO Read Register 1 definitions */ |
71 | #define XILINX_PCIE_RPIFR1_INTR_VALID BIT(31) |
72 | #define XILINX_PCIE_RPIFR1_MSI_INTR BIT(30) |
73 | #define XILINX_PCIE_RPIFR1_INTR_MASK GENMASK(28, 27) |
74 | #define XILINX_PCIE_RPIFR1_ALL_MASK 0xFFFFFFFF |
75 | #define XILINX_PCIE_RPIFR1_INTR_SHIFT 27 |
76 | |
77 | /* Bridge Info Register definitions */ |
78 | #define XILINX_PCIE_BIR_ECAM_SZ_MASK GENMASK(18, 16) |
79 | #define XILINX_PCIE_BIR_ECAM_SZ_SHIFT 16 |
80 | |
81 | /* Root Port Interrupt FIFO Read Register 2 definitions */ |
82 | #define XILINX_PCIE_RPIFR2_MSG_DATA GENMASK(15, 0) |
83 | |
84 | /* Root Port Status/control Register definitions */ |
85 | #define XILINX_PCIE_REG_RPSC_BEN BIT(0) |
86 | |
87 | /* Phy Status/Control Register definitions */ |
88 | #define XILINX_PCIE_REG_PSCR_LNKUP BIT(11) |
89 | |
90 | /* Number of MSI IRQs */ |
91 | #define XILINX_NUM_MSI_IRQS 128 |
92 | |
93 | /** |
94 | * struct xilinx_pcie - PCIe port information |
95 | * @dev: Device pointer |
96 | * @reg_base: IO Mapped Register Base |
97 | * @msi_map: Bitmap of allocated MSIs |
98 | * @map_lock: Mutex protecting the MSI allocation |
99 | * @msi_domain: MSI IRQ domain pointer |
100 | * @leg_domain: Legacy IRQ domain pointer |
101 | * @resources: Bus Resources |
102 | */ |
103 | struct xilinx_pcie { |
104 | struct device *dev; |
105 | void __iomem *reg_base; |
106 | unsigned long msi_map[BITS_TO_LONGS(XILINX_NUM_MSI_IRQS)]; |
107 | struct mutex map_lock; |
108 | struct irq_domain *msi_domain; |
109 | struct irq_domain *leg_domain; |
110 | struct list_head resources; |
111 | }; |
112 | |
113 | static inline u32 pcie_read(struct xilinx_pcie *pcie, u32 reg) |
114 | { |
115 | return readl(addr: pcie->reg_base + reg); |
116 | } |
117 | |
118 | static inline void pcie_write(struct xilinx_pcie *pcie, u32 val, u32 reg) |
119 | { |
120 | writel(val, addr: pcie->reg_base + reg); |
121 | } |
122 | |
123 | static inline bool xilinx_pcie_link_up(struct xilinx_pcie *pcie) |
124 | { |
125 | return (pcie_read(pcie, XILINX_PCIE_REG_PSCR) & |
126 | XILINX_PCIE_REG_PSCR_LNKUP) ? 1 : 0; |
127 | } |
128 | |
129 | /** |
130 | * xilinx_pcie_clear_err_interrupts - Clear Error Interrupts |
131 | * @pcie: PCIe port information |
132 | */ |
133 | static void xilinx_pcie_clear_err_interrupts(struct xilinx_pcie *pcie) |
134 | { |
135 | struct device *dev = pcie->dev; |
136 | unsigned long val = pcie_read(pcie, XILINX_PCIE_REG_RPEFR); |
137 | |
138 | if (val & XILINX_PCIE_RPEFR_ERR_VALID) { |
139 | dev_dbg(dev, "Requester ID %lu\n" , |
140 | val & XILINX_PCIE_RPEFR_REQ_ID); |
141 | pcie_write(pcie, XILINX_PCIE_RPEFR_ALL_MASK, |
142 | XILINX_PCIE_REG_RPEFR); |
143 | } |
144 | } |
145 | |
146 | /** |
147 | * xilinx_pcie_valid_device - Check if a valid device is present on bus |
148 | * @bus: PCI Bus structure |
149 | * @devfn: device/function |
150 | * |
151 | * Return: 'true' on success and 'false' if invalid device is found |
152 | */ |
153 | static bool xilinx_pcie_valid_device(struct pci_bus *bus, unsigned int devfn) |
154 | { |
155 | struct xilinx_pcie *pcie = bus->sysdata; |
156 | |
157 | /* Check if link is up when trying to access downstream pcie ports */ |
158 | if (!pci_is_root_bus(pbus: bus)) { |
159 | if (!xilinx_pcie_link_up(pcie)) |
160 | return false; |
161 | } else if (devfn > 0) { |
162 | /* Only one device down on each root port */ |
163 | return false; |
164 | } |
165 | return true; |
166 | } |
167 | |
168 | /** |
169 | * xilinx_pcie_map_bus - Get configuration base |
170 | * @bus: PCI Bus structure |
171 | * @devfn: Device/function |
172 | * @where: Offset from base |
173 | * |
174 | * Return: Base address of the configuration space needed to be |
175 | * accessed. |
176 | */ |
177 | static void __iomem *xilinx_pcie_map_bus(struct pci_bus *bus, |
178 | unsigned int devfn, int where) |
179 | { |
180 | struct xilinx_pcie *pcie = bus->sysdata; |
181 | |
182 | if (!xilinx_pcie_valid_device(bus, devfn)) |
183 | return NULL; |
184 | |
185 | return pcie->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); |
186 | } |
187 | |
188 | /* PCIe operations */ |
189 | static struct pci_ops xilinx_pcie_ops = { |
190 | .map_bus = xilinx_pcie_map_bus, |
191 | .read = pci_generic_config_read, |
192 | .write = pci_generic_config_write, |
193 | }; |
194 | |
195 | /* MSI functions */ |
196 | |
197 | static void xilinx_msi_top_irq_ack(struct irq_data *d) |
198 | { |
199 | /* |
200 | * xilinx_pcie_intr_handler() will have performed the Ack. |
201 | * Eventually, this should be fixed and the Ack be moved in |
202 | * the respective callbacks for INTx and MSI. |
203 | */ |
204 | } |
205 | |
206 | static struct irq_chip xilinx_msi_top_chip = { |
207 | .name = "PCIe MSI" , |
208 | .irq_ack = xilinx_msi_top_irq_ack, |
209 | }; |
210 | |
211 | static int xilinx_msi_set_affinity(struct irq_data *d, const struct cpumask *mask, bool force) |
212 | { |
213 | return -EINVAL; |
214 | } |
215 | |
216 | static void xilinx_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) |
217 | { |
218 | struct xilinx_pcie *pcie = irq_data_get_irq_chip_data(d: data); |
219 | phys_addr_t pa = ALIGN_DOWN(virt_to_phys(pcie), SZ_4K); |
220 | |
221 | msg->address_lo = lower_32_bits(pa); |
222 | msg->address_hi = upper_32_bits(pa); |
223 | msg->data = data->hwirq; |
224 | } |
225 | |
226 | static struct irq_chip xilinx_msi_bottom_chip = { |
227 | .name = "Xilinx MSI" , |
228 | .irq_set_affinity = xilinx_msi_set_affinity, |
229 | .irq_compose_msi_msg = xilinx_compose_msi_msg, |
230 | }; |
231 | |
232 | static int xilinx_msi_domain_alloc(struct irq_domain *domain, unsigned int virq, |
233 | unsigned int nr_irqs, void *args) |
234 | { |
235 | struct xilinx_pcie *pcie = domain->host_data; |
236 | int hwirq, i; |
237 | |
238 | mutex_lock(&pcie->map_lock); |
239 | |
240 | hwirq = bitmap_find_free_region(bitmap: pcie->msi_map, XILINX_NUM_MSI_IRQS, order_base_2(nr_irqs)); |
241 | |
242 | mutex_unlock(lock: &pcie->map_lock); |
243 | |
244 | if (hwirq < 0) |
245 | return -ENOSPC; |
246 | |
247 | for (i = 0; i < nr_irqs; i++) |
248 | irq_domain_set_info(domain, virq: virq + i, hwirq: hwirq + i, |
249 | chip: &xilinx_msi_bottom_chip, chip_data: domain->host_data, |
250 | handler: handle_edge_irq, NULL, NULL); |
251 | |
252 | return 0; |
253 | } |
254 | |
255 | static void xilinx_msi_domain_free(struct irq_domain *domain, unsigned int virq, |
256 | unsigned int nr_irqs) |
257 | { |
258 | struct irq_data *d = irq_domain_get_irq_data(domain, virq); |
259 | struct xilinx_pcie *pcie = domain->host_data; |
260 | |
261 | mutex_lock(&pcie->map_lock); |
262 | |
263 | bitmap_release_region(bitmap: pcie->msi_map, pos: d->hwirq, order_base_2(nr_irqs)); |
264 | |
265 | mutex_unlock(lock: &pcie->map_lock); |
266 | } |
267 | |
268 | static const struct irq_domain_ops xilinx_msi_domain_ops = { |
269 | .alloc = xilinx_msi_domain_alloc, |
270 | .free = xilinx_msi_domain_free, |
271 | }; |
272 | |
273 | static struct msi_domain_info xilinx_msi_info = { |
274 | .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS), |
275 | .chip = &xilinx_msi_top_chip, |
276 | }; |
277 | |
278 | static int xilinx_allocate_msi_domains(struct xilinx_pcie *pcie) |
279 | { |
280 | struct fwnode_handle *fwnode = dev_fwnode(pcie->dev); |
281 | struct irq_domain *parent; |
282 | |
283 | parent = irq_domain_create_linear(fwnode, XILINX_NUM_MSI_IRQS, |
284 | ops: &xilinx_msi_domain_ops, host_data: pcie); |
285 | if (!parent) { |
286 | dev_err(pcie->dev, "failed to create IRQ domain\n" ); |
287 | return -ENOMEM; |
288 | } |
289 | irq_domain_update_bus_token(domain: parent, bus_token: DOMAIN_BUS_NEXUS); |
290 | |
291 | pcie->msi_domain = pci_msi_create_irq_domain(fwnode, info: &xilinx_msi_info, parent); |
292 | if (!pcie->msi_domain) { |
293 | dev_err(pcie->dev, "failed to create MSI domain\n" ); |
294 | irq_domain_remove(host: parent); |
295 | return -ENOMEM; |
296 | } |
297 | |
298 | return 0; |
299 | } |
300 | |
301 | static void xilinx_free_msi_domains(struct xilinx_pcie *pcie) |
302 | { |
303 | struct irq_domain *parent = pcie->msi_domain->parent; |
304 | |
305 | irq_domain_remove(host: pcie->msi_domain); |
306 | irq_domain_remove(host: parent); |
307 | } |
308 | |
309 | /* INTx Functions */ |
310 | |
311 | /** |
312 | * xilinx_pcie_intx_map - Set the handler for the INTx and mark IRQ as valid |
313 | * @domain: IRQ domain |
314 | * @irq: Virtual IRQ number |
315 | * @hwirq: HW interrupt number |
316 | * |
317 | * Return: Always returns 0. |
318 | */ |
319 | static int xilinx_pcie_intx_map(struct irq_domain *domain, unsigned int irq, |
320 | irq_hw_number_t hwirq) |
321 | { |
322 | irq_set_chip_and_handler(irq, chip: &dummy_irq_chip, handle: handle_simple_irq); |
323 | irq_set_chip_data(irq, data: domain->host_data); |
324 | |
325 | return 0; |
326 | } |
327 | |
328 | /* INTx IRQ Domain operations */ |
329 | static const struct irq_domain_ops intx_domain_ops = { |
330 | .map = xilinx_pcie_intx_map, |
331 | .xlate = pci_irqd_intx_xlate, |
332 | }; |
333 | |
334 | /* PCIe HW Functions */ |
335 | |
336 | /** |
337 | * xilinx_pcie_intr_handler - Interrupt Service Handler |
338 | * @irq: IRQ number |
339 | * @data: PCIe port information |
340 | * |
341 | * Return: IRQ_HANDLED on success and IRQ_NONE on failure |
342 | */ |
343 | static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data) |
344 | { |
345 | struct xilinx_pcie *pcie = (struct xilinx_pcie *)data; |
346 | struct device *dev = pcie->dev; |
347 | u32 val, mask, status; |
348 | |
349 | /* Read interrupt decode and mask registers */ |
350 | val = pcie_read(pcie, XILINX_PCIE_REG_IDR); |
351 | mask = pcie_read(pcie, XILINX_PCIE_REG_IMR); |
352 | |
353 | status = val & mask; |
354 | if (!status) |
355 | return IRQ_NONE; |
356 | |
357 | if (status & XILINX_PCIE_INTR_LINK_DOWN) |
358 | dev_warn(dev, "Link Down\n" ); |
359 | |
360 | if (status & XILINX_PCIE_INTR_ECRC_ERR) |
361 | dev_warn(dev, "ECRC failed\n" ); |
362 | |
363 | if (status & XILINX_PCIE_INTR_STR_ERR) |
364 | dev_warn(dev, "Streaming error\n" ); |
365 | |
366 | if (status & XILINX_PCIE_INTR_HOT_RESET) |
367 | dev_info(dev, "Hot reset\n" ); |
368 | |
369 | if (status & XILINX_PCIE_INTR_CFG_TIMEOUT) |
370 | dev_warn(dev, "ECAM access timeout\n" ); |
371 | |
372 | if (status & XILINX_PCIE_INTR_CORRECTABLE) { |
373 | dev_warn(dev, "Correctable error message\n" ); |
374 | xilinx_pcie_clear_err_interrupts(pcie); |
375 | } |
376 | |
377 | if (status & XILINX_PCIE_INTR_NONFATAL) { |
378 | dev_warn(dev, "Non fatal error message\n" ); |
379 | xilinx_pcie_clear_err_interrupts(pcie); |
380 | } |
381 | |
382 | if (status & XILINX_PCIE_INTR_FATAL) { |
383 | dev_warn(dev, "Fatal error message\n" ); |
384 | xilinx_pcie_clear_err_interrupts(pcie); |
385 | } |
386 | |
387 | if (status & (XILINX_PCIE_INTR_INTX | XILINX_PCIE_INTR_MSI)) { |
388 | struct irq_domain *domain; |
389 | |
390 | val = pcie_read(pcie, XILINX_PCIE_REG_RPIFR1); |
391 | |
392 | /* Check whether interrupt valid */ |
393 | if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) { |
394 | dev_warn(dev, "RP Intr FIFO1 read error\n" ); |
395 | goto error; |
396 | } |
397 | |
398 | /* Decode the IRQ number */ |
399 | if (val & XILINX_PCIE_RPIFR1_MSI_INTR) { |
400 | val = pcie_read(pcie, XILINX_PCIE_REG_RPIFR2) & |
401 | XILINX_PCIE_RPIFR2_MSG_DATA; |
402 | domain = pcie->msi_domain->parent; |
403 | } else { |
404 | val = (val & XILINX_PCIE_RPIFR1_INTR_MASK) >> |
405 | XILINX_PCIE_RPIFR1_INTR_SHIFT; |
406 | domain = pcie->leg_domain; |
407 | } |
408 | |
409 | /* Clear interrupt FIFO register 1 */ |
410 | pcie_write(pcie, XILINX_PCIE_RPIFR1_ALL_MASK, |
411 | XILINX_PCIE_REG_RPIFR1); |
412 | |
413 | generic_handle_domain_irq(domain, hwirq: val); |
414 | } |
415 | |
416 | if (status & XILINX_PCIE_INTR_SLV_UNSUPP) |
417 | dev_warn(dev, "Slave unsupported request\n" ); |
418 | |
419 | if (status & XILINX_PCIE_INTR_SLV_UNEXP) |
420 | dev_warn(dev, "Slave unexpected completion\n" ); |
421 | |
422 | if (status & XILINX_PCIE_INTR_SLV_COMPL) |
423 | dev_warn(dev, "Slave completion timeout\n" ); |
424 | |
425 | if (status & XILINX_PCIE_INTR_SLV_ERRP) |
426 | dev_warn(dev, "Slave Error Poison\n" ); |
427 | |
428 | if (status & XILINX_PCIE_INTR_SLV_CMPABT) |
429 | dev_warn(dev, "Slave Completer Abort\n" ); |
430 | |
431 | if (status & XILINX_PCIE_INTR_SLV_ILLBUR) |
432 | dev_warn(dev, "Slave Illegal Burst\n" ); |
433 | |
434 | if (status & XILINX_PCIE_INTR_MST_DECERR) |
435 | dev_warn(dev, "Master decode error\n" ); |
436 | |
437 | if (status & XILINX_PCIE_INTR_MST_SLVERR) |
438 | dev_warn(dev, "Master slave error\n" ); |
439 | |
440 | if (status & XILINX_PCIE_INTR_MST_ERRP) |
441 | dev_warn(dev, "Master error poison\n" ); |
442 | |
443 | error: |
444 | /* Clear the Interrupt Decode register */ |
445 | pcie_write(pcie, val: status, XILINX_PCIE_REG_IDR); |
446 | |
447 | return IRQ_HANDLED; |
448 | } |
449 | |
450 | /** |
451 | * xilinx_pcie_init_irq_domain - Initialize IRQ domain |
452 | * @pcie: PCIe port information |
453 | * |
454 | * Return: '0' on success and error value on failure |
455 | */ |
456 | static int xilinx_pcie_init_irq_domain(struct xilinx_pcie *pcie) |
457 | { |
458 | struct device *dev = pcie->dev; |
459 | struct device_node *pcie_intc_node; |
460 | int ret; |
461 | |
462 | /* Setup INTx */ |
463 | pcie_intc_node = of_get_next_child(node: dev->of_node, NULL); |
464 | if (!pcie_intc_node) { |
465 | dev_err(dev, "No PCIe Intc node found\n" ); |
466 | return -ENODEV; |
467 | } |
468 | |
469 | pcie->leg_domain = irq_domain_add_linear(of_node: pcie_intc_node, PCI_NUM_INTX, |
470 | ops: &intx_domain_ops, |
471 | host_data: pcie); |
472 | of_node_put(node: pcie_intc_node); |
473 | if (!pcie->leg_domain) { |
474 | dev_err(dev, "Failed to get a INTx IRQ domain\n" ); |
475 | return -ENODEV; |
476 | } |
477 | |
478 | /* Setup MSI */ |
479 | if (IS_ENABLED(CONFIG_PCI_MSI)) { |
480 | phys_addr_t pa = ALIGN_DOWN(virt_to_phys(pcie), SZ_4K); |
481 | |
482 | ret = xilinx_allocate_msi_domains(pcie); |
483 | if (ret) |
484 | return ret; |
485 | |
486 | pcie_write(pcie, upper_32_bits(pa), XILINX_PCIE_REG_MSIBASE1); |
487 | pcie_write(pcie, lower_32_bits(pa), XILINX_PCIE_REG_MSIBASE2); |
488 | } |
489 | |
490 | return 0; |
491 | } |
492 | |
493 | /** |
494 | * xilinx_pcie_init_port - Initialize hardware |
495 | * @pcie: PCIe port information |
496 | */ |
497 | static void xilinx_pcie_init_port(struct xilinx_pcie *pcie) |
498 | { |
499 | struct device *dev = pcie->dev; |
500 | |
501 | if (xilinx_pcie_link_up(pcie)) |
502 | dev_info(dev, "PCIe Link is UP\n" ); |
503 | else |
504 | dev_info(dev, "PCIe Link is DOWN\n" ); |
505 | |
506 | /* Disable all interrupts */ |
507 | pcie_write(pcie, val: ~XILINX_PCIE_IDR_ALL_MASK, |
508 | XILINX_PCIE_REG_IMR); |
509 | |
510 | /* Clear pending interrupts */ |
511 | pcie_write(pcie, val: pcie_read(pcie, XILINX_PCIE_REG_IDR) & |
512 | XILINX_PCIE_IMR_ALL_MASK, |
513 | XILINX_PCIE_REG_IDR); |
514 | |
515 | /* Enable all interrupts we handle */ |
516 | pcie_write(pcie, XILINX_PCIE_IMR_ENABLE_MASK, XILINX_PCIE_REG_IMR); |
517 | |
518 | /* Enable the Bridge enable bit */ |
519 | pcie_write(pcie, val: pcie_read(pcie, XILINX_PCIE_REG_RPSC) | |
520 | XILINX_PCIE_REG_RPSC_BEN, |
521 | XILINX_PCIE_REG_RPSC); |
522 | } |
523 | |
524 | /** |
525 | * xilinx_pcie_parse_dt - Parse Device tree |
526 | * @pcie: PCIe port information |
527 | * |
528 | * Return: '0' on success and error value on failure |
529 | */ |
530 | static int xilinx_pcie_parse_dt(struct xilinx_pcie *pcie) |
531 | { |
532 | struct device *dev = pcie->dev; |
533 | struct device_node *node = dev->of_node; |
534 | struct resource regs; |
535 | unsigned int irq; |
536 | int err; |
537 | |
538 | err = of_address_to_resource(dev: node, index: 0, r: ®s); |
539 | if (err) { |
540 | dev_err(dev, "missing \"reg\" property\n" ); |
541 | return err; |
542 | } |
543 | |
544 | pcie->reg_base = devm_pci_remap_cfg_resource(dev, res: ®s); |
545 | if (IS_ERR(ptr: pcie->reg_base)) |
546 | return PTR_ERR(ptr: pcie->reg_base); |
547 | |
548 | irq = irq_of_parse_and_map(node, index: 0); |
549 | err = devm_request_irq(dev, irq, handler: xilinx_pcie_intr_handler, |
550 | IRQF_SHARED | IRQF_NO_THREAD, |
551 | devname: "xilinx-pcie" , dev_id: pcie); |
552 | if (err) { |
553 | dev_err(dev, "unable to request irq %d\n" , irq); |
554 | return err; |
555 | } |
556 | |
557 | return 0; |
558 | } |
559 | |
560 | /** |
561 | * xilinx_pcie_probe - Probe function |
562 | * @pdev: Platform device pointer |
563 | * |
564 | * Return: '0' on success and error value on failure |
565 | */ |
566 | static int xilinx_pcie_probe(struct platform_device *pdev) |
567 | { |
568 | struct device *dev = &pdev->dev; |
569 | struct xilinx_pcie *pcie; |
570 | struct pci_host_bridge *bridge; |
571 | int err; |
572 | |
573 | if (!dev->of_node) |
574 | return -ENODEV; |
575 | |
576 | bridge = devm_pci_alloc_host_bridge(dev, priv: sizeof(*pcie)); |
577 | if (!bridge) |
578 | return -ENODEV; |
579 | |
580 | pcie = pci_host_bridge_priv(bridge); |
581 | mutex_init(&pcie->map_lock); |
582 | pcie->dev = dev; |
583 | |
584 | err = xilinx_pcie_parse_dt(pcie); |
585 | if (err) { |
586 | dev_err(dev, "Parsing DT failed\n" ); |
587 | return err; |
588 | } |
589 | |
590 | xilinx_pcie_init_port(pcie); |
591 | |
592 | err = xilinx_pcie_init_irq_domain(pcie); |
593 | if (err) { |
594 | dev_err(dev, "Failed creating IRQ Domain\n" ); |
595 | return err; |
596 | } |
597 | |
598 | bridge->sysdata = pcie; |
599 | bridge->ops = &xilinx_pcie_ops; |
600 | |
601 | err = pci_host_probe(bridge); |
602 | if (err) |
603 | xilinx_free_msi_domains(pcie); |
604 | |
605 | return err; |
606 | } |
607 | |
608 | static const struct of_device_id xilinx_pcie_of_match[] = { |
609 | { .compatible = "xlnx,axi-pcie-host-1.00.a" , }, |
610 | {} |
611 | }; |
612 | |
613 | static struct platform_driver xilinx_pcie_driver = { |
614 | .driver = { |
615 | .name = "xilinx-pcie" , |
616 | .of_match_table = xilinx_pcie_of_match, |
617 | .suppress_bind_attrs = true, |
618 | }, |
619 | .probe = xilinx_pcie_probe, |
620 | }; |
621 | builtin_platform_driver(xilinx_pcie_driver); |
622 | |