1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Copyright (c) 2023, Linaro Limited |
4 | */ |
5 | |
6 | #include <linux/bitfield.h> |
7 | #include <linux/clk.h> |
8 | #include <linux/delay.h> |
9 | #include <linux/iopoll.h> |
10 | #include <linux/mod_devicetable.h> |
11 | #include <linux/phy/phy.h> |
12 | #include <linux/platform_device.h> |
13 | #include <linux/regulator/consumer.h> |
14 | #include <linux/reset.h> |
15 | |
16 | #define USB_PHY_UTMI_CTRL0 (0x3c) |
17 | #define SLEEPM BIT(0) |
18 | #define OPMODE_MASK GENMASK(4, 3) |
19 | #define OPMODE_NONDRIVING BIT(3) |
20 | |
21 | #define USB_PHY_UTMI_CTRL5 (0x50) |
22 | #define POR BIT(1) |
23 | |
24 | #define USB_PHY_HS_PHY_CTRL_COMMON0 (0x54) |
25 | #define PHY_ENABLE BIT(0) |
26 | #define SIDDQ_SEL BIT(1) |
27 | #define SIDDQ BIT(2) |
28 | #define RETENABLEN BIT(3) |
29 | #define FSEL_MASK GENMASK(6, 4) |
30 | #define FSEL_19_2_MHZ_VAL (0x0) |
31 | #define FSEL_38_4_MHZ_VAL (0x4) |
32 | |
33 | #define USB_PHY_CFG_CTRL_1 (0x58) |
34 | #define PHY_CFG_PLL_CPBIAS_CNTRL_MASK GENMASK(7, 1) |
35 | |
36 | #define USB_PHY_CFG_CTRL_2 (0x5c) |
37 | #define PHY_CFG_PLL_FB_DIV_7_0_MASK GENMASK(7, 0) |
38 | #define DIV_7_0_19_2_MHZ_VAL (0x90) |
39 | #define DIV_7_0_38_4_MHZ_VAL (0xc8) |
40 | |
41 | #define USB_PHY_CFG_CTRL_3 (0x60) |
42 | #define PHY_CFG_PLL_FB_DIV_11_8_MASK GENMASK(3, 0) |
43 | #define DIV_11_8_19_2_MHZ_VAL (0x1) |
44 | #define DIV_11_8_38_4_MHZ_VAL (0x0) |
45 | |
46 | #define PHY_CFG_PLL_REF_DIV GENMASK(7, 4) |
47 | #define PLL_REF_DIV_VAL (0x0) |
48 | |
49 | #define USB_PHY_HS_PHY_CTRL2 (0x64) |
50 | #define VBUSVLDEXT0 BIT(0) |
51 | #define USB2_SUSPEND_N BIT(2) |
52 | #define USB2_SUSPEND_N_SEL BIT(3) |
53 | #define VBUS_DET_EXT_SEL BIT(4) |
54 | |
55 | #define USB_PHY_CFG_CTRL_4 (0x68) |
56 | #define PHY_CFG_PLL_GMP_CNTRL_MASK GENMASK(1, 0) |
57 | #define PHY_CFG_PLL_INT_CNTRL_MASK GENMASK(7, 2) |
58 | |
59 | #define USB_PHY_CFG_CTRL_5 (0x6c) |
60 | #define PHY_CFG_PLL_PROP_CNTRL_MASK GENMASK(4, 0) |
61 | #define PHY_CFG_PLL_VREF_TUNE_MASK GENMASK(7, 6) |
62 | |
63 | #define USB_PHY_CFG_CTRL_6 (0x70) |
64 | #define PHY_CFG_PLL_VCO_CNTRL_MASK GENMASK(2, 0) |
65 | |
66 | #define USB_PHY_CFG_CTRL_7 (0x74) |
67 | |
68 | #define USB_PHY_CFG_CTRL_8 (0x78) |
69 | #define PHY_CFG_TX_FSLS_VREF_TUNE_MASK GENMASK(1, 0) |
70 | #define PHY_CFG_TX_FSLS_VREG_BYPASS BIT(2) |
71 | #define PHY_CFG_TX_HS_VREF_TUNE_MASK GENMASK(5, 3) |
72 | #define PHY_CFG_TX_HS_XV_TUNE_MASK GENMASK(7, 6) |
73 | |
74 | #define USB_PHY_CFG_CTRL_9 (0x7c) |
75 | #define PHY_CFG_TX_PREEMP_TUNE_MASK GENMASK(2, 0) |
76 | #define PHY_CFG_TX_RES_TUNE_MASK GENMASK(4, 3) |
77 | #define PHY_CFG_TX_RISE_TUNE_MASK GENMASK(6, 5) |
78 | #define PHY_CFG_RCAL_BYPASS BIT(7) |
79 | |
80 | #define USB_PHY_CFG_CTRL_10 (0x80) |
81 | |
82 | #define USB_PHY_CFG0 (0x94) |
83 | #define DATAPATH_CTRL_OVERRIDE_EN BIT(0) |
84 | #define CMN_CTRL_OVERRIDE_EN BIT(1) |
85 | |
86 | #define UTMI_PHY_CMN_CTRL0 (0x98) |
87 | #define TESTBURNIN BIT(6) |
88 | |
89 | #define USB_PHY_FSEL_SEL (0xb8) |
90 | #define FSEL_SEL BIT(0) |
91 | |
92 | #define USB_PHY_APB_ACCESS_CMD (0x130) |
93 | #define RW_ACCESS BIT(0) |
94 | #define APB_START_CMD BIT(1) |
95 | #define APB_LOGIC_RESET BIT(2) |
96 | |
97 | #define USB_PHY_APB_ACCESS_STATUS (0x134) |
98 | #define ACCESS_DONE BIT(0) |
99 | #define TIMED_OUT BIT(1) |
100 | #define ACCESS_ERROR BIT(2) |
101 | #define ACCESS_IN_PROGRESS BIT(3) |
102 | |
103 | #define USB_PHY_APB_ADDRESS (0x138) |
104 | #define APB_REG_ADDR_MASK GENMASK(7, 0) |
105 | |
106 | #define USB_PHY_APB_WRDATA_LSB (0x13c) |
107 | #define APB_REG_WRDATA_7_0_MASK GENMASK(3, 0) |
108 | |
109 | #define USB_PHY_APB_WRDATA_MSB (0x140) |
110 | #define APB_REG_WRDATA_15_8_MASK GENMASK(7, 4) |
111 | |
112 | #define USB_PHY_APB_RDDATA_LSB (0x144) |
113 | #define APB_REG_RDDATA_7_0_MASK GENMASK(3, 0) |
114 | |
115 | #define USB_PHY_APB_RDDATA_MSB (0x148) |
116 | #define APB_REG_RDDATA_15_8_MASK GENMASK(7, 4) |
117 | |
118 | static const char * const eusb2_hsphy_vreg_names[] = { |
119 | "vdd" , "vdda12" , |
120 | }; |
121 | |
122 | #define EUSB2_NUM_VREGS ARRAY_SIZE(eusb2_hsphy_vreg_names) |
123 | |
124 | struct qcom_snps_eusb2_hsphy { |
125 | struct phy *phy; |
126 | void __iomem *base; |
127 | |
128 | struct clk *ref_clk; |
129 | struct reset_control *phy_reset; |
130 | |
131 | struct regulator_bulk_data vregs[EUSB2_NUM_VREGS]; |
132 | |
133 | enum phy_mode mode; |
134 | |
135 | struct phy *repeater; |
136 | }; |
137 | |
138 | static int qcom_snps_eusb2_hsphy_set_mode(struct phy *p, enum phy_mode mode, int submode) |
139 | { |
140 | struct qcom_snps_eusb2_hsphy *phy = phy_get_drvdata(phy: p); |
141 | |
142 | phy->mode = mode; |
143 | |
144 | return phy_set_mode_ext(phy: phy->repeater, mode, submode); |
145 | } |
146 | |
147 | static void qcom_snps_eusb2_hsphy_write_mask(void __iomem *base, u32 offset, |
148 | u32 mask, u32 val) |
149 | { |
150 | u32 reg; |
151 | |
152 | reg = readl_relaxed(base + offset); |
153 | reg &= ~mask; |
154 | reg |= val & mask; |
155 | writel_relaxed(reg, base + offset); |
156 | |
157 | /* Ensure above write is completed */ |
158 | readl_relaxed(base + offset); |
159 | } |
160 | |
161 | static void qcom_eusb2_default_parameters(struct qcom_snps_eusb2_hsphy *phy) |
162 | { |
163 | /* default parameters: tx pre-emphasis */ |
164 | qcom_snps_eusb2_hsphy_write_mask(base: phy->base, USB_PHY_CFG_CTRL_9, |
165 | PHY_CFG_TX_PREEMP_TUNE_MASK, |
166 | FIELD_PREP(PHY_CFG_TX_PREEMP_TUNE_MASK, 0)); |
167 | |
168 | /* tx rise/fall time */ |
169 | qcom_snps_eusb2_hsphy_write_mask(base: phy->base, USB_PHY_CFG_CTRL_9, |
170 | PHY_CFG_TX_RISE_TUNE_MASK, |
171 | FIELD_PREP(PHY_CFG_TX_RISE_TUNE_MASK, 0x2)); |
172 | |
173 | /* source impedance adjustment */ |
174 | qcom_snps_eusb2_hsphy_write_mask(base: phy->base, USB_PHY_CFG_CTRL_9, |
175 | PHY_CFG_TX_RES_TUNE_MASK, |
176 | FIELD_PREP(PHY_CFG_TX_RES_TUNE_MASK, 0x1)); |
177 | |
178 | /* dc voltage level adjustement */ |
179 | qcom_snps_eusb2_hsphy_write_mask(base: phy->base, USB_PHY_CFG_CTRL_8, |
180 | PHY_CFG_TX_HS_VREF_TUNE_MASK, |
181 | FIELD_PREP(PHY_CFG_TX_HS_VREF_TUNE_MASK, 0x3)); |
182 | |
183 | /* transmitter HS crossover adjustement */ |
184 | qcom_snps_eusb2_hsphy_write_mask(base: phy->base, USB_PHY_CFG_CTRL_8, |
185 | PHY_CFG_TX_HS_XV_TUNE_MASK, |
186 | FIELD_PREP(PHY_CFG_TX_HS_XV_TUNE_MASK, 0x0)); |
187 | } |
188 | |
189 | static int qcom_eusb2_ref_clk_init(struct qcom_snps_eusb2_hsphy *phy) |
190 | { |
191 | unsigned long ref_clk_freq = clk_get_rate(clk: phy->ref_clk); |
192 | |
193 | switch (ref_clk_freq) { |
194 | case 19200000: |
195 | qcom_snps_eusb2_hsphy_write_mask(base: phy->base, USB_PHY_HS_PHY_CTRL_COMMON0, |
196 | FSEL_MASK, |
197 | FIELD_PREP(FSEL_MASK, FSEL_19_2_MHZ_VAL)); |
198 | |
199 | qcom_snps_eusb2_hsphy_write_mask(base: phy->base, USB_PHY_CFG_CTRL_2, |
200 | PHY_CFG_PLL_FB_DIV_7_0_MASK, |
201 | DIV_7_0_19_2_MHZ_VAL); |
202 | |
203 | qcom_snps_eusb2_hsphy_write_mask(base: phy->base, USB_PHY_CFG_CTRL_3, |
204 | PHY_CFG_PLL_FB_DIV_11_8_MASK, |
205 | DIV_11_8_19_2_MHZ_VAL); |
206 | break; |
207 | |
208 | case 38400000: |
209 | qcom_snps_eusb2_hsphy_write_mask(base: phy->base, USB_PHY_HS_PHY_CTRL_COMMON0, |
210 | FSEL_MASK, |
211 | FIELD_PREP(FSEL_MASK, FSEL_38_4_MHZ_VAL)); |
212 | |
213 | qcom_snps_eusb2_hsphy_write_mask(base: phy->base, USB_PHY_CFG_CTRL_2, |
214 | PHY_CFG_PLL_FB_DIV_7_0_MASK, |
215 | DIV_7_0_38_4_MHZ_VAL); |
216 | |
217 | qcom_snps_eusb2_hsphy_write_mask(base: phy->base, USB_PHY_CFG_CTRL_3, |
218 | PHY_CFG_PLL_FB_DIV_11_8_MASK, |
219 | DIV_11_8_38_4_MHZ_VAL); |
220 | break; |
221 | |
222 | default: |
223 | dev_err(&phy->phy->dev, "unsupported ref_clk_freq:%lu\n" , ref_clk_freq); |
224 | return -EINVAL; |
225 | } |
226 | |
227 | qcom_snps_eusb2_hsphy_write_mask(base: phy->base, USB_PHY_CFG_CTRL_3, |
228 | PHY_CFG_PLL_REF_DIV, PLL_REF_DIV_VAL); |
229 | |
230 | return 0; |
231 | } |
232 | |
233 | static int qcom_snps_eusb2_hsphy_init(struct phy *p) |
234 | { |
235 | struct qcom_snps_eusb2_hsphy *phy = phy_get_drvdata(phy: p); |
236 | int ret; |
237 | |
238 | ret = regulator_bulk_enable(ARRAY_SIZE(phy->vregs), consumers: phy->vregs); |
239 | if (ret) |
240 | return ret; |
241 | |
242 | ret = phy_init(phy: phy->repeater); |
243 | if (ret) { |
244 | dev_err(&p->dev, "repeater init failed. %d\n" , ret); |
245 | goto disable_vreg; |
246 | } |
247 | |
248 | ret = clk_prepare_enable(clk: phy->ref_clk); |
249 | if (ret) { |
250 | dev_err(&p->dev, "failed to enable ref clock, %d\n" , ret); |
251 | goto disable_vreg; |
252 | } |
253 | |
254 | ret = reset_control_assert(rstc: phy->phy_reset); |
255 | if (ret) { |
256 | dev_err(&p->dev, "failed to assert phy_reset, %d\n" , ret); |
257 | goto disable_ref_clk; |
258 | } |
259 | |
260 | usleep_range(min: 100, max: 150); |
261 | |
262 | ret = reset_control_deassert(rstc: phy->phy_reset); |
263 | if (ret) { |
264 | dev_err(&p->dev, "failed to de-assert phy_reset, %d\n" , ret); |
265 | goto disable_ref_clk; |
266 | } |
267 | |
268 | qcom_snps_eusb2_hsphy_write_mask(base: phy->base, USB_PHY_CFG0, |
269 | CMN_CTRL_OVERRIDE_EN, CMN_CTRL_OVERRIDE_EN); |
270 | |
271 | qcom_snps_eusb2_hsphy_write_mask(base: phy->base, USB_PHY_UTMI_CTRL5, POR, POR); |
272 | |
273 | qcom_snps_eusb2_hsphy_write_mask(base: phy->base, USB_PHY_HS_PHY_CTRL_COMMON0, |
274 | PHY_ENABLE | RETENABLEN, PHY_ENABLE | RETENABLEN); |
275 | |
276 | qcom_snps_eusb2_hsphy_write_mask(base: phy->base, USB_PHY_APB_ACCESS_CMD, |
277 | APB_LOGIC_RESET, APB_LOGIC_RESET); |
278 | |
279 | qcom_snps_eusb2_hsphy_write_mask(base: phy->base, UTMI_PHY_CMN_CTRL0, TESTBURNIN, val: 0); |
280 | |
281 | qcom_snps_eusb2_hsphy_write_mask(base: phy->base, USB_PHY_FSEL_SEL, |
282 | FSEL_SEL, FSEL_SEL); |
283 | |
284 | /* update ref_clk related registers */ |
285 | ret = qcom_eusb2_ref_clk_init(phy); |
286 | if (ret) |
287 | goto disable_ref_clk; |
288 | |
289 | qcom_snps_eusb2_hsphy_write_mask(base: phy->base, USB_PHY_CFG_CTRL_1, |
290 | PHY_CFG_PLL_CPBIAS_CNTRL_MASK, |
291 | FIELD_PREP(PHY_CFG_PLL_CPBIAS_CNTRL_MASK, 0x1)); |
292 | |
293 | qcom_snps_eusb2_hsphy_write_mask(base: phy->base, USB_PHY_CFG_CTRL_4, |
294 | PHY_CFG_PLL_INT_CNTRL_MASK, |
295 | FIELD_PREP(PHY_CFG_PLL_INT_CNTRL_MASK, 0x8)); |
296 | |
297 | qcom_snps_eusb2_hsphy_write_mask(base: phy->base, USB_PHY_CFG_CTRL_4, |
298 | PHY_CFG_PLL_GMP_CNTRL_MASK, |
299 | FIELD_PREP(PHY_CFG_PLL_GMP_CNTRL_MASK, 0x1)); |
300 | |
301 | qcom_snps_eusb2_hsphy_write_mask(base: phy->base, USB_PHY_CFG_CTRL_5, |
302 | PHY_CFG_PLL_PROP_CNTRL_MASK, |
303 | FIELD_PREP(PHY_CFG_PLL_PROP_CNTRL_MASK, 0x10)); |
304 | |
305 | qcom_snps_eusb2_hsphy_write_mask(base: phy->base, USB_PHY_CFG_CTRL_6, |
306 | PHY_CFG_PLL_VCO_CNTRL_MASK, |
307 | FIELD_PREP(PHY_CFG_PLL_VCO_CNTRL_MASK, 0x0)); |
308 | |
309 | qcom_snps_eusb2_hsphy_write_mask(base: phy->base, USB_PHY_CFG_CTRL_5, |
310 | PHY_CFG_PLL_VREF_TUNE_MASK, |
311 | FIELD_PREP(PHY_CFG_PLL_VREF_TUNE_MASK, 0x1)); |
312 | |
313 | qcom_snps_eusb2_hsphy_write_mask(base: phy->base, USB_PHY_HS_PHY_CTRL2, |
314 | VBUS_DET_EXT_SEL, VBUS_DET_EXT_SEL); |
315 | |
316 | /* set default parameters */ |
317 | qcom_eusb2_default_parameters(phy); |
318 | |
319 | qcom_snps_eusb2_hsphy_write_mask(base: phy->base, USB_PHY_HS_PHY_CTRL2, |
320 | USB2_SUSPEND_N_SEL | USB2_SUSPEND_N, |
321 | USB2_SUSPEND_N_SEL | USB2_SUSPEND_N); |
322 | |
323 | qcom_snps_eusb2_hsphy_write_mask(base: phy->base, USB_PHY_UTMI_CTRL0, SLEEPM, SLEEPM); |
324 | |
325 | qcom_snps_eusb2_hsphy_write_mask(base: phy->base, USB_PHY_HS_PHY_CTRL_COMMON0, |
326 | SIDDQ_SEL, SIDDQ_SEL); |
327 | |
328 | qcom_snps_eusb2_hsphy_write_mask(base: phy->base, USB_PHY_HS_PHY_CTRL_COMMON0, |
329 | SIDDQ, val: 0); |
330 | |
331 | qcom_snps_eusb2_hsphy_write_mask(base: phy->base, USB_PHY_UTMI_CTRL5, POR, val: 0); |
332 | |
333 | qcom_snps_eusb2_hsphy_write_mask(base: phy->base, USB_PHY_HS_PHY_CTRL2, |
334 | USB2_SUSPEND_N_SEL, val: 0); |
335 | |
336 | return 0; |
337 | |
338 | disable_ref_clk: |
339 | clk_disable_unprepare(clk: phy->ref_clk); |
340 | |
341 | disable_vreg: |
342 | regulator_bulk_disable(ARRAY_SIZE(phy->vregs), consumers: phy->vregs); |
343 | |
344 | return ret; |
345 | } |
346 | |
347 | static int qcom_snps_eusb2_hsphy_exit(struct phy *p) |
348 | { |
349 | struct qcom_snps_eusb2_hsphy *phy = phy_get_drvdata(phy: p); |
350 | |
351 | clk_disable_unprepare(clk: phy->ref_clk); |
352 | |
353 | regulator_bulk_disable(ARRAY_SIZE(phy->vregs), consumers: phy->vregs); |
354 | |
355 | phy_exit(phy: phy->repeater); |
356 | |
357 | return 0; |
358 | } |
359 | |
360 | static const struct phy_ops qcom_snps_eusb2_hsphy_ops = { |
361 | .init = qcom_snps_eusb2_hsphy_init, |
362 | .exit = qcom_snps_eusb2_hsphy_exit, |
363 | .set_mode = qcom_snps_eusb2_hsphy_set_mode, |
364 | .owner = THIS_MODULE, |
365 | }; |
366 | |
367 | static int qcom_snps_eusb2_hsphy_probe(struct platform_device *pdev) |
368 | { |
369 | struct device *dev = &pdev->dev; |
370 | struct device_node *np = dev->of_node; |
371 | struct qcom_snps_eusb2_hsphy *phy; |
372 | struct phy_provider *phy_provider; |
373 | struct phy *generic_phy; |
374 | int ret, i; |
375 | int num; |
376 | |
377 | phy = devm_kzalloc(dev, size: sizeof(*phy), GFP_KERNEL); |
378 | if (!phy) |
379 | return -ENOMEM; |
380 | |
381 | phy->base = devm_platform_ioremap_resource(pdev, index: 0); |
382 | if (IS_ERR(ptr: phy->base)) |
383 | return PTR_ERR(ptr: phy->base); |
384 | |
385 | phy->phy_reset = devm_reset_control_get_exclusive(dev, NULL); |
386 | if (IS_ERR(ptr: phy->phy_reset)) |
387 | return PTR_ERR(ptr: phy->phy_reset); |
388 | |
389 | phy->ref_clk = devm_clk_get(dev, id: "ref" ); |
390 | if (IS_ERR(ptr: phy->ref_clk)) |
391 | return dev_err_probe(dev, err: PTR_ERR(ptr: phy->ref_clk), |
392 | fmt: "failed to get ref clk\n" ); |
393 | |
394 | num = ARRAY_SIZE(phy->vregs); |
395 | for (i = 0; i < num; i++) |
396 | phy->vregs[i].supply = eusb2_hsphy_vreg_names[i]; |
397 | |
398 | ret = devm_regulator_bulk_get(dev, num_consumers: num, consumers: phy->vregs); |
399 | if (ret) |
400 | return dev_err_probe(dev, err: ret, |
401 | fmt: "failed to get regulator supplies\n" ); |
402 | |
403 | phy->repeater = devm_of_phy_get_by_index(dev, np, index: 0); |
404 | if (IS_ERR(ptr: phy->repeater)) |
405 | return dev_err_probe(dev, err: PTR_ERR(ptr: phy->repeater), |
406 | fmt: "failed to get repeater\n" ); |
407 | |
408 | generic_phy = devm_phy_create(dev, NULL, ops: &qcom_snps_eusb2_hsphy_ops); |
409 | if (IS_ERR(ptr: generic_phy)) { |
410 | dev_err(dev, "failed to create phy %d\n" , ret); |
411 | return PTR_ERR(ptr: generic_phy); |
412 | } |
413 | |
414 | dev_set_drvdata(dev, data: phy); |
415 | phy_set_drvdata(phy: generic_phy, data: phy); |
416 | |
417 | phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); |
418 | if (IS_ERR(ptr: phy_provider)) |
419 | return PTR_ERR(ptr: phy_provider); |
420 | |
421 | dev_info(dev, "Registered Qcom-eUSB2 phy\n" ); |
422 | |
423 | return 0; |
424 | } |
425 | |
426 | static const struct of_device_id qcom_snps_eusb2_hsphy_of_match_table[] = { |
427 | { .compatible = "qcom,sm8550-snps-eusb2-phy" , }, |
428 | { }, |
429 | }; |
430 | MODULE_DEVICE_TABLE(of, qcom_snps_eusb2_hsphy_of_match_table); |
431 | |
432 | static struct platform_driver qcom_snps_eusb2_hsphy_driver = { |
433 | .probe = qcom_snps_eusb2_hsphy_probe, |
434 | .driver = { |
435 | .name = "qcom-snps-eusb2-hsphy" , |
436 | .of_match_table = qcom_snps_eusb2_hsphy_of_match_table, |
437 | }, |
438 | }; |
439 | |
440 | module_platform_driver(qcom_snps_eusb2_hsphy_driver); |
441 | MODULE_DESCRIPTION("Qualcomm SNPS eUSB2 HS PHY driver" ); |
442 | MODULE_LICENSE("GPL" ); |
443 | |