1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * Pin controller and GPIO driver for Amlogic Meson SoCs |
4 | * |
5 | * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> |
6 | */ |
7 | |
8 | #include <linux/gpio/driver.h> |
9 | #include <linux/pinctrl/pinctrl.h> |
10 | #include <linux/platform_device.h> |
11 | #include <linux/regmap.h> |
12 | #include <linux/types.h> |
13 | #include <linux/module.h> |
14 | |
15 | struct fwnode_handle; |
16 | |
17 | struct meson_pinctrl; |
18 | |
19 | /** |
20 | * struct meson_pmx_group - a pinmux group |
21 | * |
22 | * @name: group name |
23 | * @pins: pins in the group |
24 | * @num_pins: number of pins in the group |
25 | * @is_gpio: whether the group is a single GPIO group |
26 | * @reg: register offset for the group in the domain mux registers |
27 | * @bit bit index enabling the group |
28 | * @domain: index of the domain this group belongs to |
29 | */ |
30 | struct meson_pmx_group { |
31 | const char *name; |
32 | const unsigned int *pins; |
33 | unsigned int num_pins; |
34 | const void *data; |
35 | }; |
36 | |
37 | /** |
38 | * struct meson_pmx_func - a pinmux function |
39 | * |
40 | * @name: function name |
41 | * @groups: groups in the function |
42 | * @num_groups: number of groups in the function |
43 | */ |
44 | struct meson_pmx_func { |
45 | const char *name; |
46 | const char * const *groups; |
47 | unsigned int num_groups; |
48 | }; |
49 | |
50 | /** |
51 | * struct meson_reg_desc - a register descriptor |
52 | * |
53 | * @reg: register offset in the regmap |
54 | * @bit: bit index in register |
55 | * |
56 | * The structure describes the information needed to control pull, |
57 | * pull-enable, direction, etc. for a single pin |
58 | */ |
59 | struct meson_reg_desc { |
60 | unsigned int reg; |
61 | unsigned int bit; |
62 | }; |
63 | |
64 | /** |
65 | * enum meson_reg_type - type of registers encoded in @meson_reg_desc |
66 | */ |
67 | enum meson_reg_type { |
68 | MESON_REG_PULLEN, |
69 | MESON_REG_PULL, |
70 | MESON_REG_DIR, |
71 | MESON_REG_OUT, |
72 | MESON_REG_IN, |
73 | MESON_REG_DS, |
74 | MESON_NUM_REG, |
75 | }; |
76 | |
77 | /** |
78 | * enum meson_pinconf_drv - value of drive-strength supported |
79 | */ |
80 | enum meson_pinconf_drv { |
81 | MESON_PINCONF_DRV_500UA, |
82 | MESON_PINCONF_DRV_2500UA, |
83 | MESON_PINCONF_DRV_3000UA, |
84 | MESON_PINCONF_DRV_4000UA, |
85 | }; |
86 | |
87 | /** |
88 | * struct meson bank |
89 | * |
90 | * @name: bank name |
91 | * @first: first pin of the bank |
92 | * @last: last pin of the bank |
93 | * @irq: hwirq base number of the bank |
94 | * @regs: array of register descriptors |
95 | * |
96 | * A bank represents a set of pins controlled by a contiguous set of |
97 | * bits in the domain registers. The structure specifies which bits in |
98 | * the regmap control the different functionalities. Each member of |
99 | * the @regs array refers to the first pin of the bank. |
100 | */ |
101 | struct meson_bank { |
102 | const char *name; |
103 | unsigned int first; |
104 | unsigned int last; |
105 | int irq_first; |
106 | int irq_last; |
107 | struct meson_reg_desc regs[MESON_NUM_REG]; |
108 | }; |
109 | |
110 | struct meson_pinctrl_data { |
111 | const char *name; |
112 | const struct pinctrl_pin_desc *pins; |
113 | struct meson_pmx_group *groups; |
114 | struct meson_pmx_func *funcs; |
115 | unsigned int num_pins; |
116 | unsigned int num_groups; |
117 | unsigned int num_funcs; |
118 | struct meson_bank *banks; |
119 | unsigned int num_banks; |
120 | const struct pinmux_ops *pmx_ops; |
121 | void *pmx_data; |
122 | int (*parse_dt)(struct meson_pinctrl *pc); |
123 | }; |
124 | |
125 | struct meson_pinctrl { |
126 | struct device *dev; |
127 | struct pinctrl_dev *pcdev; |
128 | struct pinctrl_desc desc; |
129 | struct meson_pinctrl_data *data; |
130 | struct regmap *reg_mux; |
131 | struct regmap *reg_pullen; |
132 | struct regmap *reg_pull; |
133 | struct regmap *reg_gpio; |
134 | struct regmap *reg_ds; |
135 | struct gpio_chip chip; |
136 | struct fwnode_handle *fwnode; |
137 | }; |
138 | |
139 | #define FUNCTION(fn) \ |
140 | { \ |
141 | .name = #fn, \ |
142 | .groups = fn ## _groups, \ |
143 | .num_groups = ARRAY_SIZE(fn ## _groups), \ |
144 | } |
145 | |
146 | #define BANK_DS(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib, \ |
147 | dsr, dsb) \ |
148 | { \ |
149 | .name = n, \ |
150 | .first = f, \ |
151 | .last = l, \ |
152 | .irq_first = fi, \ |
153 | .irq_last = li, \ |
154 | .regs = { \ |
155 | [MESON_REG_PULLEN] = { per, peb }, \ |
156 | [MESON_REG_PULL] = { pr, pb }, \ |
157 | [MESON_REG_DIR] = { dr, db }, \ |
158 | [MESON_REG_OUT] = { or, ob }, \ |
159 | [MESON_REG_IN] = { ir, ib }, \ |
160 | [MESON_REG_DS] = { dsr, dsb }, \ |
161 | }, \ |
162 | } |
163 | |
164 | #define BANK(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib) \ |
165 | BANK_DS(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib, 0, 0) |
166 | |
167 | #define MESON_PIN(x) PINCTRL_PIN(x, #x) |
168 | |
169 | /* Common pmx functions */ |
170 | int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev); |
171 | const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev, |
172 | unsigned selector); |
173 | int meson_pmx_get_groups(struct pinctrl_dev *pcdev, |
174 | unsigned selector, |
175 | const char * const **groups, |
176 | unsigned * const num_groups); |
177 | |
178 | /* Common probe function */ |
179 | int meson_pinctrl_probe(struct platform_device *pdev); |
180 | /* Common ao groups extra dt parse function for SoCs before g12a */ |
181 | int (struct meson_pinctrl *pc); |
182 | /* Common extra dt parse function for SoCs like A1 */ |
183 | int (struct meson_pinctrl *pc); |
184 | |