1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * NXP S32G pinctrl driver |
4 | * |
5 | * Copyright 2015-2016 Freescale Semiconductor, Inc. |
6 | * Copyright 2017-2018, 2020-2022 NXP |
7 | * Copyright (C) 2022 SUSE LLC |
8 | */ |
9 | |
10 | #include <linux/err.h> |
11 | #include <linux/init.h> |
12 | #include <linux/io.h> |
13 | #include <linux/module.h> |
14 | #include <linux/of.h> |
15 | #include <linux/platform_device.h> |
16 | #include <linux/pinctrl/pinctrl.h> |
17 | |
18 | #include "pinctrl-s32.h" |
19 | |
20 | enum s32_pins { |
21 | S32G_MSCR_PA_00 = 0, |
22 | S32G_MSCR_PA_01 = 1, |
23 | S32G_MSCR_PA_02 = 2, |
24 | S32G_MSCR_PA_03 = 3, |
25 | S32G_MSCR_PA_04 = 4, |
26 | S32G_MSCR_PA_05 = 5, |
27 | S32G_MSCR_PA_06 = 6, |
28 | S32G_MSCR_PA_07 = 7, |
29 | S32G_MSCR_PA_08 = 8, |
30 | S32G_MSCR_PA_09 = 9, |
31 | S32G_MSCR_PA_10 = 10, |
32 | S32G_MSCR_PA_11 = 11, |
33 | S32G_MSCR_PA_12 = 12, |
34 | S32G_MSCR_PA_13 = 13, |
35 | S32G_MSCR_PA_14 = 14, |
36 | S32G_MSCR_PA_15 = 15, |
37 | S32G_MSCR_PB_00 = 16, |
38 | S32G_MSCR_PB_01 = 17, |
39 | S32G_MSCR_PB_02 = 18, |
40 | S32G_MSCR_PB_03 = 19, |
41 | S32G_MSCR_PB_04 = 20, |
42 | S32G_MSCR_PB_05 = 21, |
43 | S32G_MSCR_PB_06 = 22, |
44 | S32G_MSCR_PB_07 = 23, |
45 | S32G_MSCR_PB_08 = 24, |
46 | S32G_MSCR_PB_09 = 25, |
47 | S32G_MSCR_PB_10 = 26, |
48 | S32G_MSCR_PB_11 = 27, |
49 | S32G_MSCR_PB_12 = 28, |
50 | S32G_MSCR_PB_13 = 29, |
51 | S32G_MSCR_PB_14 = 30, |
52 | S32G_MSCR_PB_15 = 31, |
53 | S32G_MSCR_PC_00 = 32, |
54 | S32G_MSCR_PC_01 = 33, |
55 | S32G_MSCR_PC_02 = 34, |
56 | S32G_MSCR_PC_03 = 35, |
57 | S32G_MSCR_PC_04 = 36, |
58 | S32G_MSCR_PC_05 = 37, |
59 | S32G_MSCR_PC_06 = 38, |
60 | S32G_MSCR_PC_07 = 39, |
61 | S32G_MSCR_PC_08 = 40, |
62 | S32G_MSCR_PC_09 = 41, |
63 | S32G_MSCR_PC_10 = 42, |
64 | S32G_MSCR_PC_11 = 43, |
65 | S32G_MSCR_PC_12 = 44, |
66 | S32G_MSCR_PC_13 = 45, |
67 | S32G_MSCR_PC_14 = 46, |
68 | S32G_MSCR_PC_15 = 47, |
69 | S32G_MSCR_PD_00 = 48, |
70 | S32G_MSCR_PD_01 = 49, |
71 | S32G_MSCR_PD_02 = 50, |
72 | S32G_MSCR_PD_03 = 51, |
73 | S32G_MSCR_PD_04 = 52, |
74 | S32G_MSCR_PD_05 = 53, |
75 | S32G_MSCR_PD_06 = 54, |
76 | S32G_MSCR_PD_07 = 55, |
77 | S32G_MSCR_PD_08 = 56, |
78 | S32G_MSCR_PD_09 = 57, |
79 | S32G_MSCR_PD_10 = 58, |
80 | S32G_MSCR_PD_11 = 59, |
81 | S32G_MSCR_PD_12 = 60, |
82 | S32G_MSCR_PD_13 = 61, |
83 | S32G_MSCR_PD_14 = 62, |
84 | S32G_MSCR_PD_15 = 63, |
85 | S32G_MSCR_PE_00 = 64, |
86 | S32G_MSCR_PE_01 = 65, |
87 | S32G_MSCR_PE_02 = 66, |
88 | S32G_MSCR_PE_03 = 67, |
89 | S32G_MSCR_PE_04 = 68, |
90 | S32G_MSCR_PE_05 = 69, |
91 | S32G_MSCR_PE_06 = 70, |
92 | S32G_MSCR_PE_07 = 71, |
93 | S32G_MSCR_PE_08 = 72, |
94 | S32G_MSCR_PE_09 = 73, |
95 | S32G_MSCR_PE_10 = 74, |
96 | S32G_MSCR_PE_11 = 75, |
97 | S32G_MSCR_PE_12 = 76, |
98 | S32G_MSCR_PE_13 = 77, |
99 | S32G_MSCR_PE_14 = 78, |
100 | S32G_MSCR_PE_15 = 79, |
101 | S32G_MSCR_PF_00 = 80, |
102 | S32G_MSCR_PF_01 = 81, |
103 | S32G_MSCR_PF_02 = 82, |
104 | S32G_MSCR_PF_03 = 83, |
105 | S32G_MSCR_PF_04 = 84, |
106 | S32G_MSCR_PF_05 = 85, |
107 | S32G_MSCR_PF_06 = 86, |
108 | S32G_MSCR_PF_07 = 87, |
109 | S32G_MSCR_PF_08 = 88, |
110 | S32G_MSCR_PF_09 = 89, |
111 | S32G_MSCR_PF_10 = 90, |
112 | S32G_MSCR_PF_11 = 91, |
113 | S32G_MSCR_PF_12 = 92, |
114 | S32G_MSCR_PF_13 = 93, |
115 | S32G_MSCR_PF_14 = 94, |
116 | S32G_MSCR_PF_15 = 95, |
117 | S32G_MSCR_PG_00 = 96, |
118 | S32G_MSCR_PG_01 = 97, |
119 | S32G_MSCR_PG_02 = 98, |
120 | S32G_MSCR_PG_03 = 99, |
121 | S32G_MSCR_PG_04 = 100, |
122 | S32G_MSCR_PG_05 = 101, |
123 | S32G_MSCR_PH_00 = 112, |
124 | S32G_MSCR_PH_01 = 113, |
125 | S32G_MSCR_PH_02 = 114, |
126 | S32G_MSCR_PH_03 = 115, |
127 | S32G_MSCR_PH_04 = 116, |
128 | S32G_MSCR_PH_05 = 117, |
129 | S32G_MSCR_PH_06 = 118, |
130 | S32G_MSCR_PH_07 = 119, |
131 | S32G_MSCR_PH_08 = 120, |
132 | S32G_MSCR_PH_09 = 121, |
133 | S32G_MSCR_PH_10 = 122, |
134 | S32G_MSCR_PJ_00 = 144, |
135 | S32G_MSCR_PJ_01 = 145, |
136 | S32G_MSCR_PJ_02 = 146, |
137 | S32G_MSCR_PJ_03 = 147, |
138 | S32G_MSCR_PJ_04 = 148, |
139 | S32G_MSCR_PJ_05 = 149, |
140 | S32G_MSCR_PJ_06 = 150, |
141 | S32G_MSCR_PJ_07 = 151, |
142 | S32G_MSCR_PJ_08 = 152, |
143 | S32G_MSCR_PJ_09 = 153, |
144 | S32G_MSCR_PJ_10 = 154, |
145 | S32G_MSCR_PJ_11 = 155, |
146 | S32G_MSCR_PJ_12 = 156, |
147 | S32G_MSCR_PJ_13 = 157, |
148 | S32G_MSCR_PJ_14 = 158, |
149 | S32G_MSCR_PJ_15 = 159, |
150 | S32G_MSCR_PK_00 = 160, |
151 | S32G_MSCR_PK_01 = 161, |
152 | S32G_MSCR_PK_02 = 162, |
153 | S32G_MSCR_PK_03 = 163, |
154 | S32G_MSCR_PK_04 = 164, |
155 | S32G_MSCR_PK_05 = 165, |
156 | S32G_MSCR_PK_06 = 166, |
157 | S32G_MSCR_PK_07 = 167, |
158 | S32G_MSCR_PK_08 = 168, |
159 | S32G_MSCR_PK_09 = 169, |
160 | S32G_MSCR_PK_10 = 170, |
161 | S32G_MSCR_PK_11 = 171, |
162 | S32G_MSCR_PK_12 = 172, |
163 | S32G_MSCR_PK_13 = 173, |
164 | S32G_MSCR_PK_14 = 174, |
165 | S32G_MSCR_PK_15 = 175, |
166 | S32G_MSCR_PL_00 = 176, |
167 | S32G_MSCR_PL_01 = 177, |
168 | S32G_MSCR_PL_02 = 178, |
169 | S32G_MSCR_PL_03 = 179, |
170 | S32G_MSCR_PL_04 = 180, |
171 | S32G_MSCR_PL_05 = 181, |
172 | S32G_MSCR_PL_06 = 182, |
173 | S32G_MSCR_PL_07 = 183, |
174 | S32G_MSCR_PL_08 = 184, |
175 | S32G_MSCR_PL_09 = 185, |
176 | S32G_MSCR_PL_10 = 186, |
177 | S32G_MSCR_PL_11 = 187, |
178 | S32G_MSCR_PL_12 = 188, |
179 | S32G_MSCR_PL_13 = 189, |
180 | S32G_MSCR_PL_14 = 190, |
181 | |
182 | S32G_IMCR_QSPI_A_DATA0 = 540, |
183 | S32G_IMCR_QSPI_A_DATA1 = 541, |
184 | S32G_IMCR_QSPI_A_DATA2 = 542, |
185 | S32G_IMCR_QSPI_A_DATA3 = 543, |
186 | S32G_IMCR_QSPI_A_DATA4 = 544, |
187 | S32G_IMCR_QSPI_A_DATA5 = 545, |
188 | S32G_IMCR_QSPI_A_DATA6 = 546, |
189 | S32G_IMCR_QSPI_A_DATA7 = 547, |
190 | S32G_IMCR_QSPI_DQS_A = 548, |
191 | S32G_IMCR_QSPI_B_DATA0 = 552, |
192 | S32G_IMCR_QSPI_B_DATA1 = 554, |
193 | S32G_IMCR_QSPI_B_DATA2 = 551, |
194 | S32G_IMCR_QSPI_B_DATA3 = 553, |
195 | S32G_IMCR_QSPI_B_DATA4 = 557, |
196 | S32G_IMCR_QSPI_B_DATA5 = 550, |
197 | S32G_IMCR_QSPI_B_DATA6 = 556, |
198 | S32G_IMCR_QSPI_B_DATA7 = 555, |
199 | S32G_IMCR_QSPI_DQS_B = 558, |
200 | S32G_IMCR_BOOT_BOOTMOD0 = 560, |
201 | S32G_IMCR_BOOT_BOOTMOD1 = 561, |
202 | S32G_IMCR_I2C0_SCL = 566, |
203 | S32G_IMCR_I2C0_SDA = 565, |
204 | S32G_IMCR_LIN0_RX = 512, |
205 | S32G_IMCR_USDHC_CMD = 515, |
206 | S32G_IMCR_USDHC_DAT0 = 516, |
207 | S32G_IMCR_USDHC_DAT1 = 517, |
208 | S32G_IMCR_USDHC_DAT2 = 520, |
209 | S32G_IMCR_USDHC_DAT3 = 521, |
210 | S32G_IMCR_USDHC_DAT4 = 522, |
211 | S32G_IMCR_USDHC_DAT5 = 523, |
212 | S32G_IMCR_USDHC_DAT6 = 519, |
213 | S32G_IMCR_USDHC_DAT7 = 518, |
214 | S32G_IMCR_USDHC_DQS = 524, |
215 | S32G_IMCR_CAN0_RXD = 513, |
216 | S32G_IMCR_CAN1_RXD = 631, |
217 | S32G_IMCR_CAN2_RXD = 632, |
218 | S32G_IMCR_CAN3_RXD = 633, |
219 | /* GMAC0 */ |
220 | S32G_IMCR_Ethernet_MDIO = 527, |
221 | S32G_IMCR_Ethernet_CRS = 526, |
222 | S32G_IMCR_Ethernet_COL = 525, |
223 | S32G_IMCR_Ethernet_RX_D0 = 531, |
224 | S32G_IMCR_Ethernet_RX_D1 = 532, |
225 | S32G_IMCR_Ethernet_RX_D2 = 533, |
226 | S32G_IMCR_Ethernet_RX_D3 = 534, |
227 | S32G_IMCR_Ethernet_RX_ER = 528, |
228 | S32G_IMCR_Ethernet_RX_CLK = 529, |
229 | S32G_IMCR_Ethernet_RX_DV = 530, |
230 | S32G_IMCR_Ethernet_TX_CLK = 538, |
231 | S32G_IMCR_Ethernet_REF_CLK = 535, |
232 | /* PFE EMAC 0 MII */ |
233 | /* PFE EMAC 1 MII */ |
234 | S32G_IMCR_PFE_EMAC_1_MDIO = 857, |
235 | S32G_IMCR_PFE_EMAC_1_CRS = 856, |
236 | S32G_IMCR_PFE_EMAC_1_COL = 855, |
237 | S32G_IMCR_PFE_EMAC_1_RX_D0 = 861, |
238 | S32G_IMCR_PFE_EMAC_1_RX_D1 = 862, |
239 | S32G_IMCR_PFE_EMAC_1_RX_D2 = 863, |
240 | S32G_IMCR_PFE_EMAC_1_RX_D3 = 864, |
241 | S32G_IMCR_PFE_EMAC_1_RX_ER = 860, |
242 | S32G_IMCR_PFE_EMAC_1_RX_CLK = 859, |
243 | S32G_IMCR_PFE_EMAC_1_RX_DV = 865, |
244 | S32G_IMCR_PFE_EMAC_1_TX_CLK = 866, |
245 | S32G_IMCR_PFE_EMAC_1_REF_CLK = 858, |
246 | /* PFE EMAC 2 MII */ |
247 | S32G_IMCR_PFE_EMAC_2_MDIO = 877, |
248 | S32G_IMCR_PFE_EMAC_2_CRS = 876, |
249 | S32G_IMCR_PFE_EMAC_2_COL = 875, |
250 | S32G_IMCR_PFE_EMAC_2_RX_D0 = 881, |
251 | S32G_IMCR_PFE_EMAC_2_RX_D1 = 882, |
252 | S32G_IMCR_PFE_EMAC_2_RX_D2 = 883, |
253 | S32G_IMCR_PFE_EMAC_2_RX_D3 = 884, |
254 | S32G_IMCR_PFE_EMAC_2_RX_ER = 880, |
255 | S32G_IMCR_PFE_EMAC_2_RX_CLK = 879, |
256 | S32G_IMCR_PFE_EMAC_2_RX_DV = 885, |
257 | S32G_IMCR_PFE_EMAC_2_TX_CLK = 886, |
258 | S32G_IMCR_PFE_EMAC_2_REF_CLK = 878, |
259 | |
260 | S32G_IMCR_FlexRay0_A_RX = 785, |
261 | S32G_IMCR_FlexRay0_B_RX = 786, |
262 | S32G_IMCR_FlexTimer0_CH0 = 655, |
263 | S32G_IMCR_FlexTimer1_CH0 = 665, |
264 | S32G_IMCR_FlexTimer0_CH1 = 656, |
265 | S32G_IMCR_FlexTimer1_CH1 = 666, |
266 | S32G_IMCR_FlexTimer0_CH2 = 657, |
267 | S32G_IMCR_FlexTimer1_CH2 = 667, |
268 | S32G_IMCR_FlexTimer0_CH3 = 658, |
269 | S32G_IMCR_FlexTimer1_CH3 = 668, |
270 | S32G_IMCR_FlexTimer0_CH4 = 659, |
271 | S32G_IMCR_FlexTimer1_CH4 = 669, |
272 | S32G_IMCR_FlexTimer0_CH5 = 660, |
273 | S32G_IMCR_FlexTimer1_CH5 = 670, |
274 | S32G_IMCR_FlexTimer0_EXTCLK = 661, |
275 | S32G_IMCR_FlexTimer1_EXTCLK = 671, |
276 | S32G_IMCR_I2C1_SCL = 717, |
277 | S32G_IMCR_I2C1_SDA = 718, |
278 | S32G_IMCR_I2C2_SCL = 719, |
279 | S32G_IMCR_I2C2_SDA = 720, |
280 | S32G_IMCR_I2C3_SCL = 721, |
281 | S32G_IMCR_I2C3_SDA = 722, |
282 | S32G_IMCR_I2C4_SCL = 723, |
283 | S32G_IMCR_I2C4_SDA = 724, |
284 | S32G_IMCR_LIN1_RX = 736, |
285 | S32G_IMCR_LIN2_RX = 737, |
286 | S32G_IMCR_DSPI0_PCS0 = 980, |
287 | S32G_IMCR_DSPI0_SCK = 981, |
288 | S32G_IMCR_DSPI0_SIN = 982, |
289 | S32G_IMCR_DSPI1_PCS0 = 985, |
290 | S32G_IMCR_DSPI1_SCK = 986, |
291 | S32G_IMCR_DSPI1_SIN = 987, |
292 | S32G_IMCR_DSPI2_PCS0 = 990, |
293 | S32G_IMCR_DSPI2_SCK = 991, |
294 | S32G_IMCR_DSPI2_SIN = 992, |
295 | S32G_IMCR_DSPI3_PCS0 = 995, |
296 | S32G_IMCR_DSPI3_SCK = 996, |
297 | S32G_IMCR_DSPI3_SIN = 997, |
298 | S32G_IMCR_DSPI4_PCS0 = 1000, |
299 | S32G_IMCR_DSPI4_SCK = 1001, |
300 | S32G_IMCR_DSPI4_SIN = 1002, |
301 | S32G_IMCR_DSPI5_PCS0 = 1005, |
302 | S32G_IMCR_DSPI5_SCK = 1006, |
303 | S32G_IMCR_DSPI5_SIN = 1007, |
304 | S32G_IMCR_LLCE_CAN0_RXD = 745, |
305 | S32G_IMCR_LLCE_CAN1_RXD = 746, |
306 | S32G_IMCR_LLCE_CAN2_RXD = 747, |
307 | S32G_IMCR_LLCE_CAN3_RXD = 748, |
308 | S32G_IMCR_LLCE_CAN4_RXD = 749, |
309 | S32G_IMCR_LLCE_CAN5_RXD = 750, |
310 | S32G_IMCR_LLCE_CAN6_RXD = 751, |
311 | S32G_IMCR_LLCE_CAN7_RXD = 752, |
312 | S32G_IMCR_LLCE_CAN8_RXD = 753, |
313 | S32G_IMCR_LLCE_CAN9_RXD = 754, |
314 | S32G_IMCR_LLCE_CAN10_RXD = 755, |
315 | S32G_IMCR_LLCE_CAN11_RXD = 756, |
316 | S32G_IMCR_LLCE_CAN12_RXD = 757, |
317 | S32G_IMCR_LLCE_CAN13_RXD = 758, |
318 | S32G_IMCR_LLCE_CAN14_RXD = 759, |
319 | S32G_IMCR_LLCE_CAN15_RXD = 760, |
320 | S32G_IMCR_USB_CLK = 895, |
321 | S32G_IMCR_USB_DATA0 = 896, |
322 | S32G_IMCR_USB_DATA1 = 897, |
323 | S32G_IMCR_USB_DATA2 = 898, |
324 | S32G_IMCR_USB_DATA3 = 899, |
325 | S32G_IMCR_USB_DATA4 = 900, |
326 | S32G_IMCR_USB_DATA5 = 901, |
327 | S32G_IMCR_USB_DATA6 = 902, |
328 | S32G_IMCR_USB_DATA7 = 903, |
329 | S32G_IMCR_USB_DIR = 904, |
330 | S32G_IMCR_USB_NXT = 905, |
331 | |
332 | S32G_IMCR_SIUL_EIRQ0 = 910, |
333 | S32G_IMCR_SIUL_EIRQ1 = 911, |
334 | S32G_IMCR_SIUL_EIRQ2 = 912, |
335 | S32G_IMCR_SIUL_EIRQ3 = 913, |
336 | S32G_IMCR_SIUL_EIRQ4 = 914, |
337 | S32G_IMCR_SIUL_EIRQ5 = 915, |
338 | S32G_IMCR_SIUL_EIRQ6 = 916, |
339 | S32G_IMCR_SIUL_EIRQ7 = 917, |
340 | S32G_IMCR_SIUL_EIRQ8 = 918, |
341 | S32G_IMCR_SIUL_EIRQ9 = 919, |
342 | S32G_IMCR_SIUL_EIRQ10 = 920, |
343 | S32G_IMCR_SIUL_EIRQ11 = 921, |
344 | S32G_IMCR_SIUL_EIRQ12 = 922, |
345 | S32G_IMCR_SIUL_EIRQ13 = 923, |
346 | S32G_IMCR_SIUL_EIRQ14 = 924, |
347 | S32G_IMCR_SIUL_EIRQ15 = 925, |
348 | S32G_IMCR_SIUL_EIRQ16 = 926, |
349 | S32G_IMCR_SIUL_EIRQ17 = 927, |
350 | S32G_IMCR_SIUL_EIRQ18 = 928, |
351 | S32G_IMCR_SIUL_EIRQ19 = 929, |
352 | S32G_IMCR_SIUL_EIRQ20 = 930, |
353 | S32G_IMCR_SIUL_EIRQ21 = 931, |
354 | S32G_IMCR_SIUL_EIRQ22 = 932, |
355 | S32G_IMCR_SIUL_EIRQ23 = 933, |
356 | S32G_IMCR_SIUL_EIRQ24 = 934, |
357 | S32G_IMCR_SIUL_EIRQ25 = 935, |
358 | S32G_IMCR_SIUL_EIRQ26 = 936, |
359 | S32G_IMCR_SIUL_EIRQ27 = 937, |
360 | S32G_IMCR_SIUL_EIRQ28 = 938, |
361 | S32G_IMCR_SIUL_EIRQ29 = 939, |
362 | S32G_IMCR_SIUL_EIRQ30 = 940, |
363 | S32G_IMCR_SIUL_EIRQ31 = 941, |
364 | }; |
365 | |
366 | /* Pad names for the pinmux subsystem */ |
367 | static const struct pinctrl_pin_desc s32_pinctrl_pads_siul2[] = { |
368 | |
369 | /* SIUL2_0 pins. */ |
370 | |
371 | S32_PINCTRL_PIN(S32G_MSCR_PA_00), |
372 | S32_PINCTRL_PIN(S32G_MSCR_PA_01), |
373 | S32_PINCTRL_PIN(S32G_MSCR_PA_02), |
374 | S32_PINCTRL_PIN(S32G_MSCR_PA_03), |
375 | S32_PINCTRL_PIN(S32G_MSCR_PA_04), |
376 | S32_PINCTRL_PIN(S32G_MSCR_PA_05), |
377 | S32_PINCTRL_PIN(S32G_MSCR_PA_06), |
378 | S32_PINCTRL_PIN(S32G_MSCR_PA_07), |
379 | S32_PINCTRL_PIN(S32G_MSCR_PA_08), |
380 | S32_PINCTRL_PIN(S32G_MSCR_PA_09), |
381 | S32_PINCTRL_PIN(S32G_MSCR_PA_10), |
382 | S32_PINCTRL_PIN(S32G_MSCR_PA_11), |
383 | S32_PINCTRL_PIN(S32G_MSCR_PA_12), |
384 | S32_PINCTRL_PIN(S32G_MSCR_PA_13), |
385 | S32_PINCTRL_PIN(S32G_MSCR_PA_14), |
386 | S32_PINCTRL_PIN(S32G_MSCR_PA_15), |
387 | S32_PINCTRL_PIN(S32G_MSCR_PB_00), |
388 | S32_PINCTRL_PIN(S32G_MSCR_PB_01), |
389 | S32_PINCTRL_PIN(S32G_MSCR_PB_02), |
390 | S32_PINCTRL_PIN(S32G_MSCR_PB_03), |
391 | S32_PINCTRL_PIN(S32G_MSCR_PB_04), |
392 | S32_PINCTRL_PIN(S32G_MSCR_PB_05), |
393 | S32_PINCTRL_PIN(S32G_MSCR_PB_06), |
394 | S32_PINCTRL_PIN(S32G_MSCR_PB_07), |
395 | S32_PINCTRL_PIN(S32G_MSCR_PB_08), |
396 | S32_PINCTRL_PIN(S32G_MSCR_PB_09), |
397 | S32_PINCTRL_PIN(S32G_MSCR_PB_10), |
398 | S32_PINCTRL_PIN(S32G_MSCR_PB_11), |
399 | S32_PINCTRL_PIN(S32G_MSCR_PB_12), |
400 | S32_PINCTRL_PIN(S32G_MSCR_PB_13), |
401 | S32_PINCTRL_PIN(S32G_MSCR_PB_14), |
402 | S32_PINCTRL_PIN(S32G_MSCR_PB_15), |
403 | S32_PINCTRL_PIN(S32G_MSCR_PC_00), |
404 | S32_PINCTRL_PIN(S32G_MSCR_PC_01), |
405 | S32_PINCTRL_PIN(S32G_MSCR_PC_02), |
406 | S32_PINCTRL_PIN(S32G_MSCR_PC_03), |
407 | S32_PINCTRL_PIN(S32G_MSCR_PC_04), |
408 | S32_PINCTRL_PIN(S32G_MSCR_PC_05), |
409 | S32_PINCTRL_PIN(S32G_MSCR_PC_06), |
410 | S32_PINCTRL_PIN(S32G_MSCR_PC_07), |
411 | S32_PINCTRL_PIN(S32G_MSCR_PC_08), |
412 | S32_PINCTRL_PIN(S32G_MSCR_PC_09), |
413 | S32_PINCTRL_PIN(S32G_MSCR_PC_10), |
414 | S32_PINCTRL_PIN(S32G_MSCR_PC_11), |
415 | S32_PINCTRL_PIN(S32G_MSCR_PC_12), |
416 | S32_PINCTRL_PIN(S32G_MSCR_PC_13), |
417 | S32_PINCTRL_PIN(S32G_MSCR_PC_14), |
418 | S32_PINCTRL_PIN(S32G_MSCR_PC_15), |
419 | S32_PINCTRL_PIN(S32G_MSCR_PD_00), |
420 | S32_PINCTRL_PIN(S32G_MSCR_PD_01), |
421 | S32_PINCTRL_PIN(S32G_MSCR_PD_02), |
422 | S32_PINCTRL_PIN(S32G_MSCR_PD_03), |
423 | S32_PINCTRL_PIN(S32G_MSCR_PD_04), |
424 | S32_PINCTRL_PIN(S32G_MSCR_PD_05), |
425 | S32_PINCTRL_PIN(S32G_MSCR_PD_06), |
426 | S32_PINCTRL_PIN(S32G_MSCR_PD_07), |
427 | S32_PINCTRL_PIN(S32G_MSCR_PD_08), |
428 | S32_PINCTRL_PIN(S32G_MSCR_PD_09), |
429 | S32_PINCTRL_PIN(S32G_MSCR_PD_10), |
430 | S32_PINCTRL_PIN(S32G_MSCR_PD_11), |
431 | S32_PINCTRL_PIN(S32G_MSCR_PD_12), |
432 | S32_PINCTRL_PIN(S32G_MSCR_PD_13), |
433 | S32_PINCTRL_PIN(S32G_MSCR_PD_14), |
434 | S32_PINCTRL_PIN(S32G_MSCR_PD_15), |
435 | S32_PINCTRL_PIN(S32G_MSCR_PE_00), |
436 | S32_PINCTRL_PIN(S32G_MSCR_PE_01), |
437 | S32_PINCTRL_PIN(S32G_MSCR_PE_02), |
438 | S32_PINCTRL_PIN(S32G_MSCR_PE_03), |
439 | S32_PINCTRL_PIN(S32G_MSCR_PE_04), |
440 | S32_PINCTRL_PIN(S32G_MSCR_PE_05), |
441 | S32_PINCTRL_PIN(S32G_MSCR_PE_06), |
442 | S32_PINCTRL_PIN(S32G_MSCR_PE_07), |
443 | S32_PINCTRL_PIN(S32G_MSCR_PE_08), |
444 | S32_PINCTRL_PIN(S32G_MSCR_PE_09), |
445 | S32_PINCTRL_PIN(S32G_MSCR_PE_10), |
446 | S32_PINCTRL_PIN(S32G_MSCR_PE_11), |
447 | S32_PINCTRL_PIN(S32G_MSCR_PE_12), |
448 | S32_PINCTRL_PIN(S32G_MSCR_PE_13), |
449 | S32_PINCTRL_PIN(S32G_MSCR_PE_14), |
450 | S32_PINCTRL_PIN(S32G_MSCR_PE_15), |
451 | S32_PINCTRL_PIN(S32G_MSCR_PF_00), |
452 | S32_PINCTRL_PIN(S32G_MSCR_PF_01), |
453 | S32_PINCTRL_PIN(S32G_MSCR_PF_02), |
454 | S32_PINCTRL_PIN(S32G_MSCR_PF_03), |
455 | S32_PINCTRL_PIN(S32G_MSCR_PF_04), |
456 | S32_PINCTRL_PIN(S32G_MSCR_PF_05), |
457 | S32_PINCTRL_PIN(S32G_MSCR_PF_06), |
458 | S32_PINCTRL_PIN(S32G_MSCR_PF_07), |
459 | S32_PINCTRL_PIN(S32G_MSCR_PF_08), |
460 | S32_PINCTRL_PIN(S32G_MSCR_PF_09), |
461 | S32_PINCTRL_PIN(S32G_MSCR_PF_10), |
462 | S32_PINCTRL_PIN(S32G_MSCR_PF_11), |
463 | S32_PINCTRL_PIN(S32G_MSCR_PF_12), |
464 | S32_PINCTRL_PIN(S32G_MSCR_PF_13), |
465 | S32_PINCTRL_PIN(S32G_MSCR_PF_14), |
466 | S32_PINCTRL_PIN(S32G_MSCR_PF_15), |
467 | S32_PINCTRL_PIN(S32G_MSCR_PG_00), |
468 | S32_PINCTRL_PIN(S32G_MSCR_PG_01), |
469 | S32_PINCTRL_PIN(S32G_MSCR_PG_02), |
470 | S32_PINCTRL_PIN(S32G_MSCR_PG_03), |
471 | S32_PINCTRL_PIN(S32G_MSCR_PG_04), |
472 | S32_PINCTRL_PIN(S32G_MSCR_PG_05), |
473 | |
474 | S32_PINCTRL_PIN(S32G_IMCR_QSPI_A_DATA0), |
475 | S32_PINCTRL_PIN(S32G_IMCR_QSPI_A_DATA1), |
476 | S32_PINCTRL_PIN(S32G_IMCR_QSPI_A_DATA2), |
477 | S32_PINCTRL_PIN(S32G_IMCR_QSPI_A_DATA3), |
478 | S32_PINCTRL_PIN(S32G_IMCR_QSPI_A_DATA4), |
479 | S32_PINCTRL_PIN(S32G_IMCR_QSPI_A_DATA5), |
480 | S32_PINCTRL_PIN(S32G_IMCR_QSPI_A_DATA6), |
481 | S32_PINCTRL_PIN(S32G_IMCR_QSPI_A_DATA7), |
482 | S32_PINCTRL_PIN(S32G_IMCR_QSPI_DQS_A), |
483 | S32_PINCTRL_PIN(S32G_IMCR_QSPI_B_DATA0), |
484 | S32_PINCTRL_PIN(S32G_IMCR_QSPI_B_DATA1), |
485 | S32_PINCTRL_PIN(S32G_IMCR_QSPI_B_DATA2), |
486 | S32_PINCTRL_PIN(S32G_IMCR_QSPI_B_DATA3), |
487 | S32_PINCTRL_PIN(S32G_IMCR_QSPI_B_DATA4), |
488 | S32_PINCTRL_PIN(S32G_IMCR_QSPI_B_DATA5), |
489 | S32_PINCTRL_PIN(S32G_IMCR_QSPI_B_DATA6), |
490 | S32_PINCTRL_PIN(S32G_IMCR_QSPI_B_DATA7), |
491 | S32_PINCTRL_PIN(S32G_IMCR_QSPI_DQS_B), |
492 | S32_PINCTRL_PIN(S32G_IMCR_I2C0_SCL), |
493 | S32_PINCTRL_PIN(S32G_IMCR_I2C0_SDA), |
494 | S32_PINCTRL_PIN(S32G_IMCR_LIN0_RX), |
495 | S32_PINCTRL_PIN(S32G_IMCR_USDHC_CMD), |
496 | S32_PINCTRL_PIN(S32G_IMCR_USDHC_DAT0), |
497 | S32_PINCTRL_PIN(S32G_IMCR_USDHC_DAT1), |
498 | S32_PINCTRL_PIN(S32G_IMCR_USDHC_DAT2), |
499 | S32_PINCTRL_PIN(S32G_IMCR_USDHC_DAT3), |
500 | S32_PINCTRL_PIN(S32G_IMCR_USDHC_DAT4), |
501 | S32_PINCTRL_PIN(S32G_IMCR_USDHC_DAT5), |
502 | S32_PINCTRL_PIN(S32G_IMCR_USDHC_DAT6), |
503 | S32_PINCTRL_PIN(S32G_IMCR_USDHC_DAT7), |
504 | S32_PINCTRL_PIN(S32G_IMCR_USDHC_DQS), |
505 | S32_PINCTRL_PIN(S32G_IMCR_CAN0_RXD), |
506 | /* GMAC0 */ |
507 | S32_PINCTRL_PIN(S32G_IMCR_Ethernet_MDIO), |
508 | S32_PINCTRL_PIN(S32G_IMCR_Ethernet_CRS), |
509 | S32_PINCTRL_PIN(S32G_IMCR_Ethernet_COL), |
510 | S32_PINCTRL_PIN(S32G_IMCR_Ethernet_RX_D0), |
511 | S32_PINCTRL_PIN(S32G_IMCR_Ethernet_RX_D1), |
512 | S32_PINCTRL_PIN(S32G_IMCR_Ethernet_RX_D2), |
513 | S32_PINCTRL_PIN(S32G_IMCR_Ethernet_RX_D3), |
514 | S32_PINCTRL_PIN(S32G_IMCR_Ethernet_RX_ER), |
515 | S32_PINCTRL_PIN(S32G_IMCR_Ethernet_RX_CLK), |
516 | S32_PINCTRL_PIN(S32G_IMCR_Ethernet_RX_DV), |
517 | S32_PINCTRL_PIN(S32G_IMCR_Ethernet_TX_CLK), |
518 | S32_PINCTRL_PIN(S32G_IMCR_Ethernet_REF_CLK), |
519 | |
520 | /* SIUL2_1 pins. */ |
521 | |
522 | S32_PINCTRL_PIN(S32G_MSCR_PH_00), |
523 | S32_PINCTRL_PIN(S32G_MSCR_PH_01), |
524 | S32_PINCTRL_PIN(S32G_MSCR_PH_02), |
525 | S32_PINCTRL_PIN(S32G_MSCR_PH_03), |
526 | S32_PINCTRL_PIN(S32G_MSCR_PH_04), |
527 | S32_PINCTRL_PIN(S32G_MSCR_PH_05), |
528 | S32_PINCTRL_PIN(S32G_MSCR_PH_06), |
529 | S32_PINCTRL_PIN(S32G_MSCR_PH_07), |
530 | S32_PINCTRL_PIN(S32G_MSCR_PH_08), |
531 | S32_PINCTRL_PIN(S32G_MSCR_PH_09), |
532 | S32_PINCTRL_PIN(S32G_MSCR_PH_10), |
533 | S32_PINCTRL_PIN(S32G_MSCR_PJ_00), |
534 | S32_PINCTRL_PIN(S32G_MSCR_PJ_01), |
535 | S32_PINCTRL_PIN(S32G_MSCR_PJ_02), |
536 | S32_PINCTRL_PIN(S32G_MSCR_PJ_03), |
537 | S32_PINCTRL_PIN(S32G_MSCR_PJ_04), |
538 | S32_PINCTRL_PIN(S32G_MSCR_PJ_05), |
539 | S32_PINCTRL_PIN(S32G_MSCR_PJ_06), |
540 | S32_PINCTRL_PIN(S32G_MSCR_PJ_07), |
541 | S32_PINCTRL_PIN(S32G_MSCR_PJ_08), |
542 | S32_PINCTRL_PIN(S32G_MSCR_PJ_09), |
543 | S32_PINCTRL_PIN(S32G_MSCR_PJ_10), |
544 | S32_PINCTRL_PIN(S32G_MSCR_PJ_11), |
545 | S32_PINCTRL_PIN(S32G_MSCR_PJ_12), |
546 | S32_PINCTRL_PIN(S32G_MSCR_PJ_13), |
547 | S32_PINCTRL_PIN(S32G_MSCR_PJ_14), |
548 | S32_PINCTRL_PIN(S32G_MSCR_PJ_15), |
549 | S32_PINCTRL_PIN(S32G_MSCR_PK_00), |
550 | S32_PINCTRL_PIN(S32G_MSCR_PK_01), |
551 | S32_PINCTRL_PIN(S32G_MSCR_PK_02), |
552 | S32_PINCTRL_PIN(S32G_MSCR_PK_03), |
553 | S32_PINCTRL_PIN(S32G_MSCR_PK_04), |
554 | S32_PINCTRL_PIN(S32G_MSCR_PK_05), |
555 | S32_PINCTRL_PIN(S32G_MSCR_PK_06), |
556 | S32_PINCTRL_PIN(S32G_MSCR_PK_07), |
557 | S32_PINCTRL_PIN(S32G_MSCR_PK_08), |
558 | S32_PINCTRL_PIN(S32G_MSCR_PK_09), |
559 | S32_PINCTRL_PIN(S32G_MSCR_PK_10), |
560 | S32_PINCTRL_PIN(S32G_MSCR_PK_11), |
561 | S32_PINCTRL_PIN(S32G_MSCR_PK_12), |
562 | S32_PINCTRL_PIN(S32G_MSCR_PK_13), |
563 | S32_PINCTRL_PIN(S32G_MSCR_PK_14), |
564 | S32_PINCTRL_PIN(S32G_MSCR_PK_15), |
565 | S32_PINCTRL_PIN(S32G_MSCR_PL_00), |
566 | S32_PINCTRL_PIN(S32G_MSCR_PL_01), |
567 | S32_PINCTRL_PIN(S32G_MSCR_PL_02), |
568 | S32_PINCTRL_PIN(S32G_MSCR_PL_03), |
569 | S32_PINCTRL_PIN(S32G_MSCR_PL_04), |
570 | S32_PINCTRL_PIN(S32G_MSCR_PL_05), |
571 | S32_PINCTRL_PIN(S32G_MSCR_PL_06), |
572 | S32_PINCTRL_PIN(S32G_MSCR_PL_07), |
573 | S32_PINCTRL_PIN(S32G_MSCR_PL_08), |
574 | S32_PINCTRL_PIN(S32G_MSCR_PL_09), |
575 | S32_PINCTRL_PIN(S32G_MSCR_PL_10), |
576 | S32_PINCTRL_PIN(S32G_MSCR_PL_11), |
577 | S32_PINCTRL_PIN(S32G_MSCR_PL_12), |
578 | S32_PINCTRL_PIN(S32G_MSCR_PL_13), |
579 | S32_PINCTRL_PIN(S32G_MSCR_PL_14), |
580 | |
581 | S32_PINCTRL_PIN(S32G_IMCR_FlexRay0_A_RX), |
582 | S32_PINCTRL_PIN(S32G_IMCR_FlexRay0_B_RX), |
583 | S32_PINCTRL_PIN(S32G_IMCR_FlexTimer0_CH0), |
584 | S32_PINCTRL_PIN(S32G_IMCR_FlexTimer1_CH0), |
585 | S32_PINCTRL_PIN(S32G_IMCR_FlexTimer0_CH1), |
586 | S32_PINCTRL_PIN(S32G_IMCR_FlexTimer1_CH1), |
587 | S32_PINCTRL_PIN(S32G_IMCR_FlexTimer0_CH2), |
588 | S32_PINCTRL_PIN(S32G_IMCR_FlexTimer1_CH2), |
589 | S32_PINCTRL_PIN(S32G_IMCR_FlexTimer0_CH3), |
590 | S32_PINCTRL_PIN(S32G_IMCR_FlexTimer1_CH3), |
591 | S32_PINCTRL_PIN(S32G_IMCR_FlexTimer0_CH4), |
592 | S32_PINCTRL_PIN(S32G_IMCR_FlexTimer1_CH4), |
593 | S32_PINCTRL_PIN(S32G_IMCR_FlexTimer0_CH5), |
594 | S32_PINCTRL_PIN(S32G_IMCR_FlexTimer1_CH5), |
595 | S32_PINCTRL_PIN(S32G_IMCR_FlexTimer0_EXTCLK), |
596 | S32_PINCTRL_PIN(S32G_IMCR_FlexTimer1_EXTCLK), |
597 | S32_PINCTRL_PIN(S32G_IMCR_I2C1_SCL), |
598 | S32_PINCTRL_PIN(S32G_IMCR_I2C1_SDA), |
599 | S32_PINCTRL_PIN(S32G_IMCR_I2C2_SCL), |
600 | S32_PINCTRL_PIN(S32G_IMCR_I2C2_SDA), |
601 | S32_PINCTRL_PIN(S32G_IMCR_I2C3_SCL), |
602 | S32_PINCTRL_PIN(S32G_IMCR_I2C3_SDA), |
603 | S32_PINCTRL_PIN(S32G_IMCR_I2C4_SCL), |
604 | S32_PINCTRL_PIN(S32G_IMCR_I2C4_SDA), |
605 | S32_PINCTRL_PIN(S32G_IMCR_LIN1_RX), |
606 | S32_PINCTRL_PIN(S32G_IMCR_LIN2_RX), |
607 | S32_PINCTRL_PIN(S32G_IMCR_DSPI0_PCS0), |
608 | S32_PINCTRL_PIN(S32G_IMCR_DSPI0_SCK), |
609 | S32_PINCTRL_PIN(S32G_IMCR_DSPI0_SIN), |
610 | S32_PINCTRL_PIN(S32G_IMCR_DSPI1_PCS0), |
611 | S32_PINCTRL_PIN(S32G_IMCR_DSPI1_SCK), |
612 | S32_PINCTRL_PIN(S32G_IMCR_DSPI1_SIN), |
613 | S32_PINCTRL_PIN(S32G_IMCR_DSPI2_PCS0), |
614 | S32_PINCTRL_PIN(S32G_IMCR_DSPI2_SCK), |
615 | S32_PINCTRL_PIN(S32G_IMCR_DSPI2_SIN), |
616 | S32_PINCTRL_PIN(S32G_IMCR_DSPI3_PCS0), |
617 | S32_PINCTRL_PIN(S32G_IMCR_DSPI3_SCK), |
618 | S32_PINCTRL_PIN(S32G_IMCR_DSPI3_SIN), |
619 | S32_PINCTRL_PIN(S32G_IMCR_DSPI4_PCS0), |
620 | S32_PINCTRL_PIN(S32G_IMCR_DSPI4_SCK), |
621 | S32_PINCTRL_PIN(S32G_IMCR_DSPI4_SIN), |
622 | S32_PINCTRL_PIN(S32G_IMCR_DSPI5_PCS0), |
623 | S32_PINCTRL_PIN(S32G_IMCR_DSPI5_SCK), |
624 | S32_PINCTRL_PIN(S32G_IMCR_DSPI5_SIN), |
625 | S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN0_RXD), |
626 | S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN1_RXD), |
627 | S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN2_RXD), |
628 | S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN3_RXD), |
629 | S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN4_RXD), |
630 | S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN5_RXD), |
631 | S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN6_RXD), |
632 | S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN7_RXD), |
633 | S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN8_RXD), |
634 | S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN9_RXD), |
635 | S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN10_RXD), |
636 | S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN11_RXD), |
637 | S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN12_RXD), |
638 | S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN13_RXD), |
639 | S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN14_RXD), |
640 | S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN15_RXD), |
641 | S32_PINCTRL_PIN(S32G_IMCR_CAN1_RXD), |
642 | S32_PINCTRL_PIN(S32G_IMCR_CAN2_RXD), |
643 | S32_PINCTRL_PIN(S32G_IMCR_CAN3_RXD), |
644 | S32_PINCTRL_PIN(S32G_IMCR_USB_CLK), |
645 | S32_PINCTRL_PIN(S32G_IMCR_USB_DATA0), |
646 | S32_PINCTRL_PIN(S32G_IMCR_USB_DATA1), |
647 | S32_PINCTRL_PIN(S32G_IMCR_USB_DATA2), |
648 | S32_PINCTRL_PIN(S32G_IMCR_USB_DATA3), |
649 | S32_PINCTRL_PIN(S32G_IMCR_USB_DATA4), |
650 | S32_PINCTRL_PIN(S32G_IMCR_USB_DATA5), |
651 | S32_PINCTRL_PIN(S32G_IMCR_USB_DATA6), |
652 | S32_PINCTRL_PIN(S32G_IMCR_USB_DATA7), |
653 | S32_PINCTRL_PIN(S32G_IMCR_USB_DIR), |
654 | S32_PINCTRL_PIN(S32G_IMCR_USB_NXT), |
655 | S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_MDIO), |
656 | S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_CRS), |
657 | S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_COL), |
658 | S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_RX_D0), |
659 | S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_RX_D1), |
660 | S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_RX_D2), |
661 | S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_RX_D3), |
662 | S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_RX_ER), |
663 | S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_RX_CLK), |
664 | S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_RX_DV), |
665 | S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_TX_CLK), |
666 | S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_REF_CLK), |
667 | S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_2_MDIO), |
668 | S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_2_CRS), |
669 | S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_2_COL), |
670 | S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_2_RX_D0), |
671 | S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_2_RX_D1), |
672 | S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_2_RX_D2), |
673 | S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_2_RX_D3), |
674 | S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_2_RX_ER), |
675 | S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_2_RX_CLK), |
676 | S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_2_RX_DV), |
677 | S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_2_TX_CLK), |
678 | S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_2_REF_CLK), |
679 | S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ0), |
680 | S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ1), |
681 | S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ2), |
682 | S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ3), |
683 | S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ4), |
684 | S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ5), |
685 | S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ6), |
686 | S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ7), |
687 | S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ8), |
688 | S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ9), |
689 | S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ10), |
690 | S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ11), |
691 | S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ12), |
692 | S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ13), |
693 | S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ14), |
694 | S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ15), |
695 | S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ16), |
696 | S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ17), |
697 | S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ18), |
698 | S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ19), |
699 | S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ20), |
700 | S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ21), |
701 | S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ22), |
702 | S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ23), |
703 | S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ24), |
704 | S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ25), |
705 | S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ26), |
706 | S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ27), |
707 | S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ28), |
708 | S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ29), |
709 | S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ30), |
710 | S32_PINCTRL_PIN(S32G_IMCR_SIUL_EIRQ31), |
711 | }; |
712 | |
713 | static const struct s32_pin_range s32_pin_ranges_siul2[] = { |
714 | /* MSCR pin ID ranges */ |
715 | S32_PIN_RANGE(0, 101), |
716 | S32_PIN_RANGE(112, 122), |
717 | S32_PIN_RANGE(144, 190), |
718 | /* IMCR pin ID ranges */ |
719 | S32_PIN_RANGE(512, 595), |
720 | S32_PIN_RANGE(631, 909), |
721 | S32_PIN_RANGE(942, 1007), |
722 | }; |
723 | |
724 | static const struct s32_pinctrl_soc_data s32_pinctrl_data = { |
725 | .pins = s32_pinctrl_pads_siul2, |
726 | .npins = ARRAY_SIZE(s32_pinctrl_pads_siul2), |
727 | .mem_pin_ranges = s32_pin_ranges_siul2, |
728 | .mem_regions = ARRAY_SIZE(s32_pin_ranges_siul2), |
729 | }; |
730 | |
731 | static const struct of_device_id s32_pinctrl_of_match[] = { |
732 | { |
733 | .compatible = "nxp,s32g2-siul2-pinctrl" , |
734 | .data = &s32_pinctrl_data, |
735 | }, |
736 | { /* sentinel */ } |
737 | }; |
738 | MODULE_DEVICE_TABLE(of, s32_pinctrl_of_match); |
739 | |
740 | static int s32g_pinctrl_probe(struct platform_device *pdev) |
741 | { |
742 | const struct s32_pinctrl_soc_data *soc_data; |
743 | |
744 | soc_data = of_device_get_match_data(dev: &pdev->dev); |
745 | |
746 | return s32_pinctrl_probe(pdev, soc_data); |
747 | } |
748 | |
749 | static const struct dev_pm_ops s32g_pinctrl_pm_ops = { |
750 | LATE_SYSTEM_SLEEP_PM_OPS(s32_pinctrl_suspend, s32_pinctrl_resume) |
751 | }; |
752 | |
753 | static struct platform_driver s32g_pinctrl_driver = { |
754 | .driver = { |
755 | .name = "s32g-siul2-pinctrl" , |
756 | .of_match_table = s32_pinctrl_of_match, |
757 | .pm = pm_sleep_ptr(&s32g_pinctrl_pm_ops), |
758 | .suppress_bind_attrs = true, |
759 | }, |
760 | .probe = s32g_pinctrl_probe, |
761 | }; |
762 | builtin_platform_driver(s32g_pinctrl_driver); |
763 | |
764 | MODULE_AUTHOR("Matthew Nunez <matthew.nunez@nxp.com>" ); |
765 | MODULE_DESCRIPTION("NXP S32G pinctrl driver" ); |
766 | MODULE_LICENSE("GPL" ); |
767 | |