1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SuperH Pin Function Controller GPIO driver.
4 *
5 * Copyright (C) 2008 Magnus Damm
6 * Copyright (C) 2009 - 2012 Paul Mundt
7 */
8
9#include <linux/device.h>
10#include <linux/gpio/driver.h>
11#include <linux/module.h>
12#include <linux/pinctrl/consumer.h>
13#include <linux/slab.h>
14#include <linux/spinlock.h>
15
16#include "core.h"
17
18struct sh_pfc_gpio_data_reg {
19 const struct pinmux_data_reg *info;
20 u32 shadow;
21};
22
23struct sh_pfc_gpio_pin {
24 u8 dbit;
25 u8 dreg;
26};
27
28struct sh_pfc_chip {
29 struct sh_pfc *pfc;
30 struct gpio_chip gpio_chip;
31
32 struct sh_pfc_window *mem;
33 struct sh_pfc_gpio_data_reg *regs;
34 struct sh_pfc_gpio_pin *pins;
35};
36
37static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc)
38{
39 struct sh_pfc_chip *chip = gpiochip_get_data(gc);
40 return chip->pfc;
41}
42
43static void gpio_get_data_reg(struct sh_pfc_chip *chip, unsigned int offset,
44 struct sh_pfc_gpio_data_reg **reg,
45 unsigned int *bit)
46{
47 int idx = sh_pfc_get_pin_index(pfc: chip->pfc, pin: offset);
48 struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx];
49
50 *reg = &chip->regs[gpio_pin->dreg];
51 *bit = gpio_pin->dbit;
52}
53
54static u32 gpio_read_data_reg(struct sh_pfc_chip *chip,
55 const struct pinmux_data_reg *dreg)
56{
57 phys_addr_t address = dreg->reg;
58 void __iomem *mem = address - chip->mem->phys + chip->mem->virt;
59
60 return sh_pfc_read_raw_reg(mapped_reg: mem, reg_width: dreg->reg_width);
61}
62
63static void gpio_write_data_reg(struct sh_pfc_chip *chip,
64 const struct pinmux_data_reg *dreg, u32 value)
65{
66 phys_addr_t address = dreg->reg;
67 void __iomem *mem = address - chip->mem->phys + chip->mem->virt;
68
69 sh_pfc_write_raw_reg(mapped_reg: mem, reg_width: dreg->reg_width, data: value);
70}
71
72static void gpio_setup_data_reg(struct sh_pfc_chip *chip, unsigned idx)
73{
74 struct sh_pfc *pfc = chip->pfc;
75 struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx];
76 const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
77 const struct pinmux_data_reg *dreg;
78 unsigned int bit;
79 unsigned int i;
80
81 for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) {
82 for (bit = 0; bit < dreg->reg_width; bit++) {
83 if (dreg->enum_ids[bit] == pin->enum_id) {
84 gpio_pin->dreg = i;
85 gpio_pin->dbit = bit;
86 return;
87 }
88 }
89 }
90
91 BUG();
92}
93
94static int gpio_setup_data_regs(struct sh_pfc_chip *chip)
95{
96 struct sh_pfc *pfc = chip->pfc;
97 const struct pinmux_data_reg *dreg;
98 unsigned int i;
99
100 /* Count the number of data registers, allocate memory and initialize
101 * them.
102 */
103 for (i = 0; pfc->info->data_regs[i].reg_width; ++i)
104 ;
105
106 chip->regs = devm_kcalloc(dev: pfc->dev, n: i, size: sizeof(*chip->regs),
107 GFP_KERNEL);
108 if (chip->regs == NULL)
109 return -ENOMEM;
110
111 for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) {
112 chip->regs[i].info = dreg;
113 chip->regs[i].shadow = gpio_read_data_reg(chip, dreg);
114 }
115
116 for (i = 0; i < pfc->info->nr_pins; i++) {
117 if (pfc->info->pins[i].enum_id == 0)
118 continue;
119
120 gpio_setup_data_reg(chip, idx: i);
121 }
122
123 return 0;
124}
125
126/* -----------------------------------------------------------------------------
127 * Pin GPIOs
128 */
129
130static int gpio_pin_request(struct gpio_chip *gc, unsigned offset)
131{
132 struct sh_pfc *pfc = gpio_to_pfc(gc);
133 int idx = sh_pfc_get_pin_index(pfc, pin: offset);
134
135 if (idx < 0 || pfc->info->pins[idx].enum_id == 0)
136 return -EINVAL;
137
138 return pinctrl_gpio_request(gc, offset);
139}
140
141static void gpio_pin_free(struct gpio_chip *gc, unsigned offset)
142{
143 return pinctrl_gpio_free(gc, offset);
144}
145
146static void gpio_pin_set_value(struct sh_pfc_chip *chip, unsigned offset,
147 int value)
148{
149 struct sh_pfc_gpio_data_reg *reg;
150 unsigned int bit;
151 unsigned int pos;
152
153 gpio_get_data_reg(chip, offset, reg: &reg, bit: &bit);
154
155 pos = reg->info->reg_width - (bit + 1);
156
157 if (value)
158 reg->shadow |= BIT(pos);
159 else
160 reg->shadow &= ~BIT(pos);
161
162 gpio_write_data_reg(chip, dreg: reg->info, value: reg->shadow);
163}
164
165static int gpio_pin_direction_input(struct gpio_chip *gc, unsigned offset)
166{
167 return pinctrl_gpio_direction_input(gc, offset);
168}
169
170static int gpio_pin_direction_output(struct gpio_chip *gc, unsigned offset,
171 int value)
172{
173 gpio_pin_set_value(chip: gpiochip_get_data(gc), offset, value);
174
175 return pinctrl_gpio_direction_output(gc, offset);
176}
177
178static int gpio_pin_get(struct gpio_chip *gc, unsigned offset)
179{
180 struct sh_pfc_chip *chip = gpiochip_get_data(gc);
181 struct sh_pfc_gpio_data_reg *reg;
182 unsigned int bit;
183 unsigned int pos;
184
185 gpio_get_data_reg(chip, offset, reg: &reg, bit: &bit);
186
187 pos = reg->info->reg_width - (bit + 1);
188
189 return (gpio_read_data_reg(chip, dreg: reg->info) >> pos) & 1;
190}
191
192static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value)
193{
194 gpio_pin_set_value(chip: gpiochip_get_data(gc), offset, value);
195}
196
197static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset)
198{
199 struct sh_pfc *pfc = gpio_to_pfc(gc);
200 unsigned int i, k;
201
202 for (i = 0; i < pfc->info->gpio_irq_size; i++) {
203 const short *gpios = pfc->info->gpio_irq[i].gpios;
204
205 for (k = 0; gpios[k] >= 0; k++) {
206 if (gpios[k] == offset)
207 return pfc->irqs[i];
208 }
209 }
210
211 return 0;
212}
213
214static int gpio_pin_setup(struct sh_pfc_chip *chip)
215{
216 struct sh_pfc *pfc = chip->pfc;
217 struct gpio_chip *gc = &chip->gpio_chip;
218 int ret;
219
220 chip->pins = devm_kcalloc(dev: pfc->dev,
221 n: pfc->info->nr_pins, size: sizeof(*chip->pins),
222 GFP_KERNEL);
223 if (chip->pins == NULL)
224 return -ENOMEM;
225
226 ret = gpio_setup_data_regs(chip);
227 if (ret < 0)
228 return ret;
229
230 gc->request = gpio_pin_request;
231 gc->free = gpio_pin_free;
232 gc->direction_input = gpio_pin_direction_input;
233 gc->get = gpio_pin_get;
234 gc->direction_output = gpio_pin_direction_output;
235 gc->set = gpio_pin_set;
236 gc->to_irq = gpio_pin_to_irq;
237
238 gc->label = pfc->info->name;
239 gc->parent = pfc->dev;
240 gc->owner = THIS_MODULE;
241 gc->base = IS_ENABLED(CONFIG_PINCTRL_SH_FUNC_GPIO) ? 0 : -1;
242 gc->ngpio = pfc->nr_gpio_pins;
243
244 return 0;
245}
246
247/* -----------------------------------------------------------------------------
248 * Function GPIOs
249 */
250
251#ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
252static int gpio_function_request(struct gpio_chip *gc, unsigned offset)
253{
254 struct sh_pfc *pfc = gpio_to_pfc(gc);
255 unsigned int mark = pfc->info->func_gpios[offset].enum_id;
256 unsigned long flags;
257 int ret;
258
259 dev_notice_once(pfc->dev,
260 "Use of GPIO API for function requests is deprecated, convert to pinctrl\n");
261
262 if (mark == 0)
263 return -EINVAL;
264
265 spin_lock_irqsave(&pfc->lock, flags);
266 ret = sh_pfc_config_mux(pfc, mark, pinmux_type: PINMUX_TYPE_FUNCTION);
267 spin_unlock_irqrestore(lock: &pfc->lock, flags);
268
269 return ret;
270}
271
272static int gpio_function_setup(struct sh_pfc_chip *chip)
273{
274 struct sh_pfc *pfc = chip->pfc;
275 struct gpio_chip *gc = &chip->gpio_chip;
276
277 gc->request = gpio_function_request;
278
279 gc->label = pfc->info->name;
280 gc->owner = THIS_MODULE;
281 gc->base = pfc->nr_gpio_pins;
282 gc->ngpio = pfc->info->nr_func_gpios;
283
284 return 0;
285}
286#endif /* CONFIG_PINCTRL_SH_FUNC_GPIO */
287
288/* -----------------------------------------------------------------------------
289 * Register/unregister
290 */
291
292static struct sh_pfc_chip *
293sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *),
294 struct sh_pfc_window *mem)
295{
296 struct sh_pfc_chip *chip;
297 int ret;
298
299 chip = devm_kzalloc(dev: pfc->dev, size: sizeof(*chip), GFP_KERNEL);
300 if (unlikely(!chip))
301 return ERR_PTR(error: -ENOMEM);
302
303 chip->mem = mem;
304 chip->pfc = pfc;
305
306 ret = setup(chip);
307 if (ret < 0)
308 return ERR_PTR(error: ret);
309
310 ret = devm_gpiochip_add_data(pfc->dev, &chip->gpio_chip, chip);
311 if (unlikely(ret < 0))
312 return ERR_PTR(error: ret);
313
314 dev_info(pfc->dev, "%s handling gpio %u -> %u\n",
315 chip->gpio_chip.label, chip->gpio_chip.base,
316 chip->gpio_chip.base + chip->gpio_chip.ngpio - 1);
317
318 return chip;
319}
320
321int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
322{
323 struct sh_pfc_chip *chip;
324 phys_addr_t address;
325 unsigned int i;
326
327 if (pfc->info->data_regs == NULL)
328 return 0;
329
330 /* Find the memory window that contains the GPIO registers. Boards that
331 * register a separate GPIO device will not supply a memory resource
332 * that covers the data registers. In that case don't try to handle
333 * GPIOs.
334 */
335 address = pfc->info->data_regs[0].reg;
336 for (i = 0; i < pfc->num_windows; ++i) {
337 struct sh_pfc_window *window = &pfc->windows[i];
338
339 if (address >= window->phys &&
340 address < window->phys + window->size)
341 break;
342 }
343
344 if (i == pfc->num_windows)
345 return 0;
346
347 /* If we have IRQ resources make sure their number is correct. */
348 if (pfc->num_irqs != pfc->info->gpio_irq_size) {
349 dev_err(pfc->dev, "invalid number of IRQ resources\n");
350 return -EINVAL;
351 }
352
353 /* Register the real GPIOs chip. */
354 chip = sh_pfc_add_gpiochip(pfc, setup: gpio_pin_setup, mem: &pfc->windows[i]);
355 if (IS_ERR(ptr: chip))
356 return PTR_ERR(ptr: chip);
357
358 pfc->gpio = chip;
359
360 if (IS_ENABLED(CONFIG_OF) && pfc->dev->of_node)
361 return 0;
362
363#ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
364 /*
365 * Register the GPIO to pin mappings. As pins with GPIO ports
366 * must come first in the ranges, skip the pins without GPIO
367 * ports by stopping at the first range that contains such a
368 * pin.
369 */
370 for (i = 0; i < pfc->nr_ranges; ++i) {
371 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
372 int ret;
373
374 if (range->start >= pfc->nr_gpio_pins)
375 break;
376
377 ret = gpiochip_add_pin_range(gc: &chip->gpio_chip,
378 pinctl_name: dev_name(dev: pfc->dev), gpio_offset: range->start, pin_offset: range->start,
379 npins: range->end - range->start + 1);
380 if (ret < 0)
381 return ret;
382 }
383
384 /* Register the function GPIOs chip. */
385 if (pfc->info->nr_func_gpios) {
386 chip = sh_pfc_add_gpiochip(pfc, setup: gpio_function_setup, NULL);
387 if (IS_ERR(ptr: chip))
388 return PTR_ERR(ptr: chip);
389 }
390#endif /* CONFIG_PINCTRL_SH_FUNC_GPIO */
391
392 return 0;
393}
394

source code of linux/drivers/pinctrl/renesas/gpio.c