1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * DWC3 glue for Cavium Octeon III SOCs. |
4 | * |
5 | * Copyright (C) 2010-2017 Cavium Networks |
6 | * Copyright (C) 2023 RACOM s.r.o. |
7 | */ |
8 | |
9 | #include <linux/bitfield.h> |
10 | #include <linux/bits.h> |
11 | #include <linux/device.h> |
12 | #include <linux/delay.h> |
13 | #include <linux/io.h> |
14 | #include <linux/module.h> |
15 | #include <linux/mutex.h> |
16 | #include <linux/of.h> |
17 | #include <linux/of_platform.h> |
18 | #include <linux/platform_device.h> |
19 | |
20 | /* |
21 | * USB Control Register |
22 | */ |
23 | #define USBDRD_UCTL_CTL 0x00 |
24 | /* BIST fast-clear mode select. A BIST run with this bit set |
25 | * clears all entries in USBH RAMs to 0x0. |
26 | */ |
27 | # define USBDRD_UCTL_CTL_CLEAR_BIST BIT_ULL(63) |
28 | /* 1 = Start BIST and cleared by hardware */ |
29 | # define USBDRD_UCTL_CTL_START_BIST BIT_ULL(62) |
30 | /* Reference clock select for SuperSpeed and HighSpeed PLLs: |
31 | * 0x0 = Both PLLs use DLMC_REF_CLK0 for reference clock |
32 | * 0x1 = Both PLLs use DLMC_REF_CLK1 for reference clock |
33 | * 0x2 = SuperSpeed PLL uses DLMC_REF_CLK0 for reference clock & |
34 | * HighSpeed PLL uses PLL_REF_CLK for reference clck |
35 | * 0x3 = SuperSpeed PLL uses DLMC_REF_CLK1 for reference clock & |
36 | * HighSpeed PLL uses PLL_REF_CLK for reference clck |
37 | */ |
38 | # define USBDRD_UCTL_CTL_REF_CLK_SEL GENMASK_ULL(61, 60) |
39 | /* 1 = Spread-spectrum clock enable, 0 = SS clock disable */ |
40 | # define USBDRD_UCTL_CTL_SSC_EN BIT_ULL(59) |
41 | /* Spread-spectrum clock modulation range: |
42 | * 0x0 = -4980 ppm downspread |
43 | * 0x1 = -4492 ppm downspread |
44 | * 0x2 = -4003 ppm downspread |
45 | * 0x3 - 0x7 = Reserved |
46 | */ |
47 | # define USBDRD_UCTL_CTL_SSC_RANGE GENMASK_ULL(58, 56) |
48 | /* Enable non-standard oscillator frequencies: |
49 | * [55:53] = modules -1 |
50 | * [52:47] = 2's complement push amount, 0 = Feature disabled |
51 | */ |
52 | # define USBDRD_UCTL_CTL_SSC_REF_CLK_SEL GENMASK_ULL(55, 47) |
53 | /* Reference clock multiplier for non-standard frequencies: |
54 | * 0x19 = 100MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1 |
55 | * 0x28 = 125MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1 |
56 | * 0x32 = 50MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1 |
57 | * Other Values = Reserved |
58 | */ |
59 | # define USBDRD_UCTL_CTL_MPLL_MULTIPLIER GENMASK_ULL(46, 40) |
60 | /* Enable reference clock to prescaler for SuperSpeed functionality. |
61 | * Should always be set to "1" |
62 | */ |
63 | # define USBDRD_UCTL_CTL_REF_SSP_EN BIT_ULL(39) |
64 | /* Divide the reference clock by 2 before entering the |
65 | * REF_CLK_FSEL divider: |
66 | * If REF_CLK_SEL = 0x0 or 0x1, then only 0x0 is legal |
67 | * If REF_CLK_SEL = 0x2 or 0x3, then: |
68 | * 0x1 = DLMC_REF_CLK* is 125MHz |
69 | * 0x0 = DLMC_REF_CLK* is another supported frequency |
70 | */ |
71 | # define USBDRD_UCTL_CTL_REF_CLK_DIV2 BIT_ULL(38) |
72 | /* Select reference clock freqnuency for both PLL blocks: |
73 | * 0x27 = REF_CLK_SEL is 0x0 or 0x1 |
74 | * 0x07 = REF_CLK_SEL is 0x2 or 0x3 |
75 | */ |
76 | # define USBDRD_UCTL_CTL_REF_CLK_FSEL GENMASK_ULL(37, 32) |
77 | /* Controller clock enable. */ |
78 | # define USBDRD_UCTL_CTL_H_CLK_EN BIT_ULL(30) |
79 | /* Select bypass input to controller clock divider: |
80 | * 0x0 = Use divided coprocessor clock from H_CLKDIV |
81 | * 0x1 = Use clock from GPIO pins |
82 | */ |
83 | # define USBDRD_UCTL_CTL_H_CLK_BYP_SEL BIT_ULL(29) |
84 | /* Reset controller clock divider. */ |
85 | # define USBDRD_UCTL_CTL_H_CLKDIV_RST BIT_ULL(28) |
86 | /* Clock divider select: |
87 | * 0x0 = divide by 1 |
88 | * 0x1 = divide by 2 |
89 | * 0x2 = divide by 4 |
90 | * 0x3 = divide by 6 |
91 | * 0x4 = divide by 8 |
92 | * 0x5 = divide by 16 |
93 | * 0x6 = divide by 24 |
94 | * 0x7 = divide by 32 |
95 | */ |
96 | # define USBDRD_UCTL_CTL_H_CLKDIV_SEL GENMASK_ULL(26, 24) |
97 | /* USB3 port permanently attached: 0x0 = No, 0x1 = Yes */ |
98 | # define USBDRD_UCTL_CTL_USB3_PORT_PERM_ATTACH BIT_ULL(21) |
99 | /* USB2 port permanently attached: 0x0 = No, 0x1 = Yes */ |
100 | # define USBDRD_UCTL_CTL_USB2_PORT_PERM_ATTACH BIT_ULL(20) |
101 | /* Disable SuperSpeed PHY: 0x0 = No, 0x1 = Yes */ |
102 | # define USBDRD_UCTL_CTL_USB3_PORT_DISABLE BIT_ULL(18) |
103 | /* Disable HighSpeed PHY: 0x0 = No, 0x1 = Yes */ |
104 | # define USBDRD_UCTL_CTL_USB2_PORT_DISABLE BIT_ULL(16) |
105 | /* Enable PHY SuperSpeed block power: 0x0 = No, 0x1 = Yes */ |
106 | # define USBDRD_UCTL_CTL_SS_POWER_EN BIT_ULL(14) |
107 | /* Enable PHY HighSpeed block power: 0x0 = No, 0x1 = Yes */ |
108 | # define USBDRD_UCTL_CTL_HS_POWER_EN BIT_ULL(12) |
109 | /* Enable USB UCTL interface clock: 0xx = No, 0x1 = Yes */ |
110 | # define USBDRD_UCTL_CTL_CSCLK_EN BIT_ULL(4) |
111 | /* Controller mode: 0x0 = Host, 0x1 = Device */ |
112 | # define USBDRD_UCTL_CTL_DRD_MODE BIT_ULL(3) |
113 | /* PHY reset */ |
114 | # define USBDRD_UCTL_CTL_UPHY_RST BIT_ULL(2) |
115 | /* Software reset UAHC */ |
116 | # define USBDRD_UCTL_CTL_UAHC_RST BIT_ULL(1) |
117 | /* Software resets UCTL */ |
118 | # define USBDRD_UCTL_CTL_UCTL_RST BIT_ULL(0) |
119 | |
120 | #define USBDRD_UCTL_BIST_STATUS 0x08 |
121 | #define USBDRD_UCTL_SPARE0 0x10 |
122 | #define USBDRD_UCTL_INTSTAT 0x30 |
123 | #define USBDRD_UCTL_PORT_CFG_HS(port) (0x40 + (0x20 * port)) |
124 | #define USBDRD_UCTL_PORT_CFG_SS(port) (0x48 + (0x20 * port)) |
125 | #define USBDRD_UCTL_PORT_CR_DBG_CFG(port) (0x50 + (0x20 * port)) |
126 | #define USBDRD_UCTL_PORT_CR_DBG_STATUS(port) (0x58 + (0x20 * port)) |
127 | |
128 | /* |
129 | * UCTL Configuration Register |
130 | */ |
131 | #define USBDRD_UCTL_HOST_CFG 0xe0 |
132 | /* Indicates minimum value of all received BELT values */ |
133 | # define USBDRD_UCTL_HOST_CFG_HOST_CURRENT_BELT GENMASK_ULL(59, 48) |
134 | /* HS jitter adjustment */ |
135 | # define USBDRD_UCTL_HOST_CFG_FLA GENMASK_ULL(37, 32) |
136 | /* Bus-master enable: 0x0 = Disabled (stall DMAs), 0x1 = enabled */ |
137 | # define USBDRD_UCTL_HOST_CFG_BME BIT_ULL(28) |
138 | /* Overcurrent protection enable: 0x0 = unavailable, 0x1 = available */ |
139 | # define USBDRD_UCTL_HOST_OCI_EN BIT_ULL(27) |
140 | /* Overcurrent sene selection: |
141 | * 0x0 = Overcurrent indication from off-chip is active-low |
142 | * 0x1 = Overcurrent indication from off-chip is active-high |
143 | */ |
144 | # define USBDRD_UCTL_HOST_OCI_ACTIVE_HIGH_EN BIT_ULL(26) |
145 | /* Port power control enable: 0x0 = unavailable, 0x1 = available */ |
146 | # define USBDRD_UCTL_HOST_PPC_EN BIT_ULL(25) |
147 | /* Port power control sense selection: |
148 | * 0x0 = Port power to off-chip is active-low |
149 | * 0x1 = Port power to off-chip is active-high |
150 | */ |
151 | # define USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN BIT_ULL(24) |
152 | |
153 | /* |
154 | * UCTL Shim Features Register |
155 | */ |
156 | #define USBDRD_UCTL_SHIM_CFG 0xe8 |
157 | /* Out-of-bound UAHC register access: 0 = read, 1 = write */ |
158 | # define USBDRD_UCTL_SHIM_CFG_XS_NCB_OOB_WRN BIT_ULL(63) |
159 | /* SRCID error log for out-of-bound UAHC register access: |
160 | * [59:58] = chipID |
161 | * [57] = Request source: 0 = core, 1 = NCB-device |
162 | * [56:51] = Core/NCB-device number, [56] always 0 for NCB devices |
163 | * [50:48] = SubID |
164 | */ |
165 | # define USBDRD_UCTL_SHIM_CFG_XS_NCB_OOB_OSRC GENMASK_ULL(59, 48) |
166 | /* Error log for bad UAHC DMA access: 0 = Read log, 1 = Write log */ |
167 | # define USBDRD_UCTL_SHIM_CFG_XM_BAD_DMA_WRN BIT_ULL(47) |
168 | /* Encoded error type for bad UAHC DMA */ |
169 | # define USBDRD_UCTL_SHIM_CFG_XM_BAD_DMA_TYPE GENMASK_ULL(43, 40) |
170 | /* Select the IOI read command used by DMA accesses */ |
171 | # define USBDRD_UCTL_SHIM_CFG_DMA_READ_CMD BIT_ULL(12) |
172 | /* Select endian format for DMA accesses to the L2C: |
173 | * 0x0 = Little endian |
174 | * 0x1 = Big endian |
175 | * 0x2 = Reserved |
176 | * 0x3 = Reserved |
177 | */ |
178 | # define USBDRD_UCTL_SHIM_CFG_DMA_ENDIAN_MODE GENMASK_ULL(9, 8) |
179 | /* Select endian format for IOI CSR access to UAHC: |
180 | * 0x0 = Little endian |
181 | * 0x1 = Big endian |
182 | * 0x2 = Reserved |
183 | * 0x3 = Reserved |
184 | */ |
185 | # define USBDRD_UCTL_SHIM_CFG_CSR_ENDIAN_MODE GENMASK_ULL(1, 0) |
186 | |
187 | #define USBDRD_UCTL_ECC 0xf0 |
188 | #define USBDRD_UCTL_SPARE1 0xf8 |
189 | |
190 | struct dwc3_octeon { |
191 | struct device *dev; |
192 | void __iomem *base; |
193 | }; |
194 | |
195 | #define DWC3_GPIO_POWER_NONE (-1) |
196 | |
197 | #ifdef CONFIG_CAVIUM_OCTEON_SOC |
198 | #include <asm/octeon/octeon.h> |
199 | static inline uint64_t dwc3_octeon_readq(void __iomem *addr) |
200 | { |
201 | return cvmx_readq_csr(addr); |
202 | } |
203 | |
204 | static inline void dwc3_octeon_writeq(void __iomem *base, uint64_t val) |
205 | { |
206 | cvmx_writeq_csr(base, val); |
207 | } |
208 | |
209 | static void dwc3_octeon_config_gpio(int index, int gpio) |
210 | { |
211 | union cvmx_gpio_bit_cfgx gpio_bit; |
212 | |
213 | if ((OCTEON_IS_MODEL(OCTEON_CN73XX) || |
214 | OCTEON_IS_MODEL(OCTEON_CNF75XX)) |
215 | && gpio <= 31) { |
216 | gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio)); |
217 | gpio_bit.s.tx_oe = 1; |
218 | gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x15); |
219 | cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64); |
220 | } else if (gpio <= 15) { |
221 | gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio)); |
222 | gpio_bit.s.tx_oe = 1; |
223 | gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x19); |
224 | cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64); |
225 | } else { |
226 | gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_XBIT_CFGX(gpio)); |
227 | gpio_bit.s.tx_oe = 1; |
228 | gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x19); |
229 | cvmx_write_csr(CVMX_GPIO_XBIT_CFGX(gpio), gpio_bit.u64); |
230 | } |
231 | } |
232 | #else |
233 | static inline uint64_t dwc3_octeon_readq(void __iomem *addr) |
234 | { |
235 | return 0; |
236 | } |
237 | |
238 | static inline void dwc3_octeon_writeq(void __iomem *base, uint64_t val) { } |
239 | |
240 | static inline void dwc3_octeon_config_gpio(int index, int gpio) { } |
241 | |
242 | static uint64_t octeon_get_io_clock_rate(void) |
243 | { |
244 | return 150000000; |
245 | } |
246 | #endif |
247 | |
248 | static int dwc3_octeon_get_divider(void) |
249 | { |
250 | static const uint8_t clk_div[] = { 1, 2, 4, 6, 8, 16, 24, 32 }; |
251 | int div = 0; |
252 | |
253 | while (div < ARRAY_SIZE(clk_div)) { |
254 | uint64_t rate = octeon_get_io_clock_rate() / clk_div[div]; |
255 | if (rate <= 300000000 && rate >= 150000000) |
256 | return div; |
257 | div++; |
258 | } |
259 | |
260 | return -EINVAL; |
261 | } |
262 | |
263 | static int dwc3_octeon_setup(struct dwc3_octeon *octeon, |
264 | int ref_clk_sel, int ref_clk_fsel, int mpll_mul, |
265 | int power_gpio, int power_active_low) |
266 | { |
267 | u64 val; |
268 | int div; |
269 | struct device *dev = octeon->dev; |
270 | void __iomem *uctl_ctl_reg = octeon->base + USBDRD_UCTL_CTL; |
271 | void __iomem *uctl_host_cfg_reg = octeon->base + USBDRD_UCTL_HOST_CFG; |
272 | |
273 | /* |
274 | * Step 1: Wait for all voltages to be stable...that surely |
275 | * happened before starting the kernel. SKIP |
276 | */ |
277 | |
278 | /* Step 2: Select GPIO for overcurrent indication, if desired. SKIP */ |
279 | |
280 | /* Step 3: Assert all resets. */ |
281 | val = dwc3_octeon_readq(addr: uctl_ctl_reg); |
282 | val |= USBDRD_UCTL_CTL_UPHY_RST | |
283 | USBDRD_UCTL_CTL_UAHC_RST | |
284 | USBDRD_UCTL_CTL_UCTL_RST; |
285 | dwc3_octeon_writeq(base: uctl_ctl_reg, val); |
286 | |
287 | /* Step 4a: Reset the clock dividers. */ |
288 | val = dwc3_octeon_readq(addr: uctl_ctl_reg); |
289 | val |= USBDRD_UCTL_CTL_H_CLKDIV_RST; |
290 | dwc3_octeon_writeq(base: uctl_ctl_reg, val); |
291 | |
292 | /* Step 4b: Select controller clock frequency. */ |
293 | div = dwc3_octeon_get_divider(); |
294 | if (div < 0) { |
295 | dev_err(dev, "clock divider invalid\n" ); |
296 | return div; |
297 | } |
298 | val = dwc3_octeon_readq(addr: uctl_ctl_reg); |
299 | val &= ~USBDRD_UCTL_CTL_H_CLKDIV_SEL; |
300 | val |= FIELD_PREP(USBDRD_UCTL_CTL_H_CLKDIV_SEL, div); |
301 | val |= USBDRD_UCTL_CTL_H_CLK_EN; |
302 | dwc3_octeon_writeq(base: uctl_ctl_reg, val); |
303 | val = dwc3_octeon_readq(addr: uctl_ctl_reg); |
304 | if ((div != FIELD_GET(USBDRD_UCTL_CTL_H_CLKDIV_SEL, val)) || |
305 | (!(FIELD_GET(USBDRD_UCTL_CTL_H_CLK_EN, val)))) { |
306 | dev_err(dev, "clock init failure (UCTL_CTL=%016llx)\n" , val); |
307 | return -EINVAL; |
308 | } |
309 | |
310 | /* Step 4c: Deassert the controller clock divider reset. */ |
311 | val &= ~USBDRD_UCTL_CTL_H_CLKDIV_RST; |
312 | dwc3_octeon_writeq(base: uctl_ctl_reg, val); |
313 | |
314 | /* Step 5a: Reference clock configuration. */ |
315 | val = dwc3_octeon_readq(addr: uctl_ctl_reg); |
316 | val &= ~USBDRD_UCTL_CTL_REF_CLK_DIV2; |
317 | val &= ~USBDRD_UCTL_CTL_REF_CLK_SEL; |
318 | val |= FIELD_PREP(USBDRD_UCTL_CTL_REF_CLK_SEL, ref_clk_sel); |
319 | |
320 | val &= ~USBDRD_UCTL_CTL_REF_CLK_FSEL; |
321 | val |= FIELD_PREP(USBDRD_UCTL_CTL_REF_CLK_FSEL, ref_clk_fsel); |
322 | |
323 | val &= ~USBDRD_UCTL_CTL_MPLL_MULTIPLIER; |
324 | val |= FIELD_PREP(USBDRD_UCTL_CTL_MPLL_MULTIPLIER, mpll_mul); |
325 | |
326 | /* Step 5b: Configure and enable spread-spectrum for SuperSpeed. */ |
327 | val |= USBDRD_UCTL_CTL_SSC_EN; |
328 | |
329 | /* Step 5c: Enable SuperSpeed. */ |
330 | val |= USBDRD_UCTL_CTL_REF_SSP_EN; |
331 | |
332 | /* Step 5d: Configure PHYs. SKIP */ |
333 | |
334 | /* Step 6a & 6b: Power up PHYs. */ |
335 | val |= USBDRD_UCTL_CTL_HS_POWER_EN; |
336 | val |= USBDRD_UCTL_CTL_SS_POWER_EN; |
337 | dwc3_octeon_writeq(base: uctl_ctl_reg, val); |
338 | |
339 | /* Step 7: Wait 10 controller-clock cycles to take effect. */ |
340 | udelay(10); |
341 | |
342 | /* Step 8a: Deassert UCTL reset signal. */ |
343 | val = dwc3_octeon_readq(addr: uctl_ctl_reg); |
344 | val &= ~USBDRD_UCTL_CTL_UCTL_RST; |
345 | dwc3_octeon_writeq(base: uctl_ctl_reg, val); |
346 | |
347 | /* Step 8b: Wait 10 controller-clock cycles. */ |
348 | udelay(10); |
349 | |
350 | /* Step 8c: Setup power control. */ |
351 | val = dwc3_octeon_readq(addr: uctl_host_cfg_reg); |
352 | val |= USBDRD_UCTL_HOST_PPC_EN; |
353 | if (power_gpio == DWC3_GPIO_POWER_NONE) { |
354 | val &= ~USBDRD_UCTL_HOST_PPC_EN; |
355 | } else { |
356 | val |= USBDRD_UCTL_HOST_PPC_EN; |
357 | dwc3_octeon_config_gpio(index: ((__force uintptr_t)octeon->base >> 24) & 1, |
358 | gpio: power_gpio); |
359 | dev_dbg(dev, "power control is using gpio%d\n" , power_gpio); |
360 | } |
361 | if (power_active_low) |
362 | val &= ~USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN; |
363 | else |
364 | val |= USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN; |
365 | dwc3_octeon_writeq(base: uctl_host_cfg_reg, val); |
366 | |
367 | /* Step 8d: Deassert UAHC reset signal. */ |
368 | val = dwc3_octeon_readq(addr: uctl_ctl_reg); |
369 | val &= ~USBDRD_UCTL_CTL_UAHC_RST; |
370 | dwc3_octeon_writeq(base: uctl_ctl_reg, val); |
371 | |
372 | /* Step 8e: Wait 10 controller-clock cycles. */ |
373 | udelay(10); |
374 | |
375 | /* Step 9: Enable conditional coprocessor clock of UCTL. */ |
376 | val = dwc3_octeon_readq(addr: uctl_ctl_reg); |
377 | val |= USBDRD_UCTL_CTL_CSCLK_EN; |
378 | dwc3_octeon_writeq(base: uctl_ctl_reg, val); |
379 | |
380 | /*Step 10: Set for host mode only. */ |
381 | val = dwc3_octeon_readq(addr: uctl_ctl_reg); |
382 | val &= ~USBDRD_UCTL_CTL_DRD_MODE; |
383 | dwc3_octeon_writeq(base: uctl_ctl_reg, val); |
384 | |
385 | return 0; |
386 | } |
387 | |
388 | static void dwc3_octeon_set_endian_mode(struct dwc3_octeon *octeon) |
389 | { |
390 | u64 val; |
391 | void __iomem *uctl_shim_cfg_reg = octeon->base + USBDRD_UCTL_SHIM_CFG; |
392 | |
393 | val = dwc3_octeon_readq(addr: uctl_shim_cfg_reg); |
394 | val &= ~USBDRD_UCTL_SHIM_CFG_DMA_ENDIAN_MODE; |
395 | val &= ~USBDRD_UCTL_SHIM_CFG_CSR_ENDIAN_MODE; |
396 | #ifdef __BIG_ENDIAN |
397 | val |= FIELD_PREP(USBDRD_UCTL_SHIM_CFG_DMA_ENDIAN_MODE, 1); |
398 | val |= FIELD_PREP(USBDRD_UCTL_SHIM_CFG_CSR_ENDIAN_MODE, 1); |
399 | #endif |
400 | dwc3_octeon_writeq(base: uctl_shim_cfg_reg, val); |
401 | } |
402 | |
403 | static void dwc3_octeon_phy_reset(struct dwc3_octeon *octeon) |
404 | { |
405 | u64 val; |
406 | void __iomem *uctl_ctl_reg = octeon->base + USBDRD_UCTL_CTL; |
407 | |
408 | val = dwc3_octeon_readq(addr: uctl_ctl_reg); |
409 | val &= ~USBDRD_UCTL_CTL_UPHY_RST; |
410 | dwc3_octeon_writeq(base: uctl_ctl_reg, val); |
411 | } |
412 | |
413 | static int dwc3_octeon_probe(struct platform_device *pdev) |
414 | { |
415 | struct device *dev = &pdev->dev; |
416 | struct device_node *node = dev->of_node; |
417 | struct dwc3_octeon *octeon; |
418 | const char *hs_clock_type, *ss_clock_type; |
419 | int ref_clk_sel, ref_clk_fsel, mpll_mul; |
420 | int power_active_low, power_gpio; |
421 | int err, len; |
422 | u32 clock_rate; |
423 | |
424 | if (of_property_read_u32(np: node, propname: "refclk-frequency" , out_value: &clock_rate)) { |
425 | dev_err(dev, "No UCTL \"refclk-frequency\"\n" ); |
426 | return -EINVAL; |
427 | } |
428 | if (of_property_read_string(np: node, propname: "refclk-type-ss" , out_string: &ss_clock_type)) { |
429 | dev_err(dev, "No UCTL \"refclk-type-ss\"\n" ); |
430 | return -EINVAL; |
431 | } |
432 | if (of_property_read_string(np: node, propname: "refclk-type-hs" , out_string: &hs_clock_type)) { |
433 | dev_err(dev, "No UCTL \"refclk-type-hs\"\n" ); |
434 | return -EINVAL; |
435 | } |
436 | |
437 | ref_clk_sel = 2; |
438 | if (strcmp("dlmc_ref_clk0" , ss_clock_type) == 0) { |
439 | if (strcmp(hs_clock_type, "dlmc_ref_clk0" ) == 0) |
440 | ref_clk_sel = 0; |
441 | else if (strcmp(hs_clock_type, "pll_ref_clk" )) |
442 | dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n" , |
443 | hs_clock_type); |
444 | } else if (strcmp(ss_clock_type, "dlmc_ref_clk1" ) == 0) { |
445 | if (strcmp(hs_clock_type, "dlmc_ref_clk1" ) == 0) { |
446 | ref_clk_sel = 1; |
447 | } else { |
448 | ref_clk_sel = 3; |
449 | if (strcmp(hs_clock_type, "pll_ref_clk" )) |
450 | dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n" , |
451 | hs_clock_type); |
452 | } |
453 | } else { |
454 | dev_warn(dev, "Invalid SS clock type %s, using dlmc_ref_clk0 instead\n" , |
455 | ss_clock_type); |
456 | } |
457 | |
458 | ref_clk_fsel = 0x07; |
459 | switch (clock_rate) { |
460 | default: |
461 | dev_warn(dev, "Invalid ref_clk %u, using 100000000 instead\n" , |
462 | clock_rate); |
463 | fallthrough; |
464 | case 100000000: |
465 | mpll_mul = 0x19; |
466 | if (ref_clk_sel < 2) |
467 | ref_clk_fsel = 0x27; |
468 | break; |
469 | case 50000000: |
470 | mpll_mul = 0x32; |
471 | break; |
472 | case 125000000: |
473 | mpll_mul = 0x28; |
474 | break; |
475 | } |
476 | |
477 | power_gpio = DWC3_GPIO_POWER_NONE; |
478 | power_active_low = 0; |
479 | if (of_find_property(np: node, name: "power" , lenp: &len)) { |
480 | u32 gpio_pwr[3]; |
481 | |
482 | switch (len) { |
483 | case 8: |
484 | of_property_read_u32_array(np: node, propname: "power" , out_values: gpio_pwr, sz: 2); |
485 | break; |
486 | case 12: |
487 | of_property_read_u32_array(np: node, propname: "power" , out_values: gpio_pwr, sz: 3); |
488 | power_active_low = gpio_pwr[2] & 0x01; |
489 | break; |
490 | default: |
491 | dev_err(dev, "invalid power configuration\n" ); |
492 | return -EINVAL; |
493 | } |
494 | power_gpio = gpio_pwr[1]; |
495 | } |
496 | |
497 | octeon = devm_kzalloc(dev, size: sizeof(*octeon), GFP_KERNEL); |
498 | if (!octeon) |
499 | return -ENOMEM; |
500 | |
501 | octeon->dev = dev; |
502 | octeon->base = devm_platform_ioremap_resource(pdev, index: 0); |
503 | if (IS_ERR(ptr: octeon->base)) |
504 | return PTR_ERR(ptr: octeon->base); |
505 | |
506 | err = dwc3_octeon_setup(octeon, ref_clk_sel, ref_clk_fsel, mpll_mul, |
507 | power_gpio, power_active_low); |
508 | if (err) |
509 | return err; |
510 | |
511 | dwc3_octeon_set_endian_mode(octeon); |
512 | dwc3_octeon_phy_reset(octeon); |
513 | |
514 | platform_set_drvdata(pdev, data: octeon); |
515 | |
516 | return of_platform_populate(root: node, NULL, NULL, parent: dev); |
517 | } |
518 | |
519 | static void dwc3_octeon_remove(struct platform_device *pdev) |
520 | { |
521 | struct dwc3_octeon *octeon = platform_get_drvdata(pdev); |
522 | |
523 | of_platform_depopulate(parent: octeon->dev); |
524 | } |
525 | |
526 | static const struct of_device_id dwc3_octeon_of_match[] = { |
527 | { .compatible = "cavium,octeon-7130-usb-uctl" }, |
528 | { }, |
529 | }; |
530 | MODULE_DEVICE_TABLE(of, dwc3_octeon_of_match); |
531 | |
532 | static struct platform_driver dwc3_octeon_driver = { |
533 | .probe = dwc3_octeon_probe, |
534 | .remove_new = dwc3_octeon_remove, |
535 | .driver = { |
536 | .name = "dwc3-octeon" , |
537 | .of_match_table = dwc3_octeon_of_match, |
538 | }, |
539 | }; |
540 | module_platform_driver(dwc3_octeon_driver); |
541 | |
542 | MODULE_ALIAS("platform:dwc3-octeon" ); |
543 | MODULE_AUTHOR("Ladislav Michl <ladis@linux-mips.org>" ); |
544 | MODULE_LICENSE("GPL" ); |
545 | MODULE_DESCRIPTION("DesignWare USB3 OCTEON III Glue Layer" ); |
546 | |