1 | // SPDX-License-Identifier: GPL-2.0 |
---|---|
2 | /* |
3 | * xHCI host controller driver PCI Bus Glue. |
4 | * |
5 | * Copyright (C) 2008 Intel Corp. |
6 | * |
7 | * Author: Sarah Sharp |
8 | * Some code borrowed from the Linux EHCI driver. |
9 | */ |
10 | |
11 | #include <linux/pci.h> |
12 | #include <linux/slab.h> |
13 | #include <linux/module.h> |
14 | #include <linux/acpi.h> |
15 | #include <linux/reset.h> |
16 | #include <linux/suspend.h> |
17 | |
18 | #include "xhci.h" |
19 | #include "xhci-trace.h" |
20 | #include "xhci-pci.h" |
21 | |
22 | #define SSIC_PORT_NUM 2 |
23 | #define SSIC_PORT_CFG2 0x880c |
24 | #define SSIC_PORT_CFG2_OFFSET 0x30 |
25 | #define PROG_DONE (1 << 30) |
26 | #define SSIC_PORT_UNUSED (1 << 31) |
27 | #define SPARSE_DISABLE_BIT 17 |
28 | #define SPARSE_CNTL_ENABLE 0xC12C |
29 | |
30 | /* Device for a quirk */ |
31 | #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 |
32 | #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 |
33 | #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009 |
34 | #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 0x1100 |
35 | #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 |
36 | |
37 | #define PCI_VENDOR_ID_ETRON 0x1b6f |
38 | #define PCI_DEVICE_ID_ETRON_EJ168 0x7023 |
39 | #define PCI_DEVICE_ID_ETRON_EJ188 0x7052 |
40 | |
41 | #define PCI_DEVICE_ID_VIA_VL805 0x3483 |
42 | |
43 | #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 |
44 | #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 |
45 | #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1 |
46 | #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5 |
47 | #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f |
48 | #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f |
49 | #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8 |
50 | #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8 |
51 | #define PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI 0x5aa8 |
52 | #define PCI_DEVICE_ID_INTEL_DENVERTON_XHCI 0x19d0 |
53 | #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13 |
54 | #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13 |
55 | #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_PCH_XHCI 0xa0ed |
56 | #define PCI_DEVICE_ID_INTEL_COMET_LAKE_XHCI 0xa3af |
57 | #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI 0x51ed |
58 | #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI 0x54ed |
59 | |
60 | #define PCI_VENDOR_ID_PHYTIUM 0x1db7 |
61 | #define PCI_DEVICE_ID_PHYTIUM_XHCI 0xdc27 |
62 | |
63 | /* Thunderbolt */ |
64 | #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138 |
65 | #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5 |
66 | #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6 |
67 | #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI 0x15c1 |
68 | #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db |
69 | #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4 |
70 | #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9 |
71 | #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec |
72 | #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0 |
73 | |
74 | #define PCI_DEVICE_ID_AMD_RENOIR_XHCI 0x1639 |
75 | #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9 |
76 | #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba |
77 | #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb |
78 | #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc |
79 | |
80 | #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042 |
81 | #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142 |
82 | #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242 |
83 | #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142 |
84 | #define PCI_DEVICE_ID_ASMEDIA_3042_XHCI 0x3042 |
85 | #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI 0x3242 |
86 | |
87 | static const char hcd_name[] = "xhci_hcd"; |
88 | |
89 | static struct hc_driver __read_mostly xhci_pci_hc_driver; |
90 | |
91 | static int xhci_pci_setup(struct usb_hcd *hcd); |
92 | static int xhci_pci_run(struct usb_hcd *hcd); |
93 | static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, |
94 | struct usb_tt *tt, gfp_t mem_flags); |
95 | |
96 | static const struct xhci_driver_overrides xhci_pci_overrides __initconst = { |
97 | .reset = xhci_pci_setup, |
98 | .start = xhci_pci_run, |
99 | .update_hub_device = xhci_pci_update_hub_device, |
100 | }; |
101 | |
102 | /* |
103 | * Primary Legacy and MSI IRQ are synced in suspend_common(). |
104 | * All MSI-X IRQs and secondary MSI IRQs should be synced here. |
105 | */ |
106 | static void xhci_msix_sync_irqs(struct xhci_hcd *xhci) |
107 | { |
108 | struct usb_hcd *hcd = xhci_to_hcd(xhci); |
109 | |
110 | if (hcd->msix_enabled) { |
111 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); |
112 | |
113 | /* for now, the driver only supports one primary interrupter */ |
114 | synchronize_irq(irq: pci_irq_vector(dev: pdev, nr: 0)); |
115 | } |
116 | } |
117 | |
118 | /* Legacy IRQ is freed by usb_remove_hcd() or usb_hcd_pci_shutdown() */ |
119 | static void xhci_cleanup_msix(struct xhci_hcd *xhci) |
120 | { |
121 | struct usb_hcd *hcd = xhci_to_hcd(xhci); |
122 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); |
123 | |
124 | if (hcd->irq > 0) |
125 | return; |
126 | |
127 | free_irq(pci_irq_vector(dev: pdev, nr: 0), xhci_to_hcd(xhci)); |
128 | pci_free_irq_vectors(dev: pdev); |
129 | hcd->msix_enabled = 0; |
130 | } |
131 | |
132 | /* Try enabling MSI-X with MSI and legacy IRQ as fallback */ |
133 | static int xhci_try_enable_msi(struct usb_hcd *hcd) |
134 | { |
135 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); |
136 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
137 | int ret; |
138 | |
139 | /* |
140 | * Some Fresco Logic host controllers advertise MSI, but fail to |
141 | * generate interrupts. Don't even try to enable MSI. |
142 | */ |
143 | if (xhci->quirks & XHCI_BROKEN_MSI) |
144 | goto legacy_irq; |
145 | |
146 | /* unregister the legacy interrupt */ |
147 | if (hcd->irq) |
148 | free_irq(hcd->irq, hcd); |
149 | hcd->irq = 0; |
150 | |
151 | /* |
152 | * Calculate number of MSI/MSI-X vectors supported. |
153 | * - max_interrupters: the max number of interrupts requested, capped to xhci HCSPARAMS1. |
154 | * - num_online_cpus: one vector per CPUs core, with at least one overall. |
155 | */ |
156 | xhci->nvecs = min(num_online_cpus() + 1, xhci->max_interrupters); |
157 | |
158 | /* TODO: Check with MSI Soc for sysdev */ |
159 | xhci->nvecs = pci_alloc_irq_vectors(dev: pdev, min_vecs: 1, max_vecs: xhci->nvecs, |
160 | PCI_IRQ_MSIX | PCI_IRQ_MSI); |
161 | if (xhci->nvecs < 0) { |
162 | xhci_dbg_trace(xhci, trace: trace_xhci_dbg_init, |
163 | fmt: "failed to allocate IRQ vectors"); |
164 | goto legacy_irq; |
165 | } |
166 | |
167 | ret = request_irq(irq: pci_irq_vector(dev: pdev, nr: 0), handler: xhci_msi_irq, flags: 0, name: "xhci_hcd", |
168 | dev: xhci_to_hcd(xhci)); |
169 | if (ret) |
170 | goto free_irq_vectors; |
171 | |
172 | hcd->msi_enabled = 1; |
173 | hcd->msix_enabled = pdev->msix_enabled; |
174 | return 0; |
175 | |
176 | free_irq_vectors: |
177 | xhci_dbg_trace(xhci, trace: trace_xhci_dbg_init, fmt: "disable %s interrupt", |
178 | pdev->msix_enabled ? "MSI-X": "MSI"); |
179 | pci_free_irq_vectors(dev: pdev); |
180 | |
181 | legacy_irq: |
182 | if (!pdev->irq) { |
183 | xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n"); |
184 | return -EINVAL; |
185 | } |
186 | |
187 | if (!strlen(hcd->irq_descr)) |
188 | snprintf(buf: hcd->irq_descr, size: sizeof(hcd->irq_descr), fmt: "%s:usb%d", |
189 | hcd->driver->description, hcd->self.busnum); |
190 | |
191 | /* fall back to legacy interrupt */ |
192 | ret = request_irq(irq: pdev->irq, handler: &usb_hcd_irq, IRQF_SHARED, name: hcd->irq_descr, dev: hcd); |
193 | if (ret) { |
194 | xhci_err(xhci, "request interrupt %d failed\n", pdev->irq); |
195 | return ret; |
196 | } |
197 | hcd->irq = pdev->irq; |
198 | return 0; |
199 | } |
200 | |
201 | static int xhci_pci_run(struct usb_hcd *hcd) |
202 | { |
203 | int ret; |
204 | |
205 | if (usb_hcd_is_primary_hcd(hcd)) { |
206 | ret = xhci_try_enable_msi(hcd); |
207 | if (ret) |
208 | return ret; |
209 | } |
210 | |
211 | return xhci_run(hcd); |
212 | } |
213 | |
214 | static void xhci_pci_stop(struct usb_hcd *hcd) |
215 | { |
216 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
217 | |
218 | xhci_stop(hcd); |
219 | |
220 | if (usb_hcd_is_primary_hcd(hcd)) |
221 | xhci_cleanup_msix(xhci); |
222 | } |
223 | |
224 | /* called after powerup, by probe or system-pm "wakeup" */ |
225 | static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) |
226 | { |
227 | /* |
228 | * TODO: Implement finding debug ports later. |
229 | * TODO: see if there are any quirks that need to be added to handle |
230 | * new extended capabilities. |
231 | */ |
232 | |
233 | /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ |
234 | if (!pci_set_mwi(dev: pdev)) |
235 | xhci_dbg(xhci, "MWI active\n"); |
236 | |
237 | xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); |
238 | return 0; |
239 | } |
240 | |
241 | static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) |
242 | { |
243 | struct pci_dev *pdev = to_pci_dev(dev); |
244 | |
245 | /* Look for vendor-specific quirks */ |
246 | if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && |
247 | (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || |
248 | pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { |
249 | if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && |
250 | pdev->revision == 0x0) { |
251 | xhci->quirks |= XHCI_RESET_EP_QUIRK; |
252 | xhci_dbg_trace(xhci, trace: trace_xhci_dbg_quirks, |
253 | fmt: "XHCI_RESET_EP_QUIRK for this evaluation HW is deprecated"); |
254 | } |
255 | if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && |
256 | pdev->revision == 0x4) { |
257 | xhci->quirks |= XHCI_SLOW_SUSPEND; |
258 | xhci_dbg_trace(xhci, trace: trace_xhci_dbg_quirks, |
259 | fmt: "QUIRK: Fresco Logic xHC revision %u" |
260 | "must be suspended extra slowly", |
261 | pdev->revision); |
262 | } |
263 | if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) |
264 | xhci->quirks |= XHCI_BROKEN_STREAMS; |
265 | /* Fresco Logic confirms: all revisions of this chip do not |
266 | * support MSI, even though some of them claim to in their PCI |
267 | * capabilities. |
268 | */ |
269 | xhci->quirks |= XHCI_BROKEN_MSI; |
270 | xhci_dbg_trace(xhci, trace: trace_xhci_dbg_quirks, |
271 | fmt: "QUIRK: Fresco Logic revision %u " |
272 | "has broken MSI implementation", |
273 | pdev->revision); |
274 | } |
275 | |
276 | if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && |
277 | pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009) |
278 | xhci->quirks |= XHCI_BROKEN_STREAMS; |
279 | |
280 | if (pdev->vendor == PCI_VENDOR_ID_NEC) |
281 | xhci->quirks |= XHCI_NEC_HOST; |
282 | |
283 | if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) |
284 | xhci->quirks |= XHCI_AMD_0x96_HOST; |
285 | |
286 | /* AMD PLL quirk */ |
287 | if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check()) |
288 | xhci->quirks |= XHCI_AMD_PLL_FIX; |
289 | |
290 | if (pdev->vendor == PCI_VENDOR_ID_AMD && |
291 | (pdev->device == 0x145c || |
292 | pdev->device == 0x15e0 || |
293 | pdev->device == 0x15e1 || |
294 | pdev->device == 0x43bb)) |
295 | xhci->quirks |= XHCI_SUSPEND_DELAY; |
296 | |
297 | if (pdev->vendor == PCI_VENDOR_ID_AMD && |
298 | (pdev->device == 0x15e0 || pdev->device == 0x15e1)) |
299 | xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND; |
300 | |
301 | if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) { |
302 | xhci->quirks |= XHCI_DISABLE_SPARSE; |
303 | xhci->quirks |= XHCI_RESET_ON_RESUME; |
304 | } |
305 | |
306 | if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x43f7) |
307 | xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; |
308 | |
309 | if ((pdev->vendor == PCI_VENDOR_ID_AMD) && |
310 | ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) || |
311 | (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) || |
312 | (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) || |
313 | (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1))) |
314 | xhci->quirks |= XHCI_U2_DISABLE_WAKE; |
315 | |
316 | if (pdev->vendor == PCI_VENDOR_ID_AMD && |
317 | pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI) |
318 | xhci->quirks |= XHCI_BROKEN_D3COLD_S2I; |
319 | |
320 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) { |
321 | xhci->quirks |= XHCI_LPM_SUPPORT; |
322 | xhci->quirks |= XHCI_INTEL_HOST; |
323 | xhci->quirks |= XHCI_AVOID_BEI; |
324 | } |
325 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
326 | pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { |
327 | xhci->quirks |= XHCI_EP_LIMIT_QUIRK; |
328 | xhci->limit_active_eps = 64; |
329 | xhci->quirks |= XHCI_SW_BW_CHECKING; |
330 | /* |
331 | * PPT desktop boards DH77EB and DH77DF will power back on after |
332 | * a few seconds of being shutdown. The fix for this is to |
333 | * switch the ports from xHCI to EHCI on shutdown. We can't use |
334 | * DMI information to find those particular boards (since each |
335 | * vendor will change the board name), so we have to key off all |
336 | * PPT chipsets. |
337 | */ |
338 | xhci->quirks |= XHCI_SPURIOUS_REBOOT; |
339 | } |
340 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
341 | (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI || |
342 | pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) { |
343 | xhci->quirks |= XHCI_SPURIOUS_REBOOT; |
344 | xhci->quirks |= XHCI_SPURIOUS_WAKEUP; |
345 | } |
346 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
347 | (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || |
348 | pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || |
349 | pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || |
350 | pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI || |
351 | pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI || |
352 | pdev->device == PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI || |
353 | pdev->device == PCI_DEVICE_ID_INTEL_DENVERTON_XHCI || |
354 | pdev->device == PCI_DEVICE_ID_INTEL_COMET_LAKE_XHCI)) { |
355 | xhci->quirks |= XHCI_PME_STUCK_QUIRK; |
356 | } |
357 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
358 | pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) |
359 | xhci->quirks |= XHCI_SSIC_PORT_UNUSED; |
360 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
361 | (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || |
362 | pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || |
363 | pdev->device == PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI)) |
364 | xhci->quirks |= XHCI_INTEL_USB_ROLE_SW; |
365 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
366 | (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || |
367 | pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || |
368 | pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || |
369 | pdev->device == PCI_DEVICE_ID_INTEL_APOLLO_LAKE_XHCI || |
370 | pdev->device == PCI_DEVICE_ID_INTEL_DENVERTON_XHCI)) |
371 | xhci->quirks |= XHCI_MISSING_CAS; |
372 | |
373 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
374 | (pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_PCH_XHCI || |
375 | pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI || |
376 | pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI)) |
377 | xhci->quirks |= XHCI_RESET_TO_DEFAULT; |
378 | |
379 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
380 | (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI || |
381 | pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI || |
382 | pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI || |
383 | pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI || |
384 | pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI || |
385 | pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI || |
386 | pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI || |
387 | pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI || |
388 | pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI || |
389 | pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI || |
390 | pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI)) |
391 | xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; |
392 | |
393 | if (pdev->vendor == PCI_VENDOR_ID_ETRON && |
394 | (pdev->device == PCI_DEVICE_ID_ETRON_EJ168 || |
395 | pdev->device == PCI_DEVICE_ID_ETRON_EJ188)) { |
396 | xhci->quirks |= XHCI_ETRON_HOST; |
397 | xhci->quirks |= XHCI_RESET_ON_RESUME; |
398 | xhci->quirks |= XHCI_BROKEN_STREAMS; |
399 | xhci->quirks |= XHCI_NO_SOFT_RETRY; |
400 | } |
401 | |
402 | if (pdev->vendor == PCI_VENDOR_ID_RENESAS && |
403 | pdev->device == 0x0014) { |
404 | xhci->quirks |= XHCI_ZERO_64B_REGS; |
405 | } |
406 | if (pdev->vendor == PCI_VENDOR_ID_RENESAS && |
407 | pdev->device == 0x0015) { |
408 | xhci->quirks |= XHCI_RESET_ON_RESUME; |
409 | xhci->quirks |= XHCI_ZERO_64B_REGS; |
410 | } |
411 | if (pdev->vendor == PCI_VENDOR_ID_VIA) |
412 | xhci->quirks |= XHCI_RESET_ON_RESUME; |
413 | |
414 | if (pdev->vendor == PCI_VENDOR_ID_PHYTIUM && |
415 | pdev->device == PCI_DEVICE_ID_PHYTIUM_XHCI) |
416 | xhci->quirks |= XHCI_RESET_ON_RESUME; |
417 | |
418 | /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ |
419 | if (pdev->vendor == PCI_VENDOR_ID_VIA && |
420 | pdev->device == 0x3432) |
421 | xhci->quirks |= XHCI_BROKEN_STREAMS; |
422 | |
423 | if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == PCI_DEVICE_ID_VIA_VL805) { |
424 | xhci->quirks |= XHCI_LPM_SUPPORT; |
425 | xhci->quirks |= XHCI_TRB_OVERFETCH; |
426 | } |
427 | |
428 | if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && |
429 | pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) { |
430 | /* |
431 | * try to tame the ASMedia 1042 controller which reports 0.96 |
432 | * but appears to behave more like 1.0 |
433 | */ |
434 | xhci->quirks |= XHCI_SPURIOUS_SUCCESS; |
435 | xhci->quirks |= XHCI_BROKEN_STREAMS; |
436 | } |
437 | if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && |
438 | pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) { |
439 | xhci->quirks |= XHCI_NO_64BIT_SUPPORT; |
440 | } |
441 | if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && |
442 | (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI || |
443 | pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI || |
444 | pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI)) |
445 | xhci->quirks |= XHCI_NO_64BIT_SUPPORT; |
446 | |
447 | if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && |
448 | pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) |
449 | xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL; |
450 | |
451 | if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && |
452 | pdev->device == PCI_DEVICE_ID_ASMEDIA_3042_XHCI) |
453 | xhci->quirks |= XHCI_RESET_ON_RESUME; |
454 | |
455 | if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) |
456 | xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7; |
457 | |
458 | if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM || |
459 | pdev->vendor == PCI_VENDOR_ID_CAVIUM) && |
460 | pdev->device == 0x9026) |
461 | xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT; |
462 | |
463 | if (pdev->vendor == PCI_VENDOR_ID_AMD && |
464 | (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 || |
465 | pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4)) |
466 | xhci->quirks |= XHCI_NO_SOFT_RETRY; |
467 | |
468 | if (pdev->vendor == PCI_VENDOR_ID_ZHAOXIN) { |
469 | xhci->quirks |= XHCI_ZHAOXIN_HOST; |
470 | xhci->quirks |= XHCI_LPM_SUPPORT; |
471 | |
472 | if (pdev->device == 0x9202) { |
473 | xhci->quirks |= XHCI_RESET_ON_RESUME; |
474 | xhci->quirks |= XHCI_TRB_OVERFETCH; |
475 | } |
476 | |
477 | if (pdev->device == 0x9203) |
478 | xhci->quirks |= XHCI_TRB_OVERFETCH; |
479 | } |
480 | |
481 | if (pdev->vendor == PCI_VENDOR_ID_CDNS && |
482 | pdev->device == PCI_DEVICE_ID_CDNS_USBSSP) |
483 | xhci->quirks |= XHCI_CDNS_SCTX_QUIRK; |
484 | |
485 | /* xHC spec requires PCI devices to support D3hot and D3cold */ |
486 | if (xhci->hci_version >= 0x120) |
487 | xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; |
488 | |
489 | if (xhci->quirks & XHCI_RESET_ON_RESUME) |
490 | xhci_dbg_trace(xhci, trace: trace_xhci_dbg_quirks, |
491 | fmt: "QUIRK: Resetting on resume"); |
492 | } |
493 | |
494 | #ifdef CONFIG_ACPI |
495 | static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) |
496 | { |
497 | static const guid_t intel_dsm_guid = |
498 | GUID_INIT(0xac340cb7, 0xe901, 0x45bf, |
499 | 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23); |
500 | union acpi_object *obj; |
501 | |
502 | obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), guid: &intel_dsm_guid, rev: 3, func: 1, |
503 | NULL); |
504 | ACPI_FREE(obj); |
505 | } |
506 | |
507 | static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) |
508 | { |
509 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
510 | struct xhci_hub *rhub = &xhci->usb3_rhub; |
511 | int ret; |
512 | int i; |
513 | |
514 | /* This is not the usb3 roothub we are looking for */ |
515 | if (hcd != rhub->hcd) |
516 | return; |
517 | |
518 | if (hdev->maxchild > rhub->num_ports) { |
519 | dev_err(&hdev->dev, "USB3 roothub port number mismatch\n"); |
520 | return; |
521 | } |
522 | |
523 | for (i = 0; i < hdev->maxchild; i++) { |
524 | ret = usb_acpi_port_lpm_incapable(hdev, index: i); |
525 | |
526 | dev_dbg(&hdev->dev, "port-%d disable U1/U2 _DSM: %d\n", i + 1, ret); |
527 | |
528 | if (ret >= 0) { |
529 | rhub->ports[i]->lpm_incapable = ret; |
530 | continue; |
531 | } |
532 | } |
533 | } |
534 | |
535 | #else |
536 | static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } |
537 | static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) { } |
538 | #endif /* CONFIG_ACPI */ |
539 | |
540 | /* called during probe() after chip reset completes */ |
541 | static int xhci_pci_setup(struct usb_hcd *hcd) |
542 | { |
543 | struct xhci_hcd *xhci; |
544 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); |
545 | int retval; |
546 | u8 sbrn; |
547 | |
548 | xhci = hcd_to_xhci(hcd); |
549 | |
550 | /* imod_interval is the interrupt moderation value in nanoseconds. */ |
551 | xhci->imod_interval = 40000; |
552 | |
553 | retval = xhci_gen_setup(hcd, get_quirks: xhci_pci_quirks); |
554 | if (retval) |
555 | return retval; |
556 | |
557 | if (!usb_hcd_is_primary_hcd(hcd)) |
558 | return 0; |
559 | |
560 | if (xhci->quirks & XHCI_PME_STUCK_QUIRK) |
561 | xhci_pme_acpi_rtd3_enable(dev: pdev); |
562 | |
563 | pci_read_config_byte(dev: pdev, XHCI_SBRN_OFFSET, val: &sbrn); |
564 | xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int)sbrn); |
565 | |
566 | /* Find any debug ports */ |
567 | return xhci_pci_reinit(xhci, pdev); |
568 | } |
569 | |
570 | static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, |
571 | struct usb_tt *tt, gfp_t mem_flags) |
572 | { |
573 | /* Check if acpi claims some USB3 roothub ports are lpm incapable */ |
574 | if (!hdev->parent) |
575 | xhci_find_lpm_incapable_ports(hcd, hdev); |
576 | |
577 | return xhci_update_hub_device(hcd, hdev, tt, mem_flags); |
578 | } |
579 | |
580 | /* |
581 | * We need to register our own PCI probe function (instead of the USB core's |
582 | * function) in order to create a second roothub under xHCI. |
583 | */ |
584 | int xhci_pci_common_probe(struct pci_dev *dev, const struct pci_device_id *id) |
585 | { |
586 | int retval; |
587 | struct xhci_hcd *xhci; |
588 | struct usb_hcd *hcd; |
589 | struct reset_control *reset; |
590 | |
591 | reset = devm_reset_control_get_optional_exclusive(dev: &dev->dev, NULL); |
592 | if (IS_ERR(ptr: reset)) |
593 | return PTR_ERR(ptr: reset); |
594 | reset_control_reset(rstc: reset); |
595 | |
596 | /* Prevent runtime suspending between USB-2 and USB-3 initialization */ |
597 | pm_runtime_get_noresume(dev: &dev->dev); |
598 | |
599 | /* Register the USB 2.0 roothub. |
600 | * FIXME: USB core must know to register the USB 2.0 roothub first. |
601 | * This is sort of silly, because we could just set the HCD driver flags |
602 | * to say USB 2.0, but I'm not sure what the implications would be in |
603 | * the other parts of the HCD code. |
604 | */ |
605 | retval = usb_hcd_pci_probe(dev, driver: &xhci_pci_hc_driver); |
606 | |
607 | if (retval) |
608 | goto put_runtime_pm; |
609 | |
610 | /* USB 2.0 roothub is stored in the PCI device now. */ |
611 | hcd = dev_get_drvdata(dev: &dev->dev); |
612 | xhci = hcd_to_xhci(hcd); |
613 | xhci->reset = reset; |
614 | xhci->shared_hcd = usb_create_shared_hcd(driver: &xhci_pci_hc_driver, dev: &dev->dev, |
615 | bus_name: pci_name(pdev: dev), shared_hcd: hcd); |
616 | if (!xhci->shared_hcd) { |
617 | retval = -ENOMEM; |
618 | goto dealloc_usb2_hcd; |
619 | } |
620 | |
621 | retval = xhci_ext_cap_init(xhci); |
622 | if (retval) |
623 | goto put_usb3_hcd; |
624 | |
625 | retval = usb_add_hcd(hcd: xhci->shared_hcd, irqnum: dev->irq, |
626 | IRQF_SHARED); |
627 | if (retval) |
628 | goto put_usb3_hcd; |
629 | /* Roothub already marked as USB 3.0 speed */ |
630 | |
631 | if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && |
632 | HCC_MAX_PSA(xhci->hcc_params) >= 4) |
633 | xhci->shared_hcd->can_do_streams = 1; |
634 | |
635 | /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ |
636 | pm_runtime_put_noidle(dev: &dev->dev); |
637 | |
638 | if (pci_choose_state(dev, PMSG_SUSPEND) == PCI_D0) |
639 | pm_runtime_get(dev: &dev->dev); |
640 | else if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) |
641 | pm_runtime_allow(dev: &dev->dev); |
642 | |
643 | dma_set_max_seg_size(dev: &dev->dev, UINT_MAX); |
644 | |
645 | if (device_property_read_bool(dev: &dev->dev, propname: "ti,pwron-active-high")) |
646 | pci_clear_and_set_config_dword(dev, pos: 0xE0, clear: 0, set: 1 << 22); |
647 | |
648 | return 0; |
649 | |
650 | put_usb3_hcd: |
651 | usb_put_hcd(hcd: xhci->shared_hcd); |
652 | dealloc_usb2_hcd: |
653 | usb_hcd_pci_remove(dev); |
654 | put_runtime_pm: |
655 | pm_runtime_put_noidle(dev: &dev->dev); |
656 | return retval; |
657 | } |
658 | EXPORT_SYMBOL_NS_GPL(xhci_pci_common_probe, "xhci"); |
659 | |
660 | /* handled by xhci-pci-renesas if enabled */ |
661 | static const struct pci_device_id pci_ids_renesas[] = { |
662 | { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, 0x0014) }, |
663 | { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, 0x0015) }, |
664 | { /* end: all zeroes */ } |
665 | }; |
666 | |
667 | static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) |
668 | { |
669 | if (IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS) && |
670 | pci_match_id(ids: pci_ids_renesas, dev)) |
671 | return -ENODEV; |
672 | |
673 | return xhci_pci_common_probe(dev, id); |
674 | } |
675 | |
676 | void xhci_pci_remove(struct pci_dev *dev) |
677 | { |
678 | struct xhci_hcd *xhci; |
679 | bool set_power_d3; |
680 | |
681 | xhci = hcd_to_xhci(hcd: pci_get_drvdata(pdev: dev)); |
682 | set_power_d3 = xhci->quirks & XHCI_SPURIOUS_WAKEUP; |
683 | |
684 | xhci->xhc_state |= XHCI_STATE_REMOVING; |
685 | |
686 | if (pci_choose_state(dev, PMSG_SUSPEND) == PCI_D0) |
687 | pm_runtime_put(dev: &dev->dev); |
688 | else if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) |
689 | pm_runtime_forbid(dev: &dev->dev); |
690 | |
691 | if (xhci->shared_hcd) { |
692 | usb_remove_hcd(hcd: xhci->shared_hcd); |
693 | usb_put_hcd(hcd: xhci->shared_hcd); |
694 | xhci->shared_hcd = NULL; |
695 | } |
696 | |
697 | usb_hcd_pci_remove(dev); |
698 | |
699 | /* Workaround for spurious wakeups at shutdown with HSW */ |
700 | if (set_power_d3) |
701 | pci_set_power_state(dev, PCI_D3hot); |
702 | } |
703 | EXPORT_SYMBOL_NS_GPL(xhci_pci_remove, "xhci"); |
704 | |
705 | /* |
706 | * In some Intel xHCI controllers, in order to get D3 working, |
707 | * through a vendor specific SSIC CONFIG register at offset 0x883c, |
708 | * SSIC PORT need to be marked as "unused" before putting xHCI |
709 | * into D3. After D3 exit, the SSIC port need to be marked as "used". |
710 | * Without this change, xHCI might not enter D3 state. |
711 | */ |
712 | static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend) |
713 | { |
714 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
715 | u32 val; |
716 | void __iomem *reg; |
717 | int i; |
718 | |
719 | for (i = 0; i < SSIC_PORT_NUM; i++) { |
720 | reg = (void __iomem *) xhci->cap_regs + |
721 | SSIC_PORT_CFG2 + |
722 | i * SSIC_PORT_CFG2_OFFSET; |
723 | |
724 | /* Notify SSIC that SSIC profile programming is not done. */ |
725 | val = readl(addr: reg) & ~PROG_DONE; |
726 | writel(val, addr: reg); |
727 | |
728 | /* Mark SSIC port as unused(suspend) or used(resume) */ |
729 | val = readl(addr: reg); |
730 | if (suspend) |
731 | val |= SSIC_PORT_UNUSED; |
732 | else |
733 | val &= ~SSIC_PORT_UNUSED; |
734 | writel(val, addr: reg); |
735 | |
736 | /* Notify SSIC that SSIC profile programming is done */ |
737 | val = readl(addr: reg) | PROG_DONE; |
738 | writel(val, addr: reg); |
739 | readl(addr: reg); |
740 | } |
741 | } |
742 | |
743 | /* |
744 | * Make sure PME works on some Intel xHCI controllers by writing 1 to clear |
745 | * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4 |
746 | */ |
747 | static void xhci_pme_quirk(struct usb_hcd *hcd) |
748 | { |
749 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
750 | void __iomem *reg; |
751 | u32 val; |
752 | |
753 | reg = (void __iomem *) xhci->cap_regs + 0x80a4; |
754 | val = readl(addr: reg); |
755 | writel(val: val | BIT(28), addr: reg); |
756 | readl(addr: reg); |
757 | } |
758 | |
759 | static void xhci_sparse_control_quirk(struct usb_hcd *hcd) |
760 | { |
761 | u32 reg; |
762 | |
763 | reg = readl(addr: hcd->regs + SPARSE_CNTL_ENABLE); |
764 | reg &= ~BIT(SPARSE_DISABLE_BIT); |
765 | writel(val: reg, addr: hcd->regs + SPARSE_CNTL_ENABLE); |
766 | } |
767 | |
768 | static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) |
769 | { |
770 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
771 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); |
772 | int ret; |
773 | |
774 | /* |
775 | * Systems with the TI redriver that loses port status change events |
776 | * need to have the registers polled during D3, so avoid D3cold. |
777 | */ |
778 | if (xhci->quirks & XHCI_COMP_MODE_QUIRK) |
779 | pci_d3cold_disable(dev: pdev); |
780 | |
781 | #ifdef CONFIG_SUSPEND |
782 | /* d3cold is broken, but only when s2idle is used */ |
783 | if (pm_suspend_target_state == PM_SUSPEND_TO_IDLE && |
784 | xhci->quirks & (XHCI_BROKEN_D3COLD_S2I)) |
785 | pci_d3cold_disable(dev: pdev); |
786 | #endif |
787 | |
788 | if (xhci->quirks & XHCI_PME_STUCK_QUIRK) |
789 | xhci_pme_quirk(hcd); |
790 | |
791 | if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) |
792 | xhci_ssic_port_unused_quirk(hcd, suspend: true); |
793 | |
794 | if (xhci->quirks & XHCI_DISABLE_SPARSE) |
795 | xhci_sparse_control_quirk(hcd); |
796 | |
797 | ret = xhci_suspend(xhci, do_wakeup); |
798 | |
799 | /* synchronize irq when using MSI-X */ |
800 | xhci_msix_sync_irqs(xhci); |
801 | |
802 | if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED)) |
803 | xhci_ssic_port_unused_quirk(hcd, suspend: false); |
804 | |
805 | return ret; |
806 | } |
807 | |
808 | static int xhci_pci_resume(struct usb_hcd *hcd, pm_message_t msg) |
809 | { |
810 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
811 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); |
812 | bool power_lost = msg.event == PM_EVENT_RESTORE; |
813 | bool is_auto_resume = msg.event == PM_EVENT_AUTO_RESUME; |
814 | |
815 | reset_control_reset(rstc: xhci->reset); |
816 | |
817 | /* The BIOS on systems with the Intel Panther Point chipset may or may |
818 | * not support xHCI natively. That means that during system resume, it |
819 | * may switch the ports back to EHCI so that users can use their |
820 | * keyboard to select a kernel from GRUB after resume from hibernate. |
821 | * |
822 | * The BIOS is supposed to remember whether the OS had xHCI ports |
823 | * enabled before resume, and switch the ports back to xHCI when the |
824 | * BIOS/OS semaphore is written, but we all know we can't trust BIOS |
825 | * writers. |
826 | * |
827 | * Unconditionally switch the ports back to xHCI after a system resume. |
828 | * It should not matter whether the EHCI or xHCI controller is |
829 | * resumed first. It's enough to do the switchover in xHCI because |
830 | * USB core won't notice anything as the hub driver doesn't start |
831 | * running again until after all the devices (including both EHCI and |
832 | * xHCI host controllers) have been resumed. |
833 | */ |
834 | |
835 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) |
836 | usb_enable_intel_xhci_ports(xhci_pdev: pdev); |
837 | |
838 | if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) |
839 | xhci_ssic_port_unused_quirk(hcd, suspend: false); |
840 | |
841 | if (xhci->quirks & XHCI_PME_STUCK_QUIRK) |
842 | xhci_pme_quirk(hcd); |
843 | |
844 | return xhci_resume(xhci, power_lost, is_auto_resume); |
845 | } |
846 | |
847 | static int xhci_pci_poweroff_late(struct usb_hcd *hcd, bool do_wakeup) |
848 | { |
849 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
850 | struct xhci_port *port; |
851 | struct usb_device *udev; |
852 | u32 portsc; |
853 | int i; |
854 | |
855 | /* |
856 | * Systems with XHCI_RESET_TO_DEFAULT quirk have boot firmware that |
857 | * cause significant boot delay if usb ports are in suspended U3 state |
858 | * during boot. Some USB devices survive in U3 state over S4 hibernate |
859 | * |
860 | * Disable ports that are in U3 if remote wake is not enabled for either |
861 | * host controller or connected device |
862 | */ |
863 | |
864 | if (!(xhci->quirks & XHCI_RESET_TO_DEFAULT)) |
865 | return 0; |
866 | |
867 | for (i = 0; i < HCS_MAX_PORTS(xhci->hcs_params1); i++) { |
868 | port = &xhci->hw_ports[i]; |
869 | portsc = readl(addr: port->addr); |
870 | |
871 | if ((portsc & PORT_PLS_MASK) != XDEV_U3) |
872 | continue; |
873 | |
874 | if (!port->slot_id || !xhci->devs[port->slot_id]) { |
875 | xhci_err(xhci, "No dev for slot_id %d for port %d-%d in U3\n", |
876 | port->slot_id, port->rhub->hcd->self.busnum, |
877 | port->hcd_portnum + 1); |
878 | continue; |
879 | } |
880 | |
881 | udev = xhci->devs[port->slot_id]->udev; |
882 | |
883 | /* if wakeup is enabled then don't disable the port */ |
884 | if (udev->do_remote_wakeup && do_wakeup) |
885 | continue; |
886 | |
887 | xhci_dbg(xhci, "port %d-%d in U3 without wakeup, disable it\n", |
888 | port->rhub->hcd->self.busnum, port->hcd_portnum + 1); |
889 | portsc = xhci_port_state_to_neutral(state: portsc); |
890 | writel(val: portsc | PORT_PE, addr: port->addr); |
891 | } |
892 | |
893 | return 0; |
894 | } |
895 | |
896 | static void xhci_pci_shutdown(struct usb_hcd *hcd) |
897 | { |
898 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
899 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); |
900 | |
901 | xhci_shutdown(hcd); |
902 | xhci_cleanup_msix(xhci); |
903 | |
904 | /* Yet another workaround for spurious wakeups at shutdown with HSW */ |
905 | if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) |
906 | pci_set_power_state(dev: pdev, PCI_D3hot); |
907 | } |
908 | |
909 | /*-------------------------------------------------------------------------*/ |
910 | |
911 | /* PCI driver selection metadata; PCI hotplugging uses this */ |
912 | static const struct pci_device_id pci_ids[] = { |
913 | /* handle any USB 3.0 xHCI controller */ |
914 | { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), |
915 | }, |
916 | { /* end: all zeroes */ } |
917 | }; |
918 | MODULE_DEVICE_TABLE(pci, pci_ids); |
919 | |
920 | /* pci driver glue; this is a "new style" PCI driver module */ |
921 | static struct pci_driver xhci_pci_driver = { |
922 | .name = hcd_name, |
923 | .id_table = pci_ids, |
924 | |
925 | .probe = xhci_pci_probe, |
926 | .remove = xhci_pci_remove, |
927 | /* suspend and resume implemented later */ |
928 | |
929 | .shutdown = usb_hcd_pci_shutdown, |
930 | .driver = { |
931 | .pm = pm_ptr(&usb_hcd_pci_pm_ops), |
932 | }, |
933 | }; |
934 | |
935 | static int __init xhci_pci_init(void) |
936 | { |
937 | xhci_init_driver(drv: &xhci_pci_hc_driver, over: &xhci_pci_overrides); |
938 | xhci_pci_hc_driver.pci_suspend = pm_ptr(xhci_pci_suspend); |
939 | xhci_pci_hc_driver.pci_resume = pm_ptr(xhci_pci_resume); |
940 | xhci_pci_hc_driver.pci_poweroff_late = pm_ptr(xhci_pci_poweroff_late); |
941 | xhci_pci_hc_driver.shutdown = pm_ptr(xhci_pci_shutdown); |
942 | xhci_pci_hc_driver.stop = xhci_pci_stop; |
943 | return pci_register_driver(&xhci_pci_driver); |
944 | } |
945 | module_init(xhci_pci_init); |
946 | |
947 | static void __exit xhci_pci_exit(void) |
948 | { |
949 | pci_unregister_driver(dev: &xhci_pci_driver); |
950 | } |
951 | module_exit(xhci_pci_exit); |
952 | |
953 | MODULE_DESCRIPTION("xHCI PCI Host Controller Driver"); |
954 | MODULE_LICENSE("GPL"); |
955 |
Definitions
- hcd_name
- xhci_pci_hc_driver
- xhci_pci_overrides
- xhci_msix_sync_irqs
- xhci_cleanup_msix
- xhci_try_enable_msi
- xhci_pci_run
- xhci_pci_stop
- xhci_pci_reinit
- xhci_pci_quirks
- xhci_pme_acpi_rtd3_enable
- xhci_find_lpm_incapable_ports
- xhci_pci_setup
- xhci_pci_update_hub_device
- xhci_pci_common_probe
- pci_ids_renesas
- xhci_pci_probe
- xhci_pci_remove
- xhci_ssic_port_unused_quirk
- xhci_pme_quirk
- xhci_sparse_control_quirk
- xhci_pci_suspend
- xhci_pci_resume
- xhci_pci_poweroff_late
- xhci_pci_shutdown
- pci_ids
- xhci_pci_driver
- xhci_pci_init
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