1 | /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ |
2 | /* Copyright 2019 NXP */ |
3 | |
4 | #ifndef _FSL_ENETC_MDIO_H_ |
5 | #define _FSL_ENETC_MDIO_H_ |
6 | |
7 | #include <linux/phy.h> |
8 | |
9 | /* PCS registers */ |
10 | #define ENETC_PCS_LINK_TIMER1 0x12 |
11 | #define ENETC_PCS_LINK_TIMER1_VAL 0x06a0 |
12 | #define ENETC_PCS_LINK_TIMER2 0x13 |
13 | #define ENETC_PCS_LINK_TIMER2_VAL 0x0003 |
14 | #define ENETC_PCS_IF_MODE 0x14 |
15 | #define ENETC_PCS_IF_MODE_SGMII_EN BIT(0) |
16 | #define ENETC_PCS_IF_MODE_USE_SGMII_AN BIT(1) |
17 | #define ENETC_PCS_IF_MODE_SGMII_SPEED(x) (((x) << 2) & GENMASK(3, 2)) |
18 | #define ENETC_PCS_IF_MODE_DUPLEX_HALF BIT(3) |
19 | |
20 | /* Not a mistake, the SerDes PLL needs to be set at 3.125 GHz by Reset |
21 | * Configuration Word (RCW, outside Linux control) for 2.5G SGMII mode. The PCS |
22 | * still thinks it's at gigabit. |
23 | */ |
24 | enum enetc_pcs_speed { |
25 | ENETC_PCS_SPEED_10 = 0, |
26 | ENETC_PCS_SPEED_100 = 1, |
27 | ENETC_PCS_SPEED_1000 = 2, |
28 | ENETC_PCS_SPEED_2500 = 2, |
29 | }; |
30 | |
31 | struct enetc_hw; |
32 | |
33 | struct enetc_mdio_priv { |
34 | struct enetc_hw *hw; |
35 | int mdio_base; |
36 | }; |
37 | |
38 | #if IS_REACHABLE(CONFIG_FSL_ENETC_MDIO) |
39 | |
40 | int enetc_mdio_read_c22(struct mii_bus *bus, int phy_id, int regnum); |
41 | int enetc_mdio_write_c22(struct mii_bus *bus, int phy_id, int regnum, |
42 | u16 value); |
43 | int enetc_mdio_read_c45(struct mii_bus *bus, int phy_id, int devad, int regnum); |
44 | int enetc_mdio_write_c45(struct mii_bus *bus, int phy_id, int devad, int regnum, |
45 | u16 value); |
46 | struct enetc_hw *enetc_hw_alloc(struct device *dev, void __iomem *port_regs); |
47 | |
48 | #else |
49 | |
50 | static inline int enetc_mdio_read_c22(struct mii_bus *bus, int phy_id, |
51 | int regnum) |
52 | { return -EINVAL; } |
53 | static inline int enetc_mdio_write_c22(struct mii_bus *bus, int phy_id, |
54 | int regnum, u16 value) |
55 | { return -EINVAL; } |
56 | static inline int enetc_mdio_read_c45(struct mii_bus *bus, int phy_id, |
57 | int devad, int regnum) |
58 | { return -EINVAL; } |
59 | static inline int enetc_mdio_write_c45(struct mii_bus *bus, int phy_id, |
60 | int devad, int regnum, u16 value) |
61 | { return -EINVAL; } |
62 | struct enetc_hw *enetc_hw_alloc(struct device *dev, void __iomem *port_regs) |
63 | { return ERR_PTR(-EINVAL); } |
64 | |
65 | #endif |
66 | |
67 | #endif |
68 | |