1 | // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
2 | /* Copyright 2017 Microsemi Corporation |
3 | * Copyright 2018-2019 NXP |
4 | */ |
5 | #include <linux/fsl/enetc_mdio.h> |
6 | #include <soc/mscc/ocelot_qsys.h> |
7 | #include <soc/mscc/ocelot_vcap.h> |
8 | #include <soc/mscc/ocelot_ana.h> |
9 | #include <soc/mscc/ocelot_dev.h> |
10 | #include <soc/mscc/ocelot_ptp.h> |
11 | #include <soc/mscc/ocelot_sys.h> |
12 | #include <net/tc_act/tc_gate.h> |
13 | #include <soc/mscc/ocelot.h> |
14 | #include <linux/dsa/ocelot.h> |
15 | #include <linux/pcs-lynx.h> |
16 | #include <net/pkt_sched.h> |
17 | #include <linux/iopoll.h> |
18 | #include <linux/mdio.h> |
19 | #include <linux/of.h> |
20 | #include <linux/pci.h> |
21 | #include <linux/time.h> |
22 | #include "felix.h" |
23 | |
24 | #define VSC9959_NUM_PORTS 6 |
25 | |
26 | #define VSC9959_TAS_GCL_ENTRY_MAX 63 |
27 | #define VSC9959_TAS_MIN_GATE_LEN_NS 33 |
28 | #define VSC9959_VCAP_POLICER_BASE 63 |
29 | #define VSC9959_VCAP_POLICER_MAX 383 |
30 | #define VSC9959_SWITCH_PCI_BAR 4 |
31 | #define VSC9959_IMDIO_PCI_BAR 0 |
32 | |
33 | #define VSC9959_PORT_MODE_SERDES (OCELOT_PORT_MODE_SGMII | \ |
34 | OCELOT_PORT_MODE_QSGMII | \ |
35 | OCELOT_PORT_MODE_1000BASEX | \ |
36 | OCELOT_PORT_MODE_2500BASEX | \ |
37 | OCELOT_PORT_MODE_USXGMII) |
38 | |
39 | static const u32 vsc9959_port_modes[VSC9959_NUM_PORTS] = { |
40 | VSC9959_PORT_MODE_SERDES, |
41 | VSC9959_PORT_MODE_SERDES, |
42 | VSC9959_PORT_MODE_SERDES, |
43 | VSC9959_PORT_MODE_SERDES, |
44 | OCELOT_PORT_MODE_INTERNAL, |
45 | OCELOT_PORT_MODE_INTERNAL, |
46 | }; |
47 | |
48 | static const u32 vsc9959_ana_regmap[] = { |
49 | REG(ANA_ADVLEARN, 0x0089a0), |
50 | REG(ANA_VLANMASK, 0x0089a4), |
51 | REG_RESERVED(ANA_PORT_B_DOMAIN), |
52 | REG(ANA_ANAGEFIL, 0x0089ac), |
53 | REG(ANA_ANEVENTS, 0x0089b0), |
54 | REG(ANA_STORMLIMIT_BURST, 0x0089b4), |
55 | REG(ANA_STORMLIMIT_CFG, 0x0089b8), |
56 | REG(ANA_ISOLATED_PORTS, 0x0089c8), |
57 | REG(ANA_COMMUNITY_PORTS, 0x0089cc), |
58 | REG(ANA_AUTOAGE, 0x0089d0), |
59 | REG(ANA_MACTOPTIONS, 0x0089d4), |
60 | REG(ANA_LEARNDISC, 0x0089d8), |
61 | REG(ANA_AGENCTRL, 0x0089dc), |
62 | REG(ANA_MIRRORPORTS, 0x0089e0), |
63 | REG(ANA_EMIRRORPORTS, 0x0089e4), |
64 | REG(ANA_FLOODING, 0x0089e8), |
65 | REG(ANA_FLOODING_IPMC, 0x008a08), |
66 | REG(ANA_SFLOW_CFG, 0x008a0c), |
67 | REG(ANA_PORT_MODE, 0x008a28), |
68 | REG(ANA_CUT_THRU_CFG, 0x008a48), |
69 | REG(ANA_PGID_PGID, 0x008400), |
70 | REG(ANA_TABLES_ANMOVED, 0x007f1c), |
71 | REG(ANA_TABLES_MACHDATA, 0x007f20), |
72 | REG(ANA_TABLES_MACLDATA, 0x007f24), |
73 | REG(ANA_TABLES_STREAMDATA, 0x007f28), |
74 | REG(ANA_TABLES_MACACCESS, 0x007f2c), |
75 | REG(ANA_TABLES_MACTINDX, 0x007f30), |
76 | REG(ANA_TABLES_VLANACCESS, 0x007f34), |
77 | REG(ANA_TABLES_VLANTIDX, 0x007f38), |
78 | REG(ANA_TABLES_ISDXACCESS, 0x007f3c), |
79 | REG(ANA_TABLES_ISDXTIDX, 0x007f40), |
80 | REG(ANA_TABLES_ENTRYLIM, 0x007f00), |
81 | REG(ANA_TABLES_PTP_ID_HIGH, 0x007f44), |
82 | REG(ANA_TABLES_PTP_ID_LOW, 0x007f48), |
83 | REG(ANA_TABLES_STREAMACCESS, 0x007f4c), |
84 | REG(ANA_TABLES_STREAMTIDX, 0x007f50), |
85 | REG(ANA_TABLES_SEQ_HISTORY, 0x007f54), |
86 | REG(ANA_TABLES_SEQ_MASK, 0x007f58), |
87 | REG(ANA_TABLES_SFID_MASK, 0x007f5c), |
88 | REG(ANA_TABLES_SFIDACCESS, 0x007f60), |
89 | REG(ANA_TABLES_SFIDTIDX, 0x007f64), |
90 | REG(ANA_MSTI_STATE, 0x008600), |
91 | REG(ANA_OAM_UPM_LM_CNT, 0x008000), |
92 | REG(ANA_SG_ACCESS_CTRL, 0x008a64), |
93 | REG(ANA_SG_CONFIG_REG_1, 0x007fb0), |
94 | REG(ANA_SG_CONFIG_REG_2, 0x007fb4), |
95 | REG(ANA_SG_CONFIG_REG_3, 0x007fb8), |
96 | REG(ANA_SG_CONFIG_REG_4, 0x007fbc), |
97 | REG(ANA_SG_CONFIG_REG_5, 0x007fc0), |
98 | REG(ANA_SG_GCL_GS_CONFIG, 0x007f80), |
99 | REG(ANA_SG_GCL_TI_CONFIG, 0x007f90), |
100 | REG(ANA_SG_STATUS_REG_1, 0x008980), |
101 | REG(ANA_SG_STATUS_REG_2, 0x008984), |
102 | REG(ANA_SG_STATUS_REG_3, 0x008988), |
103 | REG(ANA_PORT_VLAN_CFG, 0x007800), |
104 | REG(ANA_PORT_DROP_CFG, 0x007804), |
105 | REG(ANA_PORT_QOS_CFG, 0x007808), |
106 | REG(ANA_PORT_VCAP_CFG, 0x00780c), |
107 | REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x007810), |
108 | REG(ANA_PORT_VCAP_S2_CFG, 0x00781c), |
109 | REG(ANA_PORT_PCP_DEI_MAP, 0x007820), |
110 | REG(ANA_PORT_CPU_FWD_CFG, 0x007860), |
111 | REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x007864), |
112 | REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x007868), |
113 | REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00786c), |
114 | REG(ANA_PORT_PORT_CFG, 0x007870), |
115 | REG(ANA_PORT_POL_CFG, 0x007874), |
116 | REG(ANA_PORT_PTP_CFG, 0x007878), |
117 | REG(ANA_PORT_PTP_DLY1_CFG, 0x00787c), |
118 | REG(ANA_PORT_PTP_DLY2_CFG, 0x007880), |
119 | REG(ANA_PORT_SFID_CFG, 0x007884), |
120 | REG(ANA_PFC_PFC_CFG, 0x008800), |
121 | REG_RESERVED(ANA_PFC_PFC_TIMER), |
122 | REG_RESERVED(ANA_IPT_OAM_MEP_CFG), |
123 | REG_RESERVED(ANA_IPT_IPT), |
124 | REG_RESERVED(ANA_PPT_PPT), |
125 | REG_RESERVED(ANA_FID_MAP_FID_MAP), |
126 | REG(ANA_AGGR_CFG, 0x008a68), |
127 | REG(ANA_CPUQ_CFG, 0x008a6c), |
128 | REG_RESERVED(ANA_CPUQ_CFG2), |
129 | REG(ANA_CPUQ_8021_CFG, 0x008a74), |
130 | REG(ANA_DSCP_CFG, 0x008ab4), |
131 | REG(ANA_DSCP_REWR_CFG, 0x008bb4), |
132 | REG(ANA_VCAP_RNG_TYPE_CFG, 0x008bf4), |
133 | REG(ANA_VCAP_RNG_VAL_CFG, 0x008c14), |
134 | REG_RESERVED(ANA_VRAP_CFG), |
135 | REG_RESERVED(ANA_VRAP_HDR_DATA), |
136 | REG_RESERVED(ANA_VRAP_HDR_MASK), |
137 | REG(ANA_DISCARD_CFG, 0x008c40), |
138 | REG(ANA_FID_CFG, 0x008c44), |
139 | REG(ANA_POL_PIR_CFG, 0x004000), |
140 | REG(ANA_POL_CIR_CFG, 0x004004), |
141 | REG(ANA_POL_MODE_CFG, 0x004008), |
142 | REG(ANA_POL_PIR_STATE, 0x00400c), |
143 | REG(ANA_POL_CIR_STATE, 0x004010), |
144 | REG_RESERVED(ANA_POL_STATE), |
145 | REG(ANA_POL_FLOWC, 0x008c48), |
146 | REG(ANA_POL_HYST, 0x008cb4), |
147 | REG_RESERVED(ANA_POL_MISC_CFG), |
148 | }; |
149 | |
150 | static const u32 vsc9959_qs_regmap[] = { |
151 | REG(QS_XTR_GRP_CFG, 0x000000), |
152 | REG(QS_XTR_RD, 0x000008), |
153 | REG(QS_XTR_FRM_PRUNING, 0x000010), |
154 | REG(QS_XTR_FLUSH, 0x000018), |
155 | REG(QS_XTR_DATA_PRESENT, 0x00001c), |
156 | REG(QS_XTR_CFG, 0x000020), |
157 | REG(QS_INJ_GRP_CFG, 0x000024), |
158 | REG(QS_INJ_WR, 0x00002c), |
159 | REG(QS_INJ_CTRL, 0x000034), |
160 | REG(QS_INJ_STATUS, 0x00003c), |
161 | REG(QS_INJ_ERR, 0x000040), |
162 | REG_RESERVED(QS_INH_DBG), |
163 | }; |
164 | |
165 | static const u32 vsc9959_vcap_regmap[] = { |
166 | /* VCAP_CORE_CFG */ |
167 | REG(VCAP_CORE_UPDATE_CTRL, 0x000000), |
168 | REG(VCAP_CORE_MV_CFG, 0x000004), |
169 | /* VCAP_CORE_CACHE */ |
170 | REG(VCAP_CACHE_ENTRY_DAT, 0x000008), |
171 | REG(VCAP_CACHE_MASK_DAT, 0x000108), |
172 | REG(VCAP_CACHE_ACTION_DAT, 0x000208), |
173 | REG(VCAP_CACHE_CNT_DAT, 0x000308), |
174 | REG(VCAP_CACHE_TG_DAT, 0x000388), |
175 | /* VCAP_CONST */ |
176 | REG(VCAP_CONST_VCAP_VER, 0x000398), |
177 | REG(VCAP_CONST_ENTRY_WIDTH, 0x00039c), |
178 | REG(VCAP_CONST_ENTRY_CNT, 0x0003a0), |
179 | REG(VCAP_CONST_ENTRY_SWCNT, 0x0003a4), |
180 | REG(VCAP_CONST_ENTRY_TG_WIDTH, 0x0003a8), |
181 | REG(VCAP_CONST_ACTION_DEF_CNT, 0x0003ac), |
182 | REG(VCAP_CONST_ACTION_WIDTH, 0x0003b0), |
183 | REG(VCAP_CONST_CNT_WIDTH, 0x0003b4), |
184 | REG(VCAP_CONST_CORE_CNT, 0x0003b8), |
185 | REG(VCAP_CONST_IF_CNT, 0x0003bc), |
186 | }; |
187 | |
188 | static const u32 vsc9959_qsys_regmap[] = { |
189 | REG(QSYS_PORT_MODE, 0x00f460), |
190 | REG(QSYS_SWITCH_PORT_MODE, 0x00f480), |
191 | REG(QSYS_STAT_CNT_CFG, 0x00f49c), |
192 | REG(QSYS_EEE_CFG, 0x00f4a0), |
193 | REG(QSYS_EEE_THRES, 0x00f4b8), |
194 | REG(QSYS_IGR_NO_SHARING, 0x00f4bc), |
195 | REG(QSYS_EGR_NO_SHARING, 0x00f4c0), |
196 | REG(QSYS_SW_STATUS, 0x00f4c4), |
197 | REG(QSYS_EXT_CPU_CFG, 0x00f4e0), |
198 | REG_RESERVED(QSYS_PAD_CFG), |
199 | REG(QSYS_CPU_GROUP_MAP, 0x00f4e8), |
200 | REG_RESERVED(QSYS_QMAP), |
201 | REG_RESERVED(QSYS_ISDX_SGRP), |
202 | REG_RESERVED(QSYS_TIMED_FRAME_ENTRY), |
203 | REG(QSYS_TFRM_MISC, 0x00f50c), |
204 | REG(QSYS_TFRM_PORT_DLY, 0x00f510), |
205 | REG(QSYS_TFRM_TIMER_CFG_1, 0x00f514), |
206 | REG(QSYS_TFRM_TIMER_CFG_2, 0x00f518), |
207 | REG(QSYS_TFRM_TIMER_CFG_3, 0x00f51c), |
208 | REG(QSYS_TFRM_TIMER_CFG_4, 0x00f520), |
209 | REG(QSYS_TFRM_TIMER_CFG_5, 0x00f524), |
210 | REG(QSYS_TFRM_TIMER_CFG_6, 0x00f528), |
211 | REG(QSYS_TFRM_TIMER_CFG_7, 0x00f52c), |
212 | REG(QSYS_TFRM_TIMER_CFG_8, 0x00f530), |
213 | REG(QSYS_RED_PROFILE, 0x00f534), |
214 | REG(QSYS_RES_QOS_MODE, 0x00f574), |
215 | REG(QSYS_RES_CFG, 0x00c000), |
216 | REG(QSYS_RES_STAT, 0x00c004), |
217 | REG(QSYS_EGR_DROP_MODE, 0x00f578), |
218 | REG(QSYS_EQ_CTRL, 0x00f57c), |
219 | REG_RESERVED(QSYS_EVENTS_CORE), |
220 | REG(QSYS_QMAXSDU_CFG_0, 0x00f584), |
221 | REG(QSYS_QMAXSDU_CFG_1, 0x00f5a0), |
222 | REG(QSYS_QMAXSDU_CFG_2, 0x00f5bc), |
223 | REG(QSYS_QMAXSDU_CFG_3, 0x00f5d8), |
224 | REG(QSYS_QMAXSDU_CFG_4, 0x00f5f4), |
225 | REG(QSYS_QMAXSDU_CFG_5, 0x00f610), |
226 | REG(QSYS_QMAXSDU_CFG_6, 0x00f62c), |
227 | REG(QSYS_QMAXSDU_CFG_7, 0x00f648), |
228 | REG(QSYS_PREEMPTION_CFG, 0x00f664), |
229 | REG(QSYS_CIR_CFG, 0x000000), |
230 | REG(QSYS_EIR_CFG, 0x000004), |
231 | REG(QSYS_SE_CFG, 0x000008), |
232 | REG(QSYS_SE_DWRR_CFG, 0x00000c), |
233 | REG_RESERVED(QSYS_SE_CONNECT), |
234 | REG(QSYS_SE_DLB_SENSE, 0x000040), |
235 | REG(QSYS_CIR_STATE, 0x000044), |
236 | REG(QSYS_EIR_STATE, 0x000048), |
237 | REG_RESERVED(QSYS_SE_STATE), |
238 | REG(QSYS_HSCH_MISC_CFG, 0x00f67c), |
239 | REG(QSYS_TAG_CONFIG, 0x00f680), |
240 | REG(QSYS_TAS_PARAM_CFG_CTRL, 0x00f698), |
241 | REG(QSYS_PORT_MAX_SDU, 0x00f69c), |
242 | REG(QSYS_PARAM_CFG_REG_1, 0x00f440), |
243 | REG(QSYS_PARAM_CFG_REG_2, 0x00f444), |
244 | REG(QSYS_PARAM_CFG_REG_3, 0x00f448), |
245 | REG(QSYS_PARAM_CFG_REG_4, 0x00f44c), |
246 | REG(QSYS_PARAM_CFG_REG_5, 0x00f450), |
247 | REG(QSYS_GCL_CFG_REG_1, 0x00f454), |
248 | REG(QSYS_GCL_CFG_REG_2, 0x00f458), |
249 | REG(QSYS_PARAM_STATUS_REG_1, 0x00f400), |
250 | REG(QSYS_PARAM_STATUS_REG_2, 0x00f404), |
251 | REG(QSYS_PARAM_STATUS_REG_3, 0x00f408), |
252 | REG(QSYS_PARAM_STATUS_REG_4, 0x00f40c), |
253 | REG(QSYS_PARAM_STATUS_REG_5, 0x00f410), |
254 | REG(QSYS_PARAM_STATUS_REG_6, 0x00f414), |
255 | REG(QSYS_PARAM_STATUS_REG_7, 0x00f418), |
256 | REG(QSYS_PARAM_STATUS_REG_8, 0x00f41c), |
257 | REG(QSYS_PARAM_STATUS_REG_9, 0x00f420), |
258 | REG(QSYS_GCL_STATUS_REG_1, 0x00f424), |
259 | REG(QSYS_GCL_STATUS_REG_2, 0x00f428), |
260 | }; |
261 | |
262 | static const u32 vsc9959_rew_regmap[] = { |
263 | REG(REW_PORT_VLAN_CFG, 0x000000), |
264 | REG(REW_TAG_CFG, 0x000004), |
265 | REG(REW_PORT_CFG, 0x000008), |
266 | REG(REW_DSCP_CFG, 0x00000c), |
267 | REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010), |
268 | REG(REW_PTP_CFG, 0x000050), |
269 | REG(REW_PTP_DLY1_CFG, 0x000054), |
270 | REG(REW_RED_TAG_CFG, 0x000058), |
271 | REG(REW_DSCP_REMAP_DP1_CFG, 0x000410), |
272 | REG(REW_DSCP_REMAP_CFG, 0x000510), |
273 | REG_RESERVED(REW_STAT_CFG), |
274 | REG_RESERVED(REW_REW_STICKY), |
275 | REG_RESERVED(REW_PPT), |
276 | }; |
277 | |
278 | static const u32 vsc9959_sys_regmap[] = { |
279 | REG(SYS_COUNT_RX_OCTETS, 0x000000), |
280 | REG(SYS_COUNT_RX_UNICAST, 0x000004), |
281 | REG(SYS_COUNT_RX_MULTICAST, 0x000008), |
282 | REG(SYS_COUNT_RX_BROADCAST, 0x00000c), |
283 | REG(SYS_COUNT_RX_SHORTS, 0x000010), |
284 | REG(SYS_COUNT_RX_FRAGMENTS, 0x000014), |
285 | REG(SYS_COUNT_RX_JABBERS, 0x000018), |
286 | REG(SYS_COUNT_RX_CRC_ALIGN_ERRS, 0x00001c), |
287 | REG(SYS_COUNT_RX_SYM_ERRS, 0x000020), |
288 | REG(SYS_COUNT_RX_64, 0x000024), |
289 | REG(SYS_COUNT_RX_65_127, 0x000028), |
290 | REG(SYS_COUNT_RX_128_255, 0x00002c), |
291 | REG(SYS_COUNT_RX_256_511, 0x000030), |
292 | REG(SYS_COUNT_RX_512_1023, 0x000034), |
293 | REG(SYS_COUNT_RX_1024_1526, 0x000038), |
294 | REG(SYS_COUNT_RX_1527_MAX, 0x00003c), |
295 | REG(SYS_COUNT_RX_PAUSE, 0x000040), |
296 | REG(SYS_COUNT_RX_CONTROL, 0x000044), |
297 | REG(SYS_COUNT_RX_LONGS, 0x000048), |
298 | REG(SYS_COUNT_RX_CLASSIFIED_DROPS, 0x00004c), |
299 | REG(SYS_COUNT_RX_RED_PRIO_0, 0x000050), |
300 | REG(SYS_COUNT_RX_RED_PRIO_1, 0x000054), |
301 | REG(SYS_COUNT_RX_RED_PRIO_2, 0x000058), |
302 | REG(SYS_COUNT_RX_RED_PRIO_3, 0x00005c), |
303 | REG(SYS_COUNT_RX_RED_PRIO_4, 0x000060), |
304 | REG(SYS_COUNT_RX_RED_PRIO_5, 0x000064), |
305 | REG(SYS_COUNT_RX_RED_PRIO_6, 0x000068), |
306 | REG(SYS_COUNT_RX_RED_PRIO_7, 0x00006c), |
307 | REG(SYS_COUNT_RX_YELLOW_PRIO_0, 0x000070), |
308 | REG(SYS_COUNT_RX_YELLOW_PRIO_1, 0x000074), |
309 | REG(SYS_COUNT_RX_YELLOW_PRIO_2, 0x000078), |
310 | REG(SYS_COUNT_RX_YELLOW_PRIO_3, 0x00007c), |
311 | REG(SYS_COUNT_RX_YELLOW_PRIO_4, 0x000080), |
312 | REG(SYS_COUNT_RX_YELLOW_PRIO_5, 0x000084), |
313 | REG(SYS_COUNT_RX_YELLOW_PRIO_6, 0x000088), |
314 | REG(SYS_COUNT_RX_YELLOW_PRIO_7, 0x00008c), |
315 | REG(SYS_COUNT_RX_GREEN_PRIO_0, 0x000090), |
316 | REG(SYS_COUNT_RX_GREEN_PRIO_1, 0x000094), |
317 | REG(SYS_COUNT_RX_GREEN_PRIO_2, 0x000098), |
318 | REG(SYS_COUNT_RX_GREEN_PRIO_3, 0x00009c), |
319 | REG(SYS_COUNT_RX_GREEN_PRIO_4, 0x0000a0), |
320 | REG(SYS_COUNT_RX_GREEN_PRIO_5, 0x0000a4), |
321 | REG(SYS_COUNT_RX_GREEN_PRIO_6, 0x0000a8), |
322 | REG(SYS_COUNT_RX_GREEN_PRIO_7, 0x0000ac), |
323 | REG(SYS_COUNT_RX_ASSEMBLY_ERRS, 0x0000b0), |
324 | REG(SYS_COUNT_RX_SMD_ERRS, 0x0000b4), |
325 | REG(SYS_COUNT_RX_ASSEMBLY_OK, 0x0000b8), |
326 | REG(SYS_COUNT_RX_MERGE_FRAGMENTS, 0x0000bc), |
327 | REG(SYS_COUNT_RX_PMAC_OCTETS, 0x0000c0), |
328 | REG(SYS_COUNT_RX_PMAC_UNICAST, 0x0000c4), |
329 | REG(SYS_COUNT_RX_PMAC_MULTICAST, 0x0000c8), |
330 | REG(SYS_COUNT_RX_PMAC_BROADCAST, 0x0000cc), |
331 | REG(SYS_COUNT_RX_PMAC_SHORTS, 0x0000d0), |
332 | REG(SYS_COUNT_RX_PMAC_FRAGMENTS, 0x0000d4), |
333 | REG(SYS_COUNT_RX_PMAC_JABBERS, 0x0000d8), |
334 | REG(SYS_COUNT_RX_PMAC_CRC_ALIGN_ERRS, 0x0000dc), |
335 | REG(SYS_COUNT_RX_PMAC_SYM_ERRS, 0x0000e0), |
336 | REG(SYS_COUNT_RX_PMAC_64, 0x0000e4), |
337 | REG(SYS_COUNT_RX_PMAC_65_127, 0x0000e8), |
338 | REG(SYS_COUNT_RX_PMAC_128_255, 0x0000ec), |
339 | REG(SYS_COUNT_RX_PMAC_256_511, 0x0000f0), |
340 | REG(SYS_COUNT_RX_PMAC_512_1023, 0x0000f4), |
341 | REG(SYS_COUNT_RX_PMAC_1024_1526, 0x0000f8), |
342 | REG(SYS_COUNT_RX_PMAC_1527_MAX, 0x0000fc), |
343 | REG(SYS_COUNT_RX_PMAC_PAUSE, 0x000100), |
344 | REG(SYS_COUNT_RX_PMAC_CONTROL, 0x000104), |
345 | REG(SYS_COUNT_RX_PMAC_LONGS, 0x000108), |
346 | REG(SYS_COUNT_TX_OCTETS, 0x000200), |
347 | REG(SYS_COUNT_TX_UNICAST, 0x000204), |
348 | REG(SYS_COUNT_TX_MULTICAST, 0x000208), |
349 | REG(SYS_COUNT_TX_BROADCAST, 0x00020c), |
350 | REG(SYS_COUNT_TX_COLLISION, 0x000210), |
351 | REG(SYS_COUNT_TX_DROPS, 0x000214), |
352 | REG(SYS_COUNT_TX_PAUSE, 0x000218), |
353 | REG(SYS_COUNT_TX_64, 0x00021c), |
354 | REG(SYS_COUNT_TX_65_127, 0x000220), |
355 | REG(SYS_COUNT_TX_128_255, 0x000224), |
356 | REG(SYS_COUNT_TX_256_511, 0x000228), |
357 | REG(SYS_COUNT_TX_512_1023, 0x00022c), |
358 | REG(SYS_COUNT_TX_1024_1526, 0x000230), |
359 | REG(SYS_COUNT_TX_1527_MAX, 0x000234), |
360 | REG(SYS_COUNT_TX_YELLOW_PRIO_0, 0x000238), |
361 | REG(SYS_COUNT_TX_YELLOW_PRIO_1, 0x00023c), |
362 | REG(SYS_COUNT_TX_YELLOW_PRIO_2, 0x000240), |
363 | REG(SYS_COUNT_TX_YELLOW_PRIO_3, 0x000244), |
364 | REG(SYS_COUNT_TX_YELLOW_PRIO_4, 0x000248), |
365 | REG(SYS_COUNT_TX_YELLOW_PRIO_5, 0x00024c), |
366 | REG(SYS_COUNT_TX_YELLOW_PRIO_6, 0x000250), |
367 | REG(SYS_COUNT_TX_YELLOW_PRIO_7, 0x000254), |
368 | REG(SYS_COUNT_TX_GREEN_PRIO_0, 0x000258), |
369 | REG(SYS_COUNT_TX_GREEN_PRIO_1, 0x00025c), |
370 | REG(SYS_COUNT_TX_GREEN_PRIO_2, 0x000260), |
371 | REG(SYS_COUNT_TX_GREEN_PRIO_3, 0x000264), |
372 | REG(SYS_COUNT_TX_GREEN_PRIO_4, 0x000268), |
373 | REG(SYS_COUNT_TX_GREEN_PRIO_5, 0x00026c), |
374 | REG(SYS_COUNT_TX_GREEN_PRIO_6, 0x000270), |
375 | REG(SYS_COUNT_TX_GREEN_PRIO_7, 0x000274), |
376 | REG(SYS_COUNT_TX_AGED, 0x000278), |
377 | REG(SYS_COUNT_TX_MM_HOLD, 0x00027c), |
378 | REG(SYS_COUNT_TX_MERGE_FRAGMENTS, 0x000280), |
379 | REG(SYS_COUNT_TX_PMAC_OCTETS, 0x000284), |
380 | REG(SYS_COUNT_TX_PMAC_UNICAST, 0x000288), |
381 | REG(SYS_COUNT_TX_PMAC_MULTICAST, 0x00028c), |
382 | REG(SYS_COUNT_TX_PMAC_BROADCAST, 0x000290), |
383 | REG(SYS_COUNT_TX_PMAC_PAUSE, 0x000294), |
384 | REG(SYS_COUNT_TX_PMAC_64, 0x000298), |
385 | REG(SYS_COUNT_TX_PMAC_65_127, 0x00029c), |
386 | REG(SYS_COUNT_TX_PMAC_128_255, 0x0002a0), |
387 | REG(SYS_COUNT_TX_PMAC_256_511, 0x0002a4), |
388 | REG(SYS_COUNT_TX_PMAC_512_1023, 0x0002a8), |
389 | REG(SYS_COUNT_TX_PMAC_1024_1526, 0x0002ac), |
390 | REG(SYS_COUNT_TX_PMAC_1527_MAX, 0x0002b0), |
391 | REG(SYS_COUNT_DROP_LOCAL, 0x000400), |
392 | REG(SYS_COUNT_DROP_TAIL, 0x000404), |
393 | REG(SYS_COUNT_DROP_YELLOW_PRIO_0, 0x000408), |
394 | REG(SYS_COUNT_DROP_YELLOW_PRIO_1, 0x00040c), |
395 | REG(SYS_COUNT_DROP_YELLOW_PRIO_2, 0x000410), |
396 | REG(SYS_COUNT_DROP_YELLOW_PRIO_3, 0x000414), |
397 | REG(SYS_COUNT_DROP_YELLOW_PRIO_4, 0x000418), |
398 | REG(SYS_COUNT_DROP_YELLOW_PRIO_5, 0x00041c), |
399 | REG(SYS_COUNT_DROP_YELLOW_PRIO_6, 0x000420), |
400 | REG(SYS_COUNT_DROP_YELLOW_PRIO_7, 0x000424), |
401 | REG(SYS_COUNT_DROP_GREEN_PRIO_0, 0x000428), |
402 | REG(SYS_COUNT_DROP_GREEN_PRIO_1, 0x00042c), |
403 | REG(SYS_COUNT_DROP_GREEN_PRIO_2, 0x000430), |
404 | REG(SYS_COUNT_DROP_GREEN_PRIO_3, 0x000434), |
405 | REG(SYS_COUNT_DROP_GREEN_PRIO_4, 0x000438), |
406 | REG(SYS_COUNT_DROP_GREEN_PRIO_5, 0x00043c), |
407 | REG(SYS_COUNT_DROP_GREEN_PRIO_6, 0x000440), |
408 | REG(SYS_COUNT_DROP_GREEN_PRIO_7, 0x000444), |
409 | REG(SYS_COUNT_SF_MATCHING_FRAMES, 0x000800), |
410 | REG(SYS_COUNT_SF_NOT_PASSING_FRAMES, 0x000804), |
411 | REG(SYS_COUNT_SF_NOT_PASSING_SDU, 0x000808), |
412 | REG(SYS_COUNT_SF_RED_FRAMES, 0x00080c), |
413 | REG(SYS_RESET_CFG, 0x000e00), |
414 | REG(SYS_SR_ETYPE_CFG, 0x000e04), |
415 | REG(SYS_VLAN_ETYPE_CFG, 0x000e08), |
416 | REG(SYS_PORT_MODE, 0x000e0c), |
417 | REG(SYS_FRONT_PORT_MODE, 0x000e2c), |
418 | REG(SYS_FRM_AGING, 0x000e44), |
419 | REG(SYS_STAT_CFG, 0x000e48), |
420 | REG(SYS_SW_STATUS, 0x000e4c), |
421 | REG_RESERVED(SYS_MISC_CFG), |
422 | REG(SYS_REW_MAC_HIGH_CFG, 0x000e6c), |
423 | REG(SYS_REW_MAC_LOW_CFG, 0x000e84), |
424 | REG(SYS_TIMESTAMP_OFFSET, 0x000e9c), |
425 | REG(SYS_PAUSE_CFG, 0x000ea0), |
426 | REG(SYS_PAUSE_TOT_CFG, 0x000ebc), |
427 | REG(SYS_ATOP, 0x000ec0), |
428 | REG(SYS_ATOP_TOT_CFG, 0x000edc), |
429 | REG(SYS_MAC_FC_CFG, 0x000ee0), |
430 | REG(SYS_MMGT, 0x000ef8), |
431 | REG_RESERVED(SYS_MMGT_FAST), |
432 | REG_RESERVED(SYS_EVENTS_DIF), |
433 | REG_RESERVED(SYS_EVENTS_CORE), |
434 | REG(SYS_PTP_STATUS, 0x000f14), |
435 | REG(SYS_PTP_TXSTAMP, 0x000f18), |
436 | REG(SYS_PTP_NXT, 0x000f1c), |
437 | REG(SYS_PTP_CFG, 0x000f20), |
438 | REG(SYS_RAM_INIT, 0x000f24), |
439 | REG_RESERVED(SYS_CM_ADDR), |
440 | REG_RESERVED(SYS_CM_DATA_WR), |
441 | REG_RESERVED(SYS_CM_DATA_RD), |
442 | REG_RESERVED(SYS_CM_OP), |
443 | REG_RESERVED(SYS_CM_DATA), |
444 | }; |
445 | |
446 | static const u32 vsc9959_ptp_regmap[] = { |
447 | REG(PTP_PIN_CFG, 0x000000), |
448 | REG(PTP_PIN_TOD_SEC_MSB, 0x000004), |
449 | REG(PTP_PIN_TOD_SEC_LSB, 0x000008), |
450 | REG(PTP_PIN_TOD_NSEC, 0x00000c), |
451 | REG(PTP_PIN_WF_HIGH_PERIOD, 0x000014), |
452 | REG(PTP_PIN_WF_LOW_PERIOD, 0x000018), |
453 | REG(PTP_CFG_MISC, 0x0000a0), |
454 | REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4), |
455 | REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8), |
456 | }; |
457 | |
458 | static const u32 vsc9959_gcb_regmap[] = { |
459 | REG(GCB_SOFT_RST, 0x000004), |
460 | }; |
461 | |
462 | static const u32 vsc9959_dev_gmii_regmap[] = { |
463 | REG(DEV_CLOCK_CFG, 0x0), |
464 | REG(DEV_PORT_MISC, 0x4), |
465 | REG(DEV_EVENTS, 0x8), |
466 | REG(DEV_EEE_CFG, 0xc), |
467 | REG(DEV_RX_PATH_DELAY, 0x10), |
468 | REG(DEV_TX_PATH_DELAY, 0x14), |
469 | REG(DEV_PTP_PREDICT_CFG, 0x18), |
470 | REG(DEV_MAC_ENA_CFG, 0x1c), |
471 | REG(DEV_MAC_MODE_CFG, 0x20), |
472 | REG(DEV_MAC_MAXLEN_CFG, 0x24), |
473 | REG(DEV_MAC_TAGS_CFG, 0x28), |
474 | REG(DEV_MAC_ADV_CHK_CFG, 0x2c), |
475 | REG(DEV_MAC_IFG_CFG, 0x30), |
476 | REG(DEV_MAC_HDX_CFG, 0x34), |
477 | REG(DEV_MAC_DBG_CFG, 0x38), |
478 | REG(DEV_MAC_FC_MAC_LOW_CFG, 0x3c), |
479 | REG(DEV_MAC_FC_MAC_HIGH_CFG, 0x40), |
480 | REG(DEV_MAC_STICKY, 0x44), |
481 | REG(DEV_MM_ENABLE_CONFIG, 0x48), |
482 | REG(DEV_MM_VERIF_CONFIG, 0x4C), |
483 | REG(DEV_MM_STATUS, 0x50), |
484 | REG_RESERVED(PCS1G_CFG), |
485 | REG_RESERVED(PCS1G_MODE_CFG), |
486 | REG_RESERVED(PCS1G_SD_CFG), |
487 | REG_RESERVED(PCS1G_ANEG_CFG), |
488 | REG_RESERVED(PCS1G_ANEG_NP_CFG), |
489 | REG_RESERVED(PCS1G_LB_CFG), |
490 | REG_RESERVED(PCS1G_DBG_CFG), |
491 | REG_RESERVED(PCS1G_CDET_CFG), |
492 | REG_RESERVED(PCS1G_ANEG_STATUS), |
493 | REG_RESERVED(PCS1G_ANEG_NP_STATUS), |
494 | REG_RESERVED(PCS1G_LINK_STATUS), |
495 | REG_RESERVED(PCS1G_LINK_DOWN_CNT), |
496 | REG_RESERVED(PCS1G_STICKY), |
497 | REG_RESERVED(PCS1G_DEBUG_STATUS), |
498 | REG_RESERVED(PCS1G_LPI_CFG), |
499 | REG_RESERVED(PCS1G_LPI_WAKE_ERROR_CNT), |
500 | REG_RESERVED(PCS1G_LPI_STATUS), |
501 | REG_RESERVED(PCS1G_TSTPAT_MODE_CFG), |
502 | REG_RESERVED(PCS1G_TSTPAT_STATUS), |
503 | REG_RESERVED(DEV_PCS_FX100_CFG), |
504 | REG_RESERVED(DEV_PCS_FX100_STATUS), |
505 | }; |
506 | |
507 | static const u32 *vsc9959_regmap[TARGET_MAX] = { |
508 | [ANA] = vsc9959_ana_regmap, |
509 | [QS] = vsc9959_qs_regmap, |
510 | [QSYS] = vsc9959_qsys_regmap, |
511 | [REW] = vsc9959_rew_regmap, |
512 | [SYS] = vsc9959_sys_regmap, |
513 | [S0] = vsc9959_vcap_regmap, |
514 | [S1] = vsc9959_vcap_regmap, |
515 | [S2] = vsc9959_vcap_regmap, |
516 | [PTP] = vsc9959_ptp_regmap, |
517 | [GCB] = vsc9959_gcb_regmap, |
518 | [DEV_GMII] = vsc9959_dev_gmii_regmap, |
519 | }; |
520 | |
521 | /* Addresses are relative to the PCI device's base address */ |
522 | static const struct resource vsc9959_resources[] = { |
523 | DEFINE_RES_MEM_NAMED(0x0010000, 0x0010000, "sys" ), |
524 | DEFINE_RES_MEM_NAMED(0x0030000, 0x0010000, "rew" ), |
525 | DEFINE_RES_MEM_NAMED(0x0040000, 0x0000400, "s0" ), |
526 | DEFINE_RES_MEM_NAMED(0x0050000, 0x0000400, "s1" ), |
527 | DEFINE_RES_MEM_NAMED(0x0060000, 0x0000400, "s2" ), |
528 | DEFINE_RES_MEM_NAMED(0x0070000, 0x0000200, "devcpu_gcb" ), |
529 | DEFINE_RES_MEM_NAMED(0x0080000, 0x0000100, "qs" ), |
530 | DEFINE_RES_MEM_NAMED(0x0090000, 0x00000cc, "ptp" ), |
531 | DEFINE_RES_MEM_NAMED(0x0100000, 0x0010000, "port0" ), |
532 | DEFINE_RES_MEM_NAMED(0x0110000, 0x0010000, "port1" ), |
533 | DEFINE_RES_MEM_NAMED(0x0120000, 0x0010000, "port2" ), |
534 | DEFINE_RES_MEM_NAMED(0x0130000, 0x0010000, "port3" ), |
535 | DEFINE_RES_MEM_NAMED(0x0140000, 0x0010000, "port4" ), |
536 | DEFINE_RES_MEM_NAMED(0x0150000, 0x0010000, "port5" ), |
537 | DEFINE_RES_MEM_NAMED(0x0200000, 0x0020000, "qsys" ), |
538 | DEFINE_RES_MEM_NAMED(0x0280000, 0x0010000, "ana" ), |
539 | }; |
540 | |
541 | static const char * const vsc9959_resource_names[TARGET_MAX] = { |
542 | [SYS] = "sys" , |
543 | [REW] = "rew" , |
544 | [S0] = "s0" , |
545 | [S1] = "s1" , |
546 | [S2] = "s2" , |
547 | [GCB] = "devcpu_gcb" , |
548 | [QS] = "qs" , |
549 | [PTP] = "ptp" , |
550 | [QSYS] = "qsys" , |
551 | [ANA] = "ana" , |
552 | }; |
553 | |
554 | /* Port MAC 0 Internal MDIO bus through which the SerDes acting as an |
555 | * SGMII/QSGMII MAC PCS can be found. |
556 | */ |
557 | static const struct resource vsc9959_imdio_res = |
558 | DEFINE_RES_MEM_NAMED(0x8030, 0x10, "imdio" ); |
559 | |
560 | static const struct reg_field vsc9959_regfields[REGFIELD_MAX] = { |
561 | [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 6, 6), |
562 | [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 5), |
563 | [ANA_ANEVENTS_FLOOD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 30, 30), |
564 | [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 26, 26), |
565 | [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 24, 24), |
566 | [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 23, 23), |
567 | [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 22, 22), |
568 | [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 21, 21), |
569 | [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 20, 20), |
570 | [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 19, 19), |
571 | [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 18, 18), |
572 | [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 17, 17), |
573 | [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 15, 15), |
574 | [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 14, 14), |
575 | [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 13, 13), |
576 | [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 12, 12), |
577 | [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 11, 11), |
578 | [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 10, 10), |
579 | [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 9, 9), |
580 | [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 8, 8), |
581 | [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 7, 7), |
582 | [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6), |
583 | [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5), |
584 | [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 4, 4), |
585 | [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 3, 3), |
586 | [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 2, 2), |
587 | [ANA_ANEVENTS_SEQ_GEN_ERR_0] = REG_FIELD(ANA_ANEVENTS, 1, 1), |
588 | [ANA_ANEVENTS_SEQ_GEN_ERR_1] = REG_FIELD(ANA_ANEVENTS, 0, 0), |
589 | [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 16, 16), |
590 | [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 11, 12), |
591 | [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10), |
592 | [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 0, 0), |
593 | [GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0), |
594 | /* Replicated per number of ports (7), register size 4 per port */ |
595 | [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 7, 4), |
596 | [QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 7, 4), |
597 | [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 7, 4), |
598 | [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 7, 4), |
599 | [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 7, 4), |
600 | [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 7, 4), |
601 | [SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 7, 4), |
602 | [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 7, 4), |
603 | [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 7, 4), |
604 | [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 7, 4), |
605 | [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 7, 4), |
606 | [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 7, 4), |
607 | [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 7, 4), |
608 | }; |
609 | |
610 | static const struct vcap_field vsc9959_vcap_es0_keys[] = { |
611 | [VCAP_ES0_EGR_PORT] = { 0, 3}, |
612 | [VCAP_ES0_IGR_PORT] = { .offset: 3, .length: 3}, |
613 | [VCAP_ES0_RSV] = { .offset: 6, .length: 2}, |
614 | [VCAP_ES0_L2_MC] = { .offset: 8, .length: 1}, |
615 | [VCAP_ES0_L2_BC] = { .offset: 9, .length: 1}, |
616 | [VCAP_ES0_VID] = { .offset: 10, .length: 12}, |
617 | [VCAP_ES0_DP] = { .offset: 22, .length: 1}, |
618 | [VCAP_ES0_PCP] = { .offset: 23, .length: 3}, |
619 | }; |
620 | |
621 | static const struct vcap_field vsc9959_vcap_es0_actions[] = { |
622 | [VCAP_ES0_ACT_PUSH_OUTER_TAG] = { .offset: 0, .length: 2}, |
623 | [VCAP_ES0_ACT_PUSH_INNER_TAG] = { .offset: 2, .length: 1}, |
624 | [VCAP_ES0_ACT_TAG_A_TPID_SEL] = { .offset: 3, .length: 2}, |
625 | [VCAP_ES0_ACT_TAG_A_VID_SEL] = { .offset: 5, .length: 1}, |
626 | [VCAP_ES0_ACT_TAG_A_PCP_SEL] = { .offset: 6, .length: 2}, |
627 | [VCAP_ES0_ACT_TAG_A_DEI_SEL] = { .offset: 8, .length: 2}, |
628 | [VCAP_ES0_ACT_TAG_B_TPID_SEL] = { .offset: 10, .length: 2}, |
629 | [VCAP_ES0_ACT_TAG_B_VID_SEL] = { .offset: 12, .length: 1}, |
630 | [VCAP_ES0_ACT_TAG_B_PCP_SEL] = { .offset: 13, .length: 2}, |
631 | [VCAP_ES0_ACT_TAG_B_DEI_SEL] = { .offset: 15, .length: 2}, |
632 | [VCAP_ES0_ACT_VID_A_VAL] = { .offset: 17, .length: 12}, |
633 | [VCAP_ES0_ACT_PCP_A_VAL] = { .offset: 29, .length: 3}, |
634 | [VCAP_ES0_ACT_DEI_A_VAL] = { .offset: 32, .length: 1}, |
635 | [VCAP_ES0_ACT_VID_B_VAL] = { .offset: 33, .length: 12}, |
636 | [VCAP_ES0_ACT_PCP_B_VAL] = { .offset: 45, .length: 3}, |
637 | [VCAP_ES0_ACT_DEI_B_VAL] = { .offset: 48, .length: 1}, |
638 | [VCAP_ES0_ACT_RSV] = { .offset: 49, .length: 23}, |
639 | [VCAP_ES0_ACT_HIT_STICKY] = { .offset: 72, .length: 1}, |
640 | }; |
641 | |
642 | static const struct vcap_field vsc9959_vcap_is1_keys[] = { |
643 | [VCAP_IS1_HK_TYPE] = { .offset: 0, .length: 1}, |
644 | [VCAP_IS1_HK_LOOKUP] = { .offset: 1, .length: 2}, |
645 | [VCAP_IS1_HK_IGR_PORT_MASK] = { .offset: 3, .length: 7}, |
646 | [VCAP_IS1_HK_RSV] = { .offset: 10, .length: 9}, |
647 | [VCAP_IS1_HK_OAM_Y1731] = { .offset: 19, .length: 1}, |
648 | [VCAP_IS1_HK_L2_MC] = { .offset: 20, .length: 1}, |
649 | [VCAP_IS1_HK_L2_BC] = { .offset: 21, .length: 1}, |
650 | [VCAP_IS1_HK_IP_MC] = { .offset: 22, .length: 1}, |
651 | [VCAP_IS1_HK_VLAN_TAGGED] = { .offset: 23, .length: 1}, |
652 | [VCAP_IS1_HK_VLAN_DBL_TAGGED] = { .offset: 24, .length: 1}, |
653 | [VCAP_IS1_HK_TPID] = { .offset: 25, .length: 1}, |
654 | [VCAP_IS1_HK_VID] = { .offset: 26, .length: 12}, |
655 | [VCAP_IS1_HK_DEI] = { .offset: 38, .length: 1}, |
656 | [VCAP_IS1_HK_PCP] = { .offset: 39, .length: 3}, |
657 | /* Specific Fields for IS1 Half Key S1_NORMAL */ |
658 | [VCAP_IS1_HK_L2_SMAC] = { .offset: 42, .length: 48}, |
659 | [VCAP_IS1_HK_ETYPE_LEN] = { .offset: 90, .length: 1}, |
660 | [VCAP_IS1_HK_ETYPE] = { .offset: 91, .length: 16}, |
661 | [VCAP_IS1_HK_IP_SNAP] = {.offset: 107, .length: 1}, |
662 | [VCAP_IS1_HK_IP4] = {.offset: 108, .length: 1}, |
663 | /* Layer-3 Information */ |
664 | [VCAP_IS1_HK_L3_FRAGMENT] = {.offset: 109, .length: 1}, |
665 | [VCAP_IS1_HK_L3_FRAG_OFS_GT0] = {.offset: 110, .length: 1}, |
666 | [VCAP_IS1_HK_L3_OPTIONS] = {.offset: 111, .length: 1}, |
667 | [VCAP_IS1_HK_L3_DSCP] = {.offset: 112, .length: 6}, |
668 | [VCAP_IS1_HK_L3_IP4_SIP] = {.offset: 118, .length: 32}, |
669 | /* Layer-4 Information */ |
670 | [VCAP_IS1_HK_TCP_UDP] = {.offset: 150, .length: 1}, |
671 | [VCAP_IS1_HK_TCP] = {.offset: 151, .length: 1}, |
672 | [VCAP_IS1_HK_L4_SPORT] = {.offset: 152, .length: 16}, |
673 | [VCAP_IS1_HK_L4_RNG] = {.offset: 168, .length: 8}, |
674 | /* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */ |
675 | [VCAP_IS1_HK_IP4_INNER_TPID] = { .offset: 42, .length: 1}, |
676 | [VCAP_IS1_HK_IP4_INNER_VID] = { .offset: 43, .length: 12}, |
677 | [VCAP_IS1_HK_IP4_INNER_DEI] = { .offset: 55, .length: 1}, |
678 | [VCAP_IS1_HK_IP4_INNER_PCP] = { .offset: 56, .length: 3}, |
679 | [VCAP_IS1_HK_IP4_IP4] = { .offset: 59, .length: 1}, |
680 | [VCAP_IS1_HK_IP4_L3_FRAGMENT] = { .offset: 60, .length: 1}, |
681 | [VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0] = { .offset: 61, .length: 1}, |
682 | [VCAP_IS1_HK_IP4_L3_OPTIONS] = { .offset: 62, .length: 1}, |
683 | [VCAP_IS1_HK_IP4_L3_DSCP] = { .offset: 63, .length: 6}, |
684 | [VCAP_IS1_HK_IP4_L3_IP4_DIP] = { .offset: 69, .length: 32}, |
685 | [VCAP_IS1_HK_IP4_L3_IP4_SIP] = {.offset: 101, .length: 32}, |
686 | [VCAP_IS1_HK_IP4_L3_PROTO] = {.offset: 133, .length: 8}, |
687 | [VCAP_IS1_HK_IP4_TCP_UDP] = {.offset: 141, .length: 1}, |
688 | [VCAP_IS1_HK_IP4_TCP] = {.offset: 142, .length: 1}, |
689 | [VCAP_IS1_HK_IP4_L4_RNG] = {.offset: 143, .length: 8}, |
690 | [VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE] = {.offset: 151, .length: 32}, |
691 | }; |
692 | |
693 | static const struct vcap_field vsc9959_vcap_is1_actions[] = { |
694 | [VCAP_IS1_ACT_DSCP_ENA] = { .offset: 0, .length: 1}, |
695 | [VCAP_IS1_ACT_DSCP_VAL] = { .offset: 1, .length: 6}, |
696 | [VCAP_IS1_ACT_QOS_ENA] = { .offset: 7, .length: 1}, |
697 | [VCAP_IS1_ACT_QOS_VAL] = { .offset: 8, .length: 3}, |
698 | [VCAP_IS1_ACT_DP_ENA] = { .offset: 11, .length: 1}, |
699 | [VCAP_IS1_ACT_DP_VAL] = { .offset: 12, .length: 1}, |
700 | [VCAP_IS1_ACT_PAG_OVERRIDE_MASK] = { .offset: 13, .length: 8}, |
701 | [VCAP_IS1_ACT_PAG_VAL] = { .offset: 21, .length: 8}, |
702 | [VCAP_IS1_ACT_RSV] = { .offset: 29, .length: 9}, |
703 | /* The fields below are incorrectly shifted by 2 in the manual */ |
704 | [VCAP_IS1_ACT_VID_REPLACE_ENA] = { .offset: 38, .length: 1}, |
705 | [VCAP_IS1_ACT_VID_ADD_VAL] = { .offset: 39, .length: 12}, |
706 | [VCAP_IS1_ACT_FID_SEL] = { .offset: 51, .length: 2}, |
707 | [VCAP_IS1_ACT_FID_VAL] = { .offset: 53, .length: 13}, |
708 | [VCAP_IS1_ACT_PCP_DEI_ENA] = { .offset: 66, .length: 1}, |
709 | [VCAP_IS1_ACT_PCP_VAL] = { .offset: 67, .length: 3}, |
710 | [VCAP_IS1_ACT_DEI_VAL] = { .offset: 70, .length: 1}, |
711 | [VCAP_IS1_ACT_VLAN_POP_CNT_ENA] = { .offset: 71, .length: 1}, |
712 | [VCAP_IS1_ACT_VLAN_POP_CNT] = { .offset: 72, .length: 2}, |
713 | [VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA] = { .offset: 74, .length: 4}, |
714 | [VCAP_IS1_ACT_HIT_STICKY] = { .offset: 78, .length: 1}, |
715 | }; |
716 | |
717 | static struct vcap_field vsc9959_vcap_is2_keys[] = { |
718 | /* Common: 41 bits */ |
719 | [VCAP_IS2_TYPE] = { .offset: 0, .length: 4}, |
720 | [VCAP_IS2_HK_FIRST] = { .offset: 4, .length: 1}, |
721 | [VCAP_IS2_HK_PAG] = { .offset: 5, .length: 8}, |
722 | [VCAP_IS2_HK_IGR_PORT_MASK] = { .offset: 13, .length: 7}, |
723 | [VCAP_IS2_HK_RSV2] = { .offset: 20, .length: 1}, |
724 | [VCAP_IS2_HK_HOST_MATCH] = { .offset: 21, .length: 1}, |
725 | [VCAP_IS2_HK_L2_MC] = { .offset: 22, .length: 1}, |
726 | [VCAP_IS2_HK_L2_BC] = { .offset: 23, .length: 1}, |
727 | [VCAP_IS2_HK_VLAN_TAGGED] = { .offset: 24, .length: 1}, |
728 | [VCAP_IS2_HK_VID] = { .offset: 25, .length: 12}, |
729 | [VCAP_IS2_HK_DEI] = { .offset: 37, .length: 1}, |
730 | [VCAP_IS2_HK_PCP] = { .offset: 38, .length: 3}, |
731 | /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */ |
732 | [VCAP_IS2_HK_L2_DMAC] = { .offset: 41, .length: 48}, |
733 | [VCAP_IS2_HK_L2_SMAC] = { .offset: 89, .length: 48}, |
734 | /* MAC_ETYPE (TYPE=000) */ |
735 | [VCAP_IS2_HK_MAC_ETYPE_ETYPE] = {.offset: 137, .length: 16}, |
736 | [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0] = {.offset: 153, .length: 16}, |
737 | [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1] = {.offset: 169, .length: 8}, |
738 | [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2] = {.offset: 177, .length: 3}, |
739 | /* MAC_LLC (TYPE=001) */ |
740 | [VCAP_IS2_HK_MAC_LLC_L2_LLC] = {.offset: 137, .length: 40}, |
741 | /* MAC_SNAP (TYPE=010) */ |
742 | [VCAP_IS2_HK_MAC_SNAP_L2_SNAP] = {.offset: 137, .length: 40}, |
743 | /* MAC_ARP (TYPE=011) */ |
744 | [VCAP_IS2_HK_MAC_ARP_SMAC] = { .offset: 41, .length: 48}, |
745 | [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK] = { .offset: 89, .length: 1}, |
746 | [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK] = { .offset: 90, .length: 1}, |
747 | [VCAP_IS2_HK_MAC_ARP_LEN_OK] = { .offset: 91, .length: 1}, |
748 | [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH] = { .offset: 92, .length: 1}, |
749 | [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH] = { .offset: 93, .length: 1}, |
750 | [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN] = { .offset: 94, .length: 1}, |
751 | [VCAP_IS2_HK_MAC_ARP_OPCODE] = { .offset: 95, .length: 2}, |
752 | [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP] = { .offset: 97, .length: 32}, |
753 | [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP] = {.offset: 129, .length: 32}, |
754 | [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP] = {.offset: 161, .length: 1}, |
755 | /* IP4_TCP_UDP / IP4_OTHER common */ |
756 | [VCAP_IS2_HK_IP4] = { .offset: 41, .length: 1}, |
757 | [VCAP_IS2_HK_L3_FRAGMENT] = { .offset: 42, .length: 1}, |
758 | [VCAP_IS2_HK_L3_FRAG_OFS_GT0] = { .offset: 43, .length: 1}, |
759 | [VCAP_IS2_HK_L3_OPTIONS] = { .offset: 44, .length: 1}, |
760 | [VCAP_IS2_HK_IP4_L3_TTL_GT0] = { .offset: 45, .length: 1}, |
761 | [VCAP_IS2_HK_L3_TOS] = { .offset: 46, .length: 8}, |
762 | [VCAP_IS2_HK_L3_IP4_DIP] = { .offset: 54, .length: 32}, |
763 | [VCAP_IS2_HK_L3_IP4_SIP] = { .offset: 86, .length: 32}, |
764 | [VCAP_IS2_HK_DIP_EQ_SIP] = {.offset: 118, .length: 1}, |
765 | /* IP4_TCP_UDP (TYPE=100) */ |
766 | [VCAP_IS2_HK_TCP] = {.offset: 119, .length: 1}, |
767 | [VCAP_IS2_HK_L4_DPORT] = {.offset: 120, .length: 16}, |
768 | [VCAP_IS2_HK_L4_SPORT] = {.offset: 136, .length: 16}, |
769 | [VCAP_IS2_HK_L4_RNG] = {.offset: 152, .length: 8}, |
770 | [VCAP_IS2_HK_L4_SPORT_EQ_DPORT] = {.offset: 160, .length: 1}, |
771 | [VCAP_IS2_HK_L4_SEQUENCE_EQ0] = {.offset: 161, .length: 1}, |
772 | [VCAP_IS2_HK_L4_FIN] = {.offset: 162, .length: 1}, |
773 | [VCAP_IS2_HK_L4_SYN] = {.offset: 163, .length: 1}, |
774 | [VCAP_IS2_HK_L4_RST] = {.offset: 164, .length: 1}, |
775 | [VCAP_IS2_HK_L4_PSH] = {.offset: 165, .length: 1}, |
776 | [VCAP_IS2_HK_L4_ACK] = {.offset: 166, .length: 1}, |
777 | [VCAP_IS2_HK_L4_URG] = {.offset: 167, .length: 1}, |
778 | [VCAP_IS2_HK_L4_1588_DOM] = {.offset: 168, .length: 8}, |
779 | [VCAP_IS2_HK_L4_1588_VER] = {.offset: 176, .length: 4}, |
780 | /* IP4_OTHER (TYPE=101) */ |
781 | [VCAP_IS2_HK_IP4_L3_PROTO] = {.offset: 119, .length: 8}, |
782 | [VCAP_IS2_HK_L3_PAYLOAD] = {.offset: 127, .length: 56}, |
783 | /* IP6_STD (TYPE=110) */ |
784 | [VCAP_IS2_HK_IP6_L3_TTL_GT0] = { .offset: 41, .length: 1}, |
785 | [VCAP_IS2_HK_L3_IP6_SIP] = { .offset: 42, .length: 128}, |
786 | [VCAP_IS2_HK_IP6_L3_PROTO] = {.offset: 170, .length: 8}, |
787 | /* OAM (TYPE=111) */ |
788 | [VCAP_IS2_HK_OAM_MEL_FLAGS] = {.offset: 137, .length: 7}, |
789 | [VCAP_IS2_HK_OAM_VER] = {.offset: 144, .length: 5}, |
790 | [VCAP_IS2_HK_OAM_OPCODE] = {.offset: 149, .length: 8}, |
791 | [VCAP_IS2_HK_OAM_FLAGS] = {.offset: 157, .length: 8}, |
792 | [VCAP_IS2_HK_OAM_MEPID] = {.offset: 165, .length: 16}, |
793 | [VCAP_IS2_HK_OAM_CCM_CNTS_EQ0] = {.offset: 181, .length: 1}, |
794 | [VCAP_IS2_HK_OAM_IS_Y1731] = {.offset: 182, .length: 1}, |
795 | }; |
796 | |
797 | static struct vcap_field vsc9959_vcap_is2_actions[] = { |
798 | [VCAP_IS2_ACT_HIT_ME_ONCE] = { .offset: 0, .length: 1}, |
799 | [VCAP_IS2_ACT_CPU_COPY_ENA] = { .offset: 1, .length: 1}, |
800 | [VCAP_IS2_ACT_CPU_QU_NUM] = { .offset: 2, .length: 3}, |
801 | [VCAP_IS2_ACT_MASK_MODE] = { .offset: 5, .length: 2}, |
802 | [VCAP_IS2_ACT_MIRROR_ENA] = { .offset: 7, .length: 1}, |
803 | [VCAP_IS2_ACT_LRN_DIS] = { .offset: 8, .length: 1}, |
804 | [VCAP_IS2_ACT_POLICE_ENA] = { .offset: 9, .length: 1}, |
805 | [VCAP_IS2_ACT_POLICE_IDX] = { .offset: 10, .length: 9}, |
806 | [VCAP_IS2_ACT_POLICE_VCAP_ONLY] = { .offset: 19, .length: 1}, |
807 | [VCAP_IS2_ACT_PORT_MASK] = { .offset: 20, .length: 6}, |
808 | [VCAP_IS2_ACT_REW_OP] = { .offset: 26, .length: 9}, |
809 | [VCAP_IS2_ACT_SMAC_REPLACE_ENA] = { .offset: 35, .length: 1}, |
810 | [VCAP_IS2_ACT_RSV] = { .offset: 36, .length: 2}, |
811 | [VCAP_IS2_ACT_ACL_ID] = { .offset: 38, .length: 6}, |
812 | [VCAP_IS2_ACT_HIT_CNT] = { .offset: 44, .length: 32}, |
813 | }; |
814 | |
815 | static struct vcap_props vsc9959_vcap_props[] = { |
816 | [VCAP_ES0] = { |
817 | .action_type_width = 0, |
818 | .action_table = { |
819 | [ES0_ACTION_TYPE_NORMAL] = { |
820 | .width = 72, /* HIT_STICKY not included */ |
821 | .count = 1, |
822 | }, |
823 | }, |
824 | .target = S0, |
825 | .keys = vsc9959_vcap_es0_keys, |
826 | .actions = vsc9959_vcap_es0_actions, |
827 | }, |
828 | [VCAP_IS1] = { |
829 | .action_type_width = 0, |
830 | .action_table = { |
831 | [IS1_ACTION_TYPE_NORMAL] = { |
832 | .width = 78, /* HIT_STICKY not included */ |
833 | .count = 4, |
834 | }, |
835 | }, |
836 | .target = S1, |
837 | .keys = vsc9959_vcap_is1_keys, |
838 | .actions = vsc9959_vcap_is1_actions, |
839 | }, |
840 | [VCAP_IS2] = { |
841 | .action_type_width = 1, |
842 | .action_table = { |
843 | [IS2_ACTION_TYPE_NORMAL] = { |
844 | .width = 44, |
845 | .count = 2 |
846 | }, |
847 | [IS2_ACTION_TYPE_SMAC_SIP] = { |
848 | .width = 6, |
849 | .count = 4 |
850 | }, |
851 | }, |
852 | .target = S2, |
853 | .keys = vsc9959_vcap_is2_keys, |
854 | .actions = vsc9959_vcap_is2_actions, |
855 | }, |
856 | }; |
857 | |
858 | static const struct ptp_clock_info vsc9959_ptp_caps = { |
859 | .owner = THIS_MODULE, |
860 | .name = "felix ptp" , |
861 | .max_adj = 0x7fffffff, |
862 | .n_alarm = 0, |
863 | .n_ext_ts = 0, |
864 | .n_per_out = OCELOT_PTP_PINS_NUM, |
865 | .n_pins = OCELOT_PTP_PINS_NUM, |
866 | .pps = 0, |
867 | .gettime64 = ocelot_ptp_gettime64, |
868 | .settime64 = ocelot_ptp_settime64, |
869 | .adjtime = ocelot_ptp_adjtime, |
870 | .adjfine = ocelot_ptp_adjfine, |
871 | .verify = ocelot_ptp_verify, |
872 | .enable = ocelot_ptp_enable, |
873 | }; |
874 | |
875 | #define VSC9959_INIT_TIMEOUT 50000 |
876 | #define VSC9959_GCB_RST_SLEEP 100 |
877 | #define VSC9959_SYS_RAMINIT_SLEEP 80 |
878 | |
879 | static int vsc9959_gcb_soft_rst_status(struct ocelot *ocelot) |
880 | { |
881 | int val; |
882 | |
883 | ocelot_field_read(ocelot, GCB_SOFT_RST_SWC_RST, &val); |
884 | |
885 | return val; |
886 | } |
887 | |
888 | static int vsc9959_sys_ram_init_status(struct ocelot *ocelot) |
889 | { |
890 | return ocelot_read(ocelot, SYS_RAM_INIT); |
891 | } |
892 | |
893 | /* CORE_ENA is in SYS:SYSTEM:RESET_CFG |
894 | * RAM_INIT is in SYS:RAM_CTRL:RAM_INIT |
895 | */ |
896 | static int vsc9959_reset(struct ocelot *ocelot) |
897 | { |
898 | int val, err; |
899 | |
900 | /* soft-reset the switch core */ |
901 | ocelot_field_write(ocelot, GCB_SOFT_RST_SWC_RST, 1); |
902 | |
903 | err = readx_poll_timeout(vsc9959_gcb_soft_rst_status, ocelot, val, !val, |
904 | VSC9959_GCB_RST_SLEEP, VSC9959_INIT_TIMEOUT); |
905 | if (err) { |
906 | dev_err(ocelot->dev, "timeout: switch core reset\n" ); |
907 | return err; |
908 | } |
909 | |
910 | /* initialize switch mem ~40us */ |
911 | ocelot_write(ocelot, SYS_RAM_INIT_RAM_INIT, SYS_RAM_INIT); |
912 | err = readx_poll_timeout(vsc9959_sys_ram_init_status, ocelot, val, !val, |
913 | VSC9959_SYS_RAMINIT_SLEEP, |
914 | VSC9959_INIT_TIMEOUT); |
915 | if (err) { |
916 | dev_err(ocelot->dev, "timeout: switch sram init\n" ); |
917 | return err; |
918 | } |
919 | |
920 | /* enable switch core */ |
921 | ocelot_field_write(ocelot, SYS_RESET_CFG_CORE_ENA, 1); |
922 | |
923 | return 0; |
924 | } |
925 | |
926 | /* Watermark encode |
927 | * Bit 8: Unit; 0:1, 1:16 |
928 | * Bit 7-0: Value to be multiplied with unit |
929 | */ |
930 | static u16 vsc9959_wm_enc(u16 value) |
931 | { |
932 | WARN_ON(value >= 16 * BIT(8)); |
933 | |
934 | if (value >= BIT(8)) |
935 | return BIT(8) | (value / 16); |
936 | |
937 | return value; |
938 | } |
939 | |
940 | static u16 vsc9959_wm_dec(u16 wm) |
941 | { |
942 | WARN_ON(wm & ~GENMASK(8, 0)); |
943 | |
944 | if (wm & BIT(8)) |
945 | return (wm & GENMASK(7, 0)) * 16; |
946 | |
947 | return wm; |
948 | } |
949 | |
950 | static void vsc9959_wm_stat(u32 val, u32 *inuse, u32 *maxuse) |
951 | { |
952 | *inuse = (val & GENMASK(23, 12)) >> 12; |
953 | *maxuse = val & GENMASK(11, 0); |
954 | } |
955 | |
956 | static int vsc9959_mdio_bus_alloc(struct ocelot *ocelot) |
957 | { |
958 | struct pci_dev *pdev = to_pci_dev(ocelot->dev); |
959 | struct felix *felix = ocelot_to_felix(ocelot); |
960 | struct enetc_mdio_priv *mdio_priv; |
961 | struct device *dev = ocelot->dev; |
962 | resource_size_t imdio_base; |
963 | void __iomem *imdio_regs; |
964 | struct resource res; |
965 | struct enetc_hw *hw; |
966 | struct mii_bus *bus; |
967 | int port; |
968 | int rc; |
969 | |
970 | felix->pcs = devm_kcalloc(dev, n: felix->info->num_ports, |
971 | size: sizeof(struct phylink_pcs *), |
972 | GFP_KERNEL); |
973 | if (!felix->pcs) { |
974 | dev_err(dev, "failed to allocate array for PCS PHYs\n" ); |
975 | return -ENOMEM; |
976 | } |
977 | |
978 | imdio_base = pci_resource_start(pdev, VSC9959_IMDIO_PCI_BAR); |
979 | |
980 | memcpy(&res, &vsc9959_imdio_res, sizeof(res)); |
981 | res.start += imdio_base; |
982 | res.end += imdio_base; |
983 | |
984 | imdio_regs = devm_ioremap_resource(dev, res: &res); |
985 | if (IS_ERR(ptr: imdio_regs)) |
986 | return PTR_ERR(ptr: imdio_regs); |
987 | |
988 | hw = enetc_hw_alloc(dev, port_regs: imdio_regs); |
989 | if (IS_ERR(ptr: hw)) { |
990 | dev_err(dev, "failed to allocate ENETC HW structure\n" ); |
991 | return PTR_ERR(ptr: hw); |
992 | } |
993 | |
994 | bus = mdiobus_alloc_size(size: sizeof(*mdio_priv)); |
995 | if (!bus) |
996 | return -ENOMEM; |
997 | |
998 | bus->name = "VSC9959 internal MDIO bus" ; |
999 | bus->read = enetc_mdio_read_c22; |
1000 | bus->write = enetc_mdio_write_c22; |
1001 | bus->read_c45 = enetc_mdio_read_c45; |
1002 | bus->write_c45 = enetc_mdio_write_c45; |
1003 | bus->parent = dev; |
1004 | mdio_priv = bus->priv; |
1005 | mdio_priv->hw = hw; |
1006 | /* This gets added to imdio_regs, which already maps addresses |
1007 | * starting with the proper offset. |
1008 | */ |
1009 | mdio_priv->mdio_base = 0; |
1010 | snprintf(buf: bus->id, MII_BUS_ID_SIZE, fmt: "%s-imdio" , dev_name(dev)); |
1011 | |
1012 | /* Needed in order to initialize the bus mutex lock */ |
1013 | rc = mdiobus_register(bus); |
1014 | if (rc < 0) { |
1015 | dev_err(dev, "failed to register MDIO bus\n" ); |
1016 | mdiobus_free(bus); |
1017 | return rc; |
1018 | } |
1019 | |
1020 | felix->imdio = bus; |
1021 | |
1022 | for (port = 0; port < felix->info->num_ports; port++) { |
1023 | struct ocelot_port *ocelot_port = ocelot->ports[port]; |
1024 | struct phylink_pcs *phylink_pcs; |
1025 | |
1026 | if (dsa_is_unused_port(ds: felix->ds, p: port)) |
1027 | continue; |
1028 | |
1029 | if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_INTERNAL) |
1030 | continue; |
1031 | |
1032 | phylink_pcs = lynx_pcs_create_mdiodev(bus: felix->imdio, addr: port); |
1033 | if (IS_ERR(ptr: phylink_pcs)) |
1034 | continue; |
1035 | |
1036 | felix->pcs[port] = phylink_pcs; |
1037 | |
1038 | dev_info(dev, "Found PCS at internal MDIO address %d\n" , port); |
1039 | } |
1040 | |
1041 | return 0; |
1042 | } |
1043 | |
1044 | static void vsc9959_mdio_bus_free(struct ocelot *ocelot) |
1045 | { |
1046 | struct felix *felix = ocelot_to_felix(ocelot); |
1047 | int port; |
1048 | |
1049 | for (port = 0; port < ocelot->num_phys_ports; port++) { |
1050 | struct phylink_pcs *phylink_pcs = felix->pcs[port]; |
1051 | |
1052 | if (phylink_pcs) |
1053 | lynx_pcs_destroy(pcs: phylink_pcs); |
1054 | } |
1055 | mdiobus_unregister(bus: felix->imdio); |
1056 | mdiobus_free(bus: felix->imdio); |
1057 | } |
1058 | |
1059 | /* The switch considers any frame (regardless of size) as eligible for |
1060 | * transmission if the traffic class gate is open for at least 33 ns. |
1061 | * Overruns are prevented by cropping an interval at the end of the gate time |
1062 | * slot for which egress scheduling is blocked, but we need to still keep 33 ns |
1063 | * available for one packet to be transmitted, otherwise the port tc will hang. |
1064 | * This function returns the size of a gate interval that remains available for |
1065 | * setting the guard band, after reserving the space for one egress frame. |
1066 | */ |
1067 | static u64 vsc9959_tas_remaining_gate_len_ps(u64 gate_len_ns) |
1068 | { |
1069 | /* Gate always open */ |
1070 | if (gate_len_ns == U64_MAX) |
1071 | return U64_MAX; |
1072 | |
1073 | if (gate_len_ns < VSC9959_TAS_MIN_GATE_LEN_NS) |
1074 | return 0; |
1075 | |
1076 | return (gate_len_ns - VSC9959_TAS_MIN_GATE_LEN_NS) * PSEC_PER_NSEC; |
1077 | } |
1078 | |
1079 | /* Extract shortest continuous gate open intervals in ns for each traffic class |
1080 | * of a cyclic tc-taprio schedule. If a gate is always open, the duration is |
1081 | * considered U64_MAX. If the gate is always closed, it is considered 0. |
1082 | */ |
1083 | static void vsc9959_tas_min_gate_lengths(struct tc_taprio_qopt_offload *taprio, |
1084 | u64 min_gate_len[OCELOT_NUM_TC]) |
1085 | { |
1086 | struct tc_taprio_sched_entry *entry; |
1087 | u64 gate_len[OCELOT_NUM_TC]; |
1088 | u8 gates_ever_opened = 0; |
1089 | int tc, i, n; |
1090 | |
1091 | /* Initialize arrays */ |
1092 | for (tc = 0; tc < OCELOT_NUM_TC; tc++) { |
1093 | min_gate_len[tc] = U64_MAX; |
1094 | gate_len[tc] = 0; |
1095 | } |
1096 | |
1097 | /* If we don't have taprio, consider all gates as permanently open */ |
1098 | if (!taprio) |
1099 | return; |
1100 | |
1101 | n = taprio->num_entries; |
1102 | |
1103 | /* Walk through the gate list twice to determine the length |
1104 | * of consecutively open gates for a traffic class, including |
1105 | * open gates that wrap around. We are just interested in the |
1106 | * minimum window size, and this doesn't change what the |
1107 | * minimum is (if the gate never closes, min_gate_len will |
1108 | * remain U64_MAX). |
1109 | */ |
1110 | for (i = 0; i < 2 * n; i++) { |
1111 | entry = &taprio->entries[i % n]; |
1112 | |
1113 | for (tc = 0; tc < OCELOT_NUM_TC; tc++) { |
1114 | if (entry->gate_mask & BIT(tc)) { |
1115 | gate_len[tc] += entry->interval; |
1116 | gates_ever_opened |= BIT(tc); |
1117 | } else { |
1118 | /* Gate closes now, record a potential new |
1119 | * minimum and reinitialize length |
1120 | */ |
1121 | if (min_gate_len[tc] > gate_len[tc] && |
1122 | gate_len[tc]) |
1123 | min_gate_len[tc] = gate_len[tc]; |
1124 | gate_len[tc] = 0; |
1125 | } |
1126 | } |
1127 | } |
1128 | |
1129 | /* min_gate_len[tc] actually tracks minimum *open* gate time, so for |
1130 | * permanently closed gates, min_gate_len[tc] will still be U64_MAX. |
1131 | * Therefore they are currently indistinguishable from permanently |
1132 | * open gates. Overwrite the gate len with 0 when we know they're |
1133 | * actually permanently closed, i.e. after the loop above. |
1134 | */ |
1135 | for (tc = 0; tc < OCELOT_NUM_TC; tc++) |
1136 | if (!(gates_ever_opened & BIT(tc))) |
1137 | min_gate_len[tc] = 0; |
1138 | } |
1139 | |
1140 | /* ocelot_write_rix is a macro that concatenates QSYS_MAXSDU_CFG_* with _RSZ, |
1141 | * so we need to spell out the register access to each traffic class in helper |
1142 | * functions, to simplify callers |
1143 | */ |
1144 | static void vsc9959_port_qmaxsdu_set(struct ocelot *ocelot, int port, int tc, |
1145 | u32 max_sdu) |
1146 | { |
1147 | switch (tc) { |
1148 | case 0: |
1149 | ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_0, |
1150 | port); |
1151 | break; |
1152 | case 1: |
1153 | ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_1, |
1154 | port); |
1155 | break; |
1156 | case 2: |
1157 | ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_2, |
1158 | port); |
1159 | break; |
1160 | case 3: |
1161 | ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_3, |
1162 | port); |
1163 | break; |
1164 | case 4: |
1165 | ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_4, |
1166 | port); |
1167 | break; |
1168 | case 5: |
1169 | ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_5, |
1170 | port); |
1171 | break; |
1172 | case 6: |
1173 | ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_6, |
1174 | port); |
1175 | break; |
1176 | case 7: |
1177 | ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_7, |
1178 | port); |
1179 | break; |
1180 | } |
1181 | } |
1182 | |
1183 | static u32 vsc9959_port_qmaxsdu_get(struct ocelot *ocelot, int port, int tc) |
1184 | { |
1185 | switch (tc) { |
1186 | case 0: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_0, port); |
1187 | case 1: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_1, port); |
1188 | case 2: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_2, port); |
1189 | case 3: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_3, port); |
1190 | case 4: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_4, port); |
1191 | case 5: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_5, port); |
1192 | case 6: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_6, port); |
1193 | case 7: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_7, port); |
1194 | default: |
1195 | return 0; |
1196 | } |
1197 | } |
1198 | |
1199 | static u32 vsc9959_tas_tc_max_sdu(struct tc_taprio_qopt_offload *taprio, int tc) |
1200 | { |
1201 | if (!taprio || !taprio->max_sdu[tc]) |
1202 | return 0; |
1203 | |
1204 | return taprio->max_sdu[tc] + ETH_HLEN + 2 * VLAN_HLEN + ETH_FCS_LEN; |
1205 | } |
1206 | |
1207 | /* Update QSYS_PORT_MAX_SDU to make sure the static guard bands added by the |
1208 | * switch (see the ALWAYS_GUARD_BAND_SCH_Q comment) are correct at all MTU |
1209 | * values (the default value is 1518). Also, for traffic class windows smaller |
1210 | * than one MTU sized frame, update QSYS_QMAXSDU_CFG to enable oversized frame |
1211 | * dropping, such that these won't hang the port, as they will never be sent. |
1212 | */ |
1213 | static void vsc9959_tas_guard_bands_update(struct ocelot *ocelot, int port) |
1214 | { |
1215 | struct ocelot_port *ocelot_port = ocelot->ports[port]; |
1216 | struct ocelot_mm_state *mm = &ocelot->mm[port]; |
1217 | struct tc_taprio_qopt_offload *taprio; |
1218 | u64 min_gate_len[OCELOT_NUM_TC]; |
1219 | u32 val, maxlen, add_frag_size; |
1220 | u64 needed_min_frag_time_ps; |
1221 | int speed, picos_per_byte; |
1222 | u64 needed_bit_time_ps; |
1223 | u8 tas_speed; |
1224 | int tc; |
1225 | |
1226 | lockdep_assert_held(&ocelot->fwd_domain_lock); |
1227 | |
1228 | taprio = ocelot_port->taprio; |
1229 | |
1230 | val = ocelot_read_rix(ocelot, QSYS_TAG_CONFIG, port); |
1231 | tas_speed = QSYS_TAG_CONFIG_LINK_SPEED_X(val); |
1232 | |
1233 | switch (tas_speed) { |
1234 | case OCELOT_SPEED_10: |
1235 | speed = SPEED_10; |
1236 | break; |
1237 | case OCELOT_SPEED_100: |
1238 | speed = SPEED_100; |
1239 | break; |
1240 | case OCELOT_SPEED_1000: |
1241 | speed = SPEED_1000; |
1242 | break; |
1243 | case OCELOT_SPEED_2500: |
1244 | speed = SPEED_2500; |
1245 | break; |
1246 | default: |
1247 | return; |
1248 | } |
1249 | |
1250 | picos_per_byte = (USEC_PER_SEC * 8) / speed; |
1251 | |
1252 | val = ocelot_port_readl(port: ocelot_port, reg: DEV_MAC_MAXLEN_CFG); |
1253 | /* MAXLEN_CFG accounts automatically for VLAN. We need to include it |
1254 | * manually in the bit time calculation, plus the preamble and SFD. |
1255 | */ |
1256 | maxlen = val + 2 * VLAN_HLEN; |
1257 | /* Consider the standard Ethernet overhead of 8 octets preamble+SFD, |
1258 | * 4 octets FCS, 12 octets IFG. |
1259 | */ |
1260 | needed_bit_time_ps = (u64)(maxlen + 24) * picos_per_byte; |
1261 | |
1262 | /* Preemptible TCs don't need to pass a full MTU, the port will |
1263 | * automatically emit a HOLD request when a preemptible TC gate closes |
1264 | */ |
1265 | val = ocelot_read_rix(ocelot, QSYS_PREEMPTION_CFG, port); |
1266 | add_frag_size = QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE_X(val); |
1267 | needed_min_frag_time_ps = picos_per_byte * |
1268 | (u64)(24 + 2 * ethtool_mm_frag_size_add_to_min(val_add: add_frag_size)); |
1269 | |
1270 | dev_dbg(ocelot->dev, |
1271 | "port %d: max frame size %d needs %llu ps, %llu ps for mPackets at speed %d\n" , |
1272 | port, maxlen, needed_bit_time_ps, needed_min_frag_time_ps, |
1273 | speed); |
1274 | |
1275 | vsc9959_tas_min_gate_lengths(taprio, min_gate_len); |
1276 | |
1277 | for (tc = 0; tc < OCELOT_NUM_TC; tc++) { |
1278 | u32 requested_max_sdu = vsc9959_tas_tc_max_sdu(taprio, tc); |
1279 | u64 remaining_gate_len_ps; |
1280 | u32 max_sdu; |
1281 | |
1282 | remaining_gate_len_ps = |
1283 | vsc9959_tas_remaining_gate_len_ps(gate_len_ns: min_gate_len[tc]); |
1284 | |
1285 | if ((mm->active_preemptible_tcs & BIT(tc)) ? |
1286 | remaining_gate_len_ps > needed_min_frag_time_ps : |
1287 | remaining_gate_len_ps > needed_bit_time_ps) { |
1288 | /* Setting QMAXSDU_CFG to 0 disables oversized frame |
1289 | * dropping. |
1290 | */ |
1291 | max_sdu = requested_max_sdu; |
1292 | dev_dbg(ocelot->dev, |
1293 | "port %d tc %d min gate len %llu" |
1294 | ", sending all frames\n" , |
1295 | port, tc, min_gate_len[tc]); |
1296 | } else { |
1297 | /* If traffic class doesn't support a full MTU sized |
1298 | * frame, make sure to enable oversize frame dropping |
1299 | * for frames larger than the smallest that would fit. |
1300 | * |
1301 | * However, the exact same register, QSYS_QMAXSDU_CFG_*, |
1302 | * controls not only oversized frame dropping, but also |
1303 | * per-tc static guard band lengths, so it reduces the |
1304 | * useful gate interval length. Therefore, be careful |
1305 | * to calculate a guard band (and therefore max_sdu) |
1306 | * that still leaves 33 ns available in the time slot. |
1307 | */ |
1308 | max_sdu = div_u64(dividend: remaining_gate_len_ps, divisor: picos_per_byte); |
1309 | /* A TC gate may be completely closed, which is a |
1310 | * special case where all packets are oversized. |
1311 | * Any limit smaller than 64 octets accomplishes this |
1312 | */ |
1313 | if (!max_sdu) |
1314 | max_sdu = 1; |
1315 | /* Take L1 overhead into account, but just don't allow |
1316 | * max_sdu to go negative or to 0. Here we use 20 |
1317 | * because QSYS_MAXSDU_CFG_* already counts the 4 FCS |
1318 | * octets as part of packet size. |
1319 | */ |
1320 | if (max_sdu > 20) |
1321 | max_sdu -= 20; |
1322 | |
1323 | if (requested_max_sdu && requested_max_sdu < max_sdu) |
1324 | max_sdu = requested_max_sdu; |
1325 | |
1326 | dev_info(ocelot->dev, |
1327 | "port %d tc %d min gate length %llu" |
1328 | " ns not enough for max frame size %d at %d" |
1329 | " Mbps, dropping frames over %d" |
1330 | " octets including FCS\n" , |
1331 | port, tc, min_gate_len[tc], maxlen, speed, |
1332 | max_sdu); |
1333 | } |
1334 | |
1335 | vsc9959_port_qmaxsdu_set(ocelot, port, tc, max_sdu); |
1336 | } |
1337 | |
1338 | ocelot_write_rix(ocelot, maxlen, QSYS_PORT_MAX_SDU, port); |
1339 | |
1340 | ocelot->ops->cut_through_fwd(ocelot); |
1341 | } |
1342 | |
1343 | static void vsc9959_sched_speed_set(struct ocelot *ocelot, int port, |
1344 | u32 speed) |
1345 | { |
1346 | struct ocelot_port *ocelot_port = ocelot->ports[port]; |
1347 | u8 tas_speed; |
1348 | |
1349 | switch (speed) { |
1350 | case SPEED_10: |
1351 | tas_speed = OCELOT_SPEED_10; |
1352 | break; |
1353 | case SPEED_100: |
1354 | tas_speed = OCELOT_SPEED_100; |
1355 | break; |
1356 | case SPEED_1000: |
1357 | tas_speed = OCELOT_SPEED_1000; |
1358 | break; |
1359 | case SPEED_2500: |
1360 | tas_speed = OCELOT_SPEED_2500; |
1361 | break; |
1362 | default: |
1363 | tas_speed = OCELOT_SPEED_1000; |
1364 | break; |
1365 | } |
1366 | |
1367 | mutex_lock(&ocelot->fwd_domain_lock); |
1368 | |
1369 | ocelot_rmw_rix(ocelot, |
1370 | QSYS_TAG_CONFIG_LINK_SPEED(tas_speed), |
1371 | QSYS_TAG_CONFIG_LINK_SPEED_M, |
1372 | QSYS_TAG_CONFIG, port); |
1373 | |
1374 | if (ocelot_port->taprio) |
1375 | vsc9959_tas_guard_bands_update(ocelot, port); |
1376 | |
1377 | mutex_unlock(lock: &ocelot->fwd_domain_lock); |
1378 | } |
1379 | |
1380 | static void vsc9959_new_base_time(struct ocelot *ocelot, ktime_t base_time, |
1381 | u64 cycle_time, |
1382 | struct timespec64 *new_base_ts) |
1383 | { |
1384 | struct timespec64 ts; |
1385 | ktime_t new_base_time; |
1386 | ktime_t current_time; |
1387 | |
1388 | ocelot_ptp_gettime64(ptp: &ocelot->ptp_info, ts: &ts); |
1389 | current_time = timespec64_to_ktime(ts); |
1390 | new_base_time = base_time; |
1391 | |
1392 | if (base_time < current_time) { |
1393 | u64 nr_of_cycles = current_time - base_time; |
1394 | |
1395 | do_div(nr_of_cycles, cycle_time); |
1396 | new_base_time += cycle_time * (nr_of_cycles + 1); |
1397 | } |
1398 | |
1399 | *new_base_ts = ktime_to_timespec64(new_base_time); |
1400 | } |
1401 | |
1402 | static u32 vsc9959_tas_read_cfg_status(struct ocelot *ocelot) |
1403 | { |
1404 | return ocelot_read(ocelot, QSYS_TAS_PARAM_CFG_CTRL); |
1405 | } |
1406 | |
1407 | static void vsc9959_tas_gcl_set(struct ocelot *ocelot, const u32 gcl_ix, |
1408 | struct tc_taprio_sched_entry *entry) |
1409 | { |
1410 | ocelot_write(ocelot, |
1411 | QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM(gcl_ix) | |
1412 | QSYS_GCL_CFG_REG_1_GATE_STATE(entry->gate_mask), |
1413 | QSYS_GCL_CFG_REG_1); |
1414 | ocelot_write(ocelot, entry->interval, QSYS_GCL_CFG_REG_2); |
1415 | } |
1416 | |
1417 | static int vsc9959_qos_port_tas_set(struct ocelot *ocelot, int port, |
1418 | struct tc_taprio_qopt_offload *taprio) |
1419 | { |
1420 | struct ocelot_port *ocelot_port = ocelot->ports[port]; |
1421 | struct timespec64 base_ts; |
1422 | int ret, i; |
1423 | u32 val; |
1424 | |
1425 | mutex_lock(&ocelot->fwd_domain_lock); |
1426 | |
1427 | if (taprio->cmd == TAPRIO_CMD_DESTROY) { |
1428 | ocelot_port_mqprio(ocelot, port, mqprio: &taprio->mqprio); |
1429 | ocelot_rmw_rix(ocelot, 0, QSYS_TAG_CONFIG_ENABLE, |
1430 | QSYS_TAG_CONFIG, port); |
1431 | |
1432 | taprio_offload_free(offload: ocelot_port->taprio); |
1433 | ocelot_port->taprio = NULL; |
1434 | |
1435 | vsc9959_tas_guard_bands_update(ocelot, port); |
1436 | |
1437 | mutex_unlock(lock: &ocelot->fwd_domain_lock); |
1438 | return 0; |
1439 | } else if (taprio->cmd != TAPRIO_CMD_REPLACE) { |
1440 | ret = -EOPNOTSUPP; |
1441 | goto err_unlock; |
1442 | } |
1443 | |
1444 | ret = ocelot_port_mqprio(ocelot, port, mqprio: &taprio->mqprio); |
1445 | if (ret) |
1446 | goto err_unlock; |
1447 | |
1448 | if (taprio->cycle_time > NSEC_PER_SEC || |
1449 | taprio->cycle_time_extension >= NSEC_PER_SEC) { |
1450 | ret = -EINVAL; |
1451 | goto err_reset_tc; |
1452 | } |
1453 | |
1454 | if (taprio->num_entries > VSC9959_TAS_GCL_ENTRY_MAX) { |
1455 | ret = -ERANGE; |
1456 | goto err_reset_tc; |
1457 | } |
1458 | |
1459 | /* Enable guard band. The switch will schedule frames without taking |
1460 | * their length into account. Thus we'll always need to enable the |
1461 | * guard band which reserves the time of a maximum sized frame at the |
1462 | * end of the time window. |
1463 | * |
1464 | * Although the ALWAYS_GUARD_BAND_SCH_Q bit is global for all ports, we |
1465 | * need to set PORT_NUM, because subsequent writes to PARAM_CFG_REG_n |
1466 | * operate on the port number. |
1467 | */ |
1468 | ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port) | |
1469 | QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q, |
1470 | QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M | |
1471 | QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q, |
1472 | QSYS_TAS_PARAM_CFG_CTRL); |
1473 | |
1474 | /* Hardware errata - Admin config could not be overwritten if |
1475 | * config is pending, need reset the TAS module |
1476 | */ |
1477 | val = ocelot_read(ocelot, QSYS_PARAM_STATUS_REG_8); |
1478 | if (val & QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING) { |
1479 | ret = -EBUSY; |
1480 | goto err_reset_tc; |
1481 | } |
1482 | |
1483 | ocelot_rmw_rix(ocelot, |
1484 | QSYS_TAG_CONFIG_ENABLE | |
1485 | QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF) | |
1486 | QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(0xFF), |
1487 | QSYS_TAG_CONFIG_ENABLE | |
1488 | QSYS_TAG_CONFIG_INIT_GATE_STATE_M | |
1489 | QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_M, |
1490 | QSYS_TAG_CONFIG, port); |
1491 | |
1492 | vsc9959_new_base_time(ocelot, base_time: taprio->base_time, |
1493 | cycle_time: taprio->cycle_time, new_base_ts: &base_ts); |
1494 | ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1); |
1495 | ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec), QSYS_PARAM_CFG_REG_2); |
1496 | val = upper_32_bits(base_ts.tv_sec); |
1497 | ocelot_write(ocelot, |
1498 | QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val) | |
1499 | QSYS_PARAM_CFG_REG_3_LIST_LENGTH(taprio->num_entries), |
1500 | QSYS_PARAM_CFG_REG_3); |
1501 | ocelot_write(ocelot, taprio->cycle_time, QSYS_PARAM_CFG_REG_4); |
1502 | ocelot_write(ocelot, taprio->cycle_time_extension, QSYS_PARAM_CFG_REG_5); |
1503 | |
1504 | for (i = 0; i < taprio->num_entries; i++) |
1505 | vsc9959_tas_gcl_set(ocelot, gcl_ix: i, entry: &taprio->entries[i]); |
1506 | |
1507 | ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, |
1508 | QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, |
1509 | QSYS_TAS_PARAM_CFG_CTRL); |
1510 | |
1511 | ret = readx_poll_timeout(vsc9959_tas_read_cfg_status, ocelot, val, |
1512 | !(val & QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE), |
1513 | 10, 100000); |
1514 | if (ret) |
1515 | goto err_reset_tc; |
1516 | |
1517 | ocelot_port->taprio = taprio_offload_get(offload: taprio); |
1518 | vsc9959_tas_guard_bands_update(ocelot, port); |
1519 | |
1520 | mutex_unlock(lock: &ocelot->fwd_domain_lock); |
1521 | |
1522 | return 0; |
1523 | |
1524 | err_reset_tc: |
1525 | taprio->mqprio.qopt.num_tc = 0; |
1526 | ocelot_port_mqprio(ocelot, port, mqprio: &taprio->mqprio); |
1527 | err_unlock: |
1528 | mutex_unlock(lock: &ocelot->fwd_domain_lock); |
1529 | |
1530 | return ret; |
1531 | } |
1532 | |
1533 | static void vsc9959_tas_clock_adjust(struct ocelot *ocelot) |
1534 | { |
1535 | struct tc_taprio_qopt_offload *taprio; |
1536 | struct ocelot_port *ocelot_port; |
1537 | struct timespec64 base_ts; |
1538 | int port; |
1539 | u32 val; |
1540 | |
1541 | mutex_lock(&ocelot->fwd_domain_lock); |
1542 | |
1543 | for (port = 0; port < ocelot->num_phys_ports; port++) { |
1544 | ocelot_port = ocelot->ports[port]; |
1545 | taprio = ocelot_port->taprio; |
1546 | if (!taprio) |
1547 | continue; |
1548 | |
1549 | ocelot_rmw(ocelot, |
1550 | QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port), |
1551 | QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M, |
1552 | QSYS_TAS_PARAM_CFG_CTRL); |
1553 | |
1554 | /* Disable time-aware shaper */ |
1555 | ocelot_rmw_rix(ocelot, 0, QSYS_TAG_CONFIG_ENABLE, |
1556 | QSYS_TAG_CONFIG, port); |
1557 | |
1558 | vsc9959_new_base_time(ocelot, base_time: taprio->base_time, |
1559 | cycle_time: taprio->cycle_time, new_base_ts: &base_ts); |
1560 | |
1561 | ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1); |
1562 | ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec), |
1563 | QSYS_PARAM_CFG_REG_2); |
1564 | val = upper_32_bits(base_ts.tv_sec); |
1565 | ocelot_rmw(ocelot, |
1566 | QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val), |
1567 | QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB_M, |
1568 | QSYS_PARAM_CFG_REG_3); |
1569 | |
1570 | ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, |
1571 | QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, |
1572 | QSYS_TAS_PARAM_CFG_CTRL); |
1573 | |
1574 | /* Re-enable time-aware shaper */ |
1575 | ocelot_rmw_rix(ocelot, QSYS_TAG_CONFIG_ENABLE, |
1576 | QSYS_TAG_CONFIG_ENABLE, |
1577 | QSYS_TAG_CONFIG, port); |
1578 | } |
1579 | mutex_unlock(lock: &ocelot->fwd_domain_lock); |
1580 | } |
1581 | |
1582 | static int vsc9959_qos_port_cbs_set(struct dsa_switch *ds, int port, |
1583 | struct tc_cbs_qopt_offload *cbs_qopt) |
1584 | { |
1585 | struct ocelot *ocelot = ds->priv; |
1586 | int port_ix = port * 8 + cbs_qopt->queue; |
1587 | u32 rate, burst; |
1588 | |
1589 | if (cbs_qopt->queue >= ds->num_tx_queues) |
1590 | return -EINVAL; |
1591 | |
1592 | if (!cbs_qopt->enable) { |
1593 | ocelot_write_gix(ocelot, QSYS_CIR_CFG_CIR_RATE(0) | |
1594 | QSYS_CIR_CFG_CIR_BURST(0), |
1595 | QSYS_CIR_CFG, port_ix); |
1596 | |
1597 | ocelot_rmw_gix(ocelot, 0, QSYS_SE_CFG_SE_AVB_ENA, |
1598 | QSYS_SE_CFG, port_ix); |
1599 | |
1600 | return 0; |
1601 | } |
1602 | |
1603 | /* Rate unit is 100 kbps */ |
1604 | rate = DIV_ROUND_UP(cbs_qopt->idleslope, 100); |
1605 | /* Avoid using zero rate */ |
1606 | rate = clamp_t(u32, rate, 1, GENMASK(14, 0)); |
1607 | /* Burst unit is 4kB */ |
1608 | burst = DIV_ROUND_UP(cbs_qopt->hicredit, 4096); |
1609 | /* Avoid using zero burst size */ |
1610 | burst = clamp_t(u32, burst, 1, GENMASK(5, 0)); |
1611 | ocelot_write_gix(ocelot, |
1612 | QSYS_CIR_CFG_CIR_RATE(rate) | |
1613 | QSYS_CIR_CFG_CIR_BURST(burst), |
1614 | QSYS_CIR_CFG, |
1615 | port_ix); |
1616 | |
1617 | ocelot_rmw_gix(ocelot, |
1618 | QSYS_SE_CFG_SE_FRM_MODE(0) | |
1619 | QSYS_SE_CFG_SE_AVB_ENA, |
1620 | QSYS_SE_CFG_SE_AVB_ENA | |
1621 | QSYS_SE_CFG_SE_FRM_MODE_M, |
1622 | QSYS_SE_CFG, |
1623 | port_ix); |
1624 | |
1625 | return 0; |
1626 | } |
1627 | |
1628 | static int vsc9959_qos_query_caps(struct tc_query_caps_base *base) |
1629 | { |
1630 | switch (base->type) { |
1631 | case TC_SETUP_QDISC_MQPRIO: { |
1632 | struct tc_mqprio_caps *caps = base->caps; |
1633 | |
1634 | caps->validate_queue_counts = true; |
1635 | |
1636 | return 0; |
1637 | } |
1638 | case TC_SETUP_QDISC_TAPRIO: { |
1639 | struct tc_taprio_caps *caps = base->caps; |
1640 | |
1641 | caps->supports_queue_max_sdu = true; |
1642 | |
1643 | return 0; |
1644 | } |
1645 | default: |
1646 | return -EOPNOTSUPP; |
1647 | } |
1648 | } |
1649 | |
1650 | static int vsc9959_qos_port_mqprio(struct ocelot *ocelot, int port, |
1651 | struct tc_mqprio_qopt_offload *mqprio) |
1652 | { |
1653 | int ret; |
1654 | |
1655 | mutex_lock(&ocelot->fwd_domain_lock); |
1656 | ret = ocelot_port_mqprio(ocelot, port, mqprio); |
1657 | mutex_unlock(lock: &ocelot->fwd_domain_lock); |
1658 | |
1659 | return ret; |
1660 | } |
1661 | |
1662 | static int vsc9959_port_setup_tc(struct dsa_switch *ds, int port, |
1663 | enum tc_setup_type type, |
1664 | void *type_data) |
1665 | { |
1666 | struct ocelot *ocelot = ds->priv; |
1667 | |
1668 | switch (type) { |
1669 | case TC_QUERY_CAPS: |
1670 | return vsc9959_qos_query_caps(base: type_data); |
1671 | case TC_SETUP_QDISC_TAPRIO: |
1672 | return vsc9959_qos_port_tas_set(ocelot, port, taprio: type_data); |
1673 | case TC_SETUP_QDISC_MQPRIO: |
1674 | return vsc9959_qos_port_mqprio(ocelot, port, mqprio: type_data); |
1675 | case TC_SETUP_QDISC_CBS: |
1676 | return vsc9959_qos_port_cbs_set(ds, port, cbs_qopt: type_data); |
1677 | default: |
1678 | return -EOPNOTSUPP; |
1679 | } |
1680 | } |
1681 | |
1682 | #define VSC9959_PSFP_SFID_MAX 175 |
1683 | #define VSC9959_PSFP_GATE_ID_MAX 183 |
1684 | #define VSC9959_PSFP_POLICER_BASE 63 |
1685 | #define VSC9959_PSFP_POLICER_MAX 383 |
1686 | #define VSC9959_PSFP_GATE_LIST_NUM 4 |
1687 | #define VSC9959_PSFP_GATE_CYCLETIME_MIN 5000 |
1688 | |
1689 | struct felix_stream { |
1690 | struct list_head list; |
1691 | unsigned long id; |
1692 | bool dummy; |
1693 | int ports; |
1694 | int port; |
1695 | u8 dmac[ETH_ALEN]; |
1696 | u16 vid; |
1697 | s8 prio; |
1698 | u8 sfid_valid; |
1699 | u8 ssid_valid; |
1700 | u32 sfid; |
1701 | u32 ssid; |
1702 | }; |
1703 | |
1704 | struct felix_stream_filter_counters { |
1705 | u64 match; |
1706 | u64 not_pass_gate; |
1707 | u64 not_pass_sdu; |
1708 | u64 red; |
1709 | }; |
1710 | |
1711 | struct felix_stream_filter { |
1712 | struct felix_stream_filter_counters stats; |
1713 | struct list_head list; |
1714 | refcount_t refcount; |
1715 | u32 index; |
1716 | u8 enable; |
1717 | int portmask; |
1718 | u8 sg_valid; |
1719 | u32 sgid; |
1720 | u8 fm_valid; |
1721 | u32 fmid; |
1722 | u8 prio_valid; |
1723 | u8 prio; |
1724 | u32 maxsdu; |
1725 | }; |
1726 | |
1727 | struct felix_stream_gate { |
1728 | u32 index; |
1729 | u8 enable; |
1730 | u8 ipv_valid; |
1731 | u8 init_ipv; |
1732 | u64 basetime; |
1733 | u64 cycletime; |
1734 | u64 cycletime_ext; |
1735 | u32 num_entries; |
1736 | struct action_gate_entry entries[]; |
1737 | }; |
1738 | |
1739 | struct felix_stream_gate_entry { |
1740 | struct list_head list; |
1741 | refcount_t refcount; |
1742 | u32 index; |
1743 | }; |
1744 | |
1745 | static int vsc9959_stream_identify(struct flow_cls_offload *f, |
1746 | struct felix_stream *stream) |
1747 | { |
1748 | struct flow_rule *rule = flow_cls_offload_flow_rule(flow_cmd: f); |
1749 | struct flow_dissector *dissector = rule->match.dissector; |
1750 | |
1751 | if (dissector->used_keys & |
1752 | ~(BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) | |
1753 | BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) | |
1754 | BIT_ULL(FLOW_DISSECTOR_KEY_VLAN) | |
1755 | BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS))) |
1756 | return -EOPNOTSUPP; |
1757 | |
1758 | if (flow_rule_match_key(rule, key: FLOW_DISSECTOR_KEY_ETH_ADDRS)) { |
1759 | struct flow_match_eth_addrs match; |
1760 | |
1761 | flow_rule_match_eth_addrs(rule, out: &match); |
1762 | ether_addr_copy(dst: stream->dmac, src: match.key->dst); |
1763 | if (!is_zero_ether_addr(addr: match.mask->src)) |
1764 | return -EOPNOTSUPP; |
1765 | } else { |
1766 | return -EOPNOTSUPP; |
1767 | } |
1768 | |
1769 | if (flow_rule_match_key(rule, key: FLOW_DISSECTOR_KEY_VLAN)) { |
1770 | struct flow_match_vlan match; |
1771 | |
1772 | flow_rule_match_vlan(rule, out: &match); |
1773 | if (match.mask->vlan_priority) |
1774 | stream->prio = match.key->vlan_priority; |
1775 | else |
1776 | stream->prio = -1; |
1777 | |
1778 | if (!match.mask->vlan_id) |
1779 | return -EOPNOTSUPP; |
1780 | stream->vid = match.key->vlan_id; |
1781 | } else { |
1782 | return -EOPNOTSUPP; |
1783 | } |
1784 | |
1785 | stream->id = f->cookie; |
1786 | |
1787 | return 0; |
1788 | } |
1789 | |
1790 | static int vsc9959_mact_stream_set(struct ocelot *ocelot, |
1791 | struct felix_stream *stream, |
1792 | struct netlink_ext_ack *extack) |
1793 | { |
1794 | enum macaccess_entry_type type; |
1795 | int ret, sfid, ssid; |
1796 | u32 vid, dst_idx; |
1797 | u8 mac[ETH_ALEN]; |
1798 | |
1799 | ether_addr_copy(dst: mac, src: stream->dmac); |
1800 | vid = stream->vid; |
1801 | |
1802 | /* Stream identification desn't support to add a stream with non |
1803 | * existent MAC (The MAC entry has not been learned in MAC table). |
1804 | */ |
1805 | ret = ocelot_mact_lookup(ocelot, dst_idx: &dst_idx, mac, vid, type: &type); |
1806 | if (ret) { |
1807 | if (extack) |
1808 | NL_SET_ERR_MSG_MOD(extack, "Stream is not learned in MAC table" ); |
1809 | return -EOPNOTSUPP; |
1810 | } |
1811 | |
1812 | if ((stream->sfid_valid || stream->ssid_valid) && |
1813 | type == ENTRYTYPE_NORMAL) |
1814 | type = ENTRYTYPE_LOCKED; |
1815 | |
1816 | sfid = stream->sfid_valid ? stream->sfid : -1; |
1817 | ssid = stream->ssid_valid ? stream->ssid : -1; |
1818 | |
1819 | ret = ocelot_mact_learn_streamdata(ocelot, dst_idx, mac, vid, type, |
1820 | sfid, ssid); |
1821 | |
1822 | return ret; |
1823 | } |
1824 | |
1825 | static struct felix_stream * |
1826 | vsc9959_stream_table_lookup(struct list_head *stream_list, |
1827 | struct felix_stream *stream) |
1828 | { |
1829 | struct felix_stream *tmp; |
1830 | |
1831 | list_for_each_entry(tmp, stream_list, list) |
1832 | if (ether_addr_equal(addr1: tmp->dmac, addr2: stream->dmac) && |
1833 | tmp->vid == stream->vid) |
1834 | return tmp; |
1835 | |
1836 | return NULL; |
1837 | } |
1838 | |
1839 | static int vsc9959_stream_table_add(struct ocelot *ocelot, |
1840 | struct list_head *stream_list, |
1841 | struct felix_stream *stream, |
1842 | struct netlink_ext_ack *extack) |
1843 | { |
1844 | struct felix_stream *stream_entry; |
1845 | int ret; |
1846 | |
1847 | stream_entry = kmemdup(p: stream, size: sizeof(*stream_entry), GFP_KERNEL); |
1848 | if (!stream_entry) |
1849 | return -ENOMEM; |
1850 | |
1851 | if (!stream->dummy) { |
1852 | ret = vsc9959_mact_stream_set(ocelot, stream: stream_entry, extack); |
1853 | if (ret) { |
1854 | kfree(objp: stream_entry); |
1855 | return ret; |
1856 | } |
1857 | } |
1858 | |
1859 | list_add_tail(new: &stream_entry->list, head: stream_list); |
1860 | |
1861 | return 0; |
1862 | } |
1863 | |
1864 | static struct felix_stream * |
1865 | vsc9959_stream_table_get(struct list_head *stream_list, unsigned long id) |
1866 | { |
1867 | struct felix_stream *tmp; |
1868 | |
1869 | list_for_each_entry(tmp, stream_list, list) |
1870 | if (tmp->id == id) |
1871 | return tmp; |
1872 | |
1873 | return NULL; |
1874 | } |
1875 | |
1876 | static void vsc9959_stream_table_del(struct ocelot *ocelot, |
1877 | struct felix_stream *stream) |
1878 | { |
1879 | if (!stream->dummy) |
1880 | vsc9959_mact_stream_set(ocelot, stream, NULL); |
1881 | |
1882 | list_del(entry: &stream->list); |
1883 | kfree(objp: stream); |
1884 | } |
1885 | |
1886 | static u32 vsc9959_sfi_access_status(struct ocelot *ocelot) |
1887 | { |
1888 | return ocelot_read(ocelot, ANA_TABLES_SFIDACCESS); |
1889 | } |
1890 | |
1891 | static int vsc9959_psfp_sfi_set(struct ocelot *ocelot, |
1892 | struct felix_stream_filter *sfi) |
1893 | { |
1894 | u32 val; |
1895 | |
1896 | if (sfi->index > VSC9959_PSFP_SFID_MAX) |
1897 | return -EINVAL; |
1898 | |
1899 | if (!sfi->enable) { |
1900 | ocelot_write(ocelot, ANA_TABLES_SFIDTIDX_SFID_INDEX(sfi->index), |
1901 | ANA_TABLES_SFIDTIDX); |
1902 | |
1903 | val = ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE); |
1904 | ocelot_write(ocelot, val, ANA_TABLES_SFIDACCESS); |
1905 | |
1906 | return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val, |
1907 | (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)), |
1908 | 10, 100000); |
1909 | } |
1910 | |
1911 | if (sfi->sgid > VSC9959_PSFP_GATE_ID_MAX || |
1912 | sfi->fmid > VSC9959_PSFP_POLICER_MAX) |
1913 | return -EINVAL; |
1914 | |
1915 | ocelot_write(ocelot, |
1916 | (sfi->sg_valid ? ANA_TABLES_SFIDTIDX_SGID_VALID : 0) | |
1917 | ANA_TABLES_SFIDTIDX_SGID(sfi->sgid) | |
1918 | (sfi->fm_valid ? ANA_TABLES_SFIDTIDX_POL_ENA : 0) | |
1919 | ANA_TABLES_SFIDTIDX_POL_IDX(sfi->fmid) | |
1920 | ANA_TABLES_SFIDTIDX_SFID_INDEX(sfi->index), |
1921 | ANA_TABLES_SFIDTIDX); |
1922 | |
1923 | ocelot_write(ocelot, |
1924 | (sfi->prio_valid ? ANA_TABLES_SFIDACCESS_IGR_PRIO_MATCH_ENA : 0) | |
1925 | ANA_TABLES_SFIDACCESS_IGR_PRIO(sfi->prio) | |
1926 | ANA_TABLES_SFIDACCESS_MAX_SDU_LEN(sfi->maxsdu) | |
1927 | ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE), |
1928 | ANA_TABLES_SFIDACCESS); |
1929 | |
1930 | return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val, |
1931 | (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)), |
1932 | 10, 100000); |
1933 | } |
1934 | |
1935 | static int vsc9959_psfp_sfidmask_set(struct ocelot *ocelot, u32 sfid, int ports) |
1936 | { |
1937 | u32 val; |
1938 | |
1939 | ocelot_rmw(ocelot, |
1940 | ANA_TABLES_SFIDTIDX_SFID_INDEX(sfid), |
1941 | ANA_TABLES_SFIDTIDX_SFID_INDEX_M, |
1942 | ANA_TABLES_SFIDTIDX); |
1943 | |
1944 | ocelot_write(ocelot, |
1945 | ANA_TABLES_SFID_MASK_IGR_PORT_MASK(ports) | |
1946 | ANA_TABLES_SFID_MASK_IGR_SRCPORT_MATCH_ENA, |
1947 | ANA_TABLES_SFID_MASK); |
1948 | |
1949 | ocelot_rmw(ocelot, |
1950 | ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE), |
1951 | ANA_TABLES_SFIDACCESS_SFID_TBL_CMD_M, |
1952 | ANA_TABLES_SFIDACCESS); |
1953 | |
1954 | return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val, |
1955 | (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)), |
1956 | 10, 100000); |
1957 | } |
1958 | |
1959 | static int vsc9959_psfp_sfi_list_add(struct ocelot *ocelot, |
1960 | struct felix_stream_filter *sfi, |
1961 | struct list_head *pos) |
1962 | { |
1963 | struct felix_stream_filter *sfi_entry; |
1964 | int ret; |
1965 | |
1966 | sfi_entry = kmemdup(p: sfi, size: sizeof(*sfi_entry), GFP_KERNEL); |
1967 | if (!sfi_entry) |
1968 | return -ENOMEM; |
1969 | |
1970 | refcount_set(r: &sfi_entry->refcount, n: 1); |
1971 | |
1972 | ret = vsc9959_psfp_sfi_set(ocelot, sfi: sfi_entry); |
1973 | if (ret) { |
1974 | kfree(objp: sfi_entry); |
1975 | return ret; |
1976 | } |
1977 | |
1978 | vsc9959_psfp_sfidmask_set(ocelot, sfid: sfi->index, ports: sfi->portmask); |
1979 | |
1980 | list_add(new: &sfi_entry->list, head: pos); |
1981 | |
1982 | return 0; |
1983 | } |
1984 | |
1985 | static int vsc9959_psfp_sfi_table_add(struct ocelot *ocelot, |
1986 | struct felix_stream_filter *sfi) |
1987 | { |
1988 | struct list_head *pos, *q, *last; |
1989 | struct felix_stream_filter *tmp; |
1990 | struct ocelot_psfp_list *psfp; |
1991 | u32 insert = 0; |
1992 | |
1993 | psfp = &ocelot->psfp; |
1994 | last = &psfp->sfi_list; |
1995 | |
1996 | list_for_each_safe(pos, q, &psfp->sfi_list) { |
1997 | tmp = list_entry(pos, struct felix_stream_filter, list); |
1998 | if (sfi->sg_valid == tmp->sg_valid && |
1999 | sfi->fm_valid == tmp->fm_valid && |
2000 | sfi->portmask == tmp->portmask && |
2001 | tmp->sgid == sfi->sgid && |
2002 | tmp->fmid == sfi->fmid) { |
2003 | sfi->index = tmp->index; |
2004 | refcount_inc(r: &tmp->refcount); |
2005 | return 0; |
2006 | } |
2007 | /* Make sure that the index is increasing in order. */ |
2008 | if (tmp->index == insert) { |
2009 | last = pos; |
2010 | insert++; |
2011 | } |
2012 | } |
2013 | sfi->index = insert; |
2014 | |
2015 | return vsc9959_psfp_sfi_list_add(ocelot, sfi, pos: last); |
2016 | } |
2017 | |
2018 | static int vsc9959_psfp_sfi_table_add2(struct ocelot *ocelot, |
2019 | struct felix_stream_filter *sfi, |
2020 | struct felix_stream_filter *sfi2) |
2021 | { |
2022 | struct felix_stream_filter *tmp; |
2023 | struct list_head *pos, *q, *last; |
2024 | struct ocelot_psfp_list *psfp; |
2025 | u32 insert = 0; |
2026 | int ret; |
2027 | |
2028 | psfp = &ocelot->psfp; |
2029 | last = &psfp->sfi_list; |
2030 | |
2031 | list_for_each_safe(pos, q, &psfp->sfi_list) { |
2032 | tmp = list_entry(pos, struct felix_stream_filter, list); |
2033 | /* Make sure that the index is increasing in order. */ |
2034 | if (tmp->index >= insert + 2) |
2035 | break; |
2036 | |
2037 | insert = tmp->index + 1; |
2038 | last = pos; |
2039 | } |
2040 | sfi->index = insert; |
2041 | |
2042 | ret = vsc9959_psfp_sfi_list_add(ocelot, sfi, pos: last); |
2043 | if (ret) |
2044 | return ret; |
2045 | |
2046 | sfi2->index = insert + 1; |
2047 | |
2048 | return vsc9959_psfp_sfi_list_add(ocelot, sfi: sfi2, pos: last->next); |
2049 | } |
2050 | |
2051 | static struct felix_stream_filter * |
2052 | vsc9959_psfp_sfi_table_get(struct list_head *sfi_list, u32 index) |
2053 | { |
2054 | struct felix_stream_filter *tmp; |
2055 | |
2056 | list_for_each_entry(tmp, sfi_list, list) |
2057 | if (tmp->index == index) |
2058 | return tmp; |
2059 | |
2060 | return NULL; |
2061 | } |
2062 | |
2063 | static void vsc9959_psfp_sfi_table_del(struct ocelot *ocelot, u32 index) |
2064 | { |
2065 | struct felix_stream_filter *tmp, *n; |
2066 | struct ocelot_psfp_list *psfp; |
2067 | u8 z; |
2068 | |
2069 | psfp = &ocelot->psfp; |
2070 | |
2071 | list_for_each_entry_safe(tmp, n, &psfp->sfi_list, list) |
2072 | if (tmp->index == index) { |
2073 | z = refcount_dec_and_test(r: &tmp->refcount); |
2074 | if (z) { |
2075 | tmp->enable = 0; |
2076 | vsc9959_psfp_sfi_set(ocelot, sfi: tmp); |
2077 | list_del(entry: &tmp->list); |
2078 | kfree(objp: tmp); |
2079 | } |
2080 | break; |
2081 | } |
2082 | } |
2083 | |
2084 | static void vsc9959_psfp_parse_gate(const struct flow_action_entry *entry, |
2085 | struct felix_stream_gate *sgi) |
2086 | { |
2087 | sgi->index = entry->hw_index; |
2088 | sgi->ipv_valid = (entry->gate.prio < 0) ? 0 : 1; |
2089 | sgi->init_ipv = (sgi->ipv_valid) ? entry->gate.prio : 0; |
2090 | sgi->basetime = entry->gate.basetime; |
2091 | sgi->cycletime = entry->gate.cycletime; |
2092 | sgi->num_entries = entry->gate.num_entries; |
2093 | sgi->enable = 1; |
2094 | |
2095 | memcpy(sgi->entries, entry->gate.entries, |
2096 | entry->gate.num_entries * sizeof(struct action_gate_entry)); |
2097 | } |
2098 | |
2099 | static u32 vsc9959_sgi_cfg_status(struct ocelot *ocelot) |
2100 | { |
2101 | return ocelot_read(ocelot, ANA_SG_ACCESS_CTRL); |
2102 | } |
2103 | |
2104 | static int vsc9959_psfp_sgi_set(struct ocelot *ocelot, |
2105 | struct felix_stream_gate *sgi) |
2106 | { |
2107 | struct action_gate_entry *e; |
2108 | struct timespec64 base_ts; |
2109 | u32 interval_sum = 0; |
2110 | u32 val; |
2111 | int i; |
2112 | |
2113 | if (sgi->index > VSC9959_PSFP_GATE_ID_MAX) |
2114 | return -EINVAL; |
2115 | |
2116 | ocelot_write(ocelot, ANA_SG_ACCESS_CTRL_SGID(sgi->index), |
2117 | ANA_SG_ACCESS_CTRL); |
2118 | |
2119 | if (!sgi->enable) { |
2120 | ocelot_rmw(ocelot, ANA_SG_CONFIG_REG_3_INIT_GATE_STATE, |
2121 | ANA_SG_CONFIG_REG_3_INIT_GATE_STATE | |
2122 | ANA_SG_CONFIG_REG_3_GATE_ENABLE, |
2123 | ANA_SG_CONFIG_REG_3); |
2124 | |
2125 | return 0; |
2126 | } |
2127 | |
2128 | if (sgi->cycletime < VSC9959_PSFP_GATE_CYCLETIME_MIN || |
2129 | sgi->cycletime > NSEC_PER_SEC) |
2130 | return -EINVAL; |
2131 | |
2132 | if (sgi->num_entries > VSC9959_PSFP_GATE_LIST_NUM) |
2133 | return -EINVAL; |
2134 | |
2135 | vsc9959_new_base_time(ocelot, base_time: sgi->basetime, cycle_time: sgi->cycletime, new_base_ts: &base_ts); |
2136 | ocelot_write(ocelot, base_ts.tv_nsec, ANA_SG_CONFIG_REG_1); |
2137 | val = lower_32_bits(base_ts.tv_sec); |
2138 | ocelot_write(ocelot, val, ANA_SG_CONFIG_REG_2); |
2139 | |
2140 | val = upper_32_bits(base_ts.tv_sec); |
2141 | ocelot_write(ocelot, |
2142 | (sgi->ipv_valid ? ANA_SG_CONFIG_REG_3_IPV_VALID : 0) | |
2143 | ANA_SG_CONFIG_REG_3_INIT_IPV(sgi->init_ipv) | |
2144 | ANA_SG_CONFIG_REG_3_GATE_ENABLE | |
2145 | ANA_SG_CONFIG_REG_3_LIST_LENGTH(sgi->num_entries) | |
2146 | ANA_SG_CONFIG_REG_3_INIT_GATE_STATE | |
2147 | ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB(val), |
2148 | ANA_SG_CONFIG_REG_3); |
2149 | |
2150 | ocelot_write(ocelot, sgi->cycletime, ANA_SG_CONFIG_REG_4); |
2151 | |
2152 | e = sgi->entries; |
2153 | for (i = 0; i < sgi->num_entries; i++) { |
2154 | u32 ips = (e[i].ipv < 0) ? 0 : (e[i].ipv + 8); |
2155 | |
2156 | ocelot_write_rix(ocelot, ANA_SG_GCL_GS_CONFIG_IPS(ips) | |
2157 | (e[i].gate_state ? |
2158 | ANA_SG_GCL_GS_CONFIG_GATE_STATE : 0), |
2159 | ANA_SG_GCL_GS_CONFIG, i); |
2160 | |
2161 | interval_sum += e[i].interval; |
2162 | ocelot_write_rix(ocelot, interval_sum, ANA_SG_GCL_TI_CONFIG, i); |
2163 | } |
2164 | |
2165 | ocelot_rmw(ocelot, ANA_SG_ACCESS_CTRL_CONFIG_CHANGE, |
2166 | ANA_SG_ACCESS_CTRL_CONFIG_CHANGE, |
2167 | ANA_SG_ACCESS_CTRL); |
2168 | |
2169 | return readx_poll_timeout(vsc9959_sgi_cfg_status, ocelot, val, |
2170 | (!(ANA_SG_ACCESS_CTRL_CONFIG_CHANGE & val)), |
2171 | 10, 100000); |
2172 | } |
2173 | |
2174 | static int vsc9959_psfp_sgi_table_add(struct ocelot *ocelot, |
2175 | struct felix_stream_gate *sgi) |
2176 | { |
2177 | struct felix_stream_gate_entry *tmp; |
2178 | struct ocelot_psfp_list *psfp; |
2179 | int ret; |
2180 | |
2181 | psfp = &ocelot->psfp; |
2182 | |
2183 | list_for_each_entry(tmp, &psfp->sgi_list, list) |
2184 | if (tmp->index == sgi->index) { |
2185 | refcount_inc(r: &tmp->refcount); |
2186 | return 0; |
2187 | } |
2188 | |
2189 | tmp = kzalloc(size: sizeof(*tmp), GFP_KERNEL); |
2190 | if (!tmp) |
2191 | return -ENOMEM; |
2192 | |
2193 | ret = vsc9959_psfp_sgi_set(ocelot, sgi); |
2194 | if (ret) { |
2195 | kfree(objp: tmp); |
2196 | return ret; |
2197 | } |
2198 | |
2199 | tmp->index = sgi->index; |
2200 | refcount_set(r: &tmp->refcount, n: 1); |
2201 | list_add_tail(new: &tmp->list, head: &psfp->sgi_list); |
2202 | |
2203 | return 0; |
2204 | } |
2205 | |
2206 | static void vsc9959_psfp_sgi_table_del(struct ocelot *ocelot, |
2207 | u32 index) |
2208 | { |
2209 | struct felix_stream_gate_entry *tmp, *n; |
2210 | struct felix_stream_gate sgi = {0}; |
2211 | struct ocelot_psfp_list *psfp; |
2212 | u8 z; |
2213 | |
2214 | psfp = &ocelot->psfp; |
2215 | |
2216 | list_for_each_entry_safe(tmp, n, &psfp->sgi_list, list) |
2217 | if (tmp->index == index) { |
2218 | z = refcount_dec_and_test(r: &tmp->refcount); |
2219 | if (z) { |
2220 | sgi.index = index; |
2221 | sgi.enable = 0; |
2222 | vsc9959_psfp_sgi_set(ocelot, sgi: &sgi); |
2223 | list_del(entry: &tmp->list); |
2224 | kfree(objp: tmp); |
2225 | } |
2226 | break; |
2227 | } |
2228 | } |
2229 | |
2230 | static int vsc9959_psfp_filter_add(struct ocelot *ocelot, int port, |
2231 | struct flow_cls_offload *f) |
2232 | { |
2233 | struct netlink_ext_ack *extack = f->common.extack; |
2234 | struct felix_stream_filter old_sfi, *sfi_entry; |
2235 | struct felix_stream_filter sfi = {0}; |
2236 | const struct flow_action_entry *a; |
2237 | struct felix_stream *stream_entry; |
2238 | struct felix_stream stream = {0}; |
2239 | struct felix_stream_gate *sgi; |
2240 | struct ocelot_psfp_list *psfp; |
2241 | struct ocelot_policer pol; |
2242 | int ret, i, size; |
2243 | u64 rate, burst; |
2244 | u32 index; |
2245 | |
2246 | psfp = &ocelot->psfp; |
2247 | |
2248 | ret = vsc9959_stream_identify(f, stream: &stream); |
2249 | if (ret) { |
2250 | NL_SET_ERR_MSG_MOD(extack, "Only can match on VID, PCP, and dest MAC" ); |
2251 | return ret; |
2252 | } |
2253 | |
2254 | mutex_lock(&psfp->lock); |
2255 | |
2256 | flow_action_for_each(i, a, &f->rule->action) { |
2257 | switch (a->id) { |
2258 | case FLOW_ACTION_GATE: |
2259 | size = struct_size(sgi, entries, a->gate.num_entries); |
2260 | sgi = kzalloc(size, GFP_KERNEL); |
2261 | if (!sgi) { |
2262 | ret = -ENOMEM; |
2263 | goto err; |
2264 | } |
2265 | vsc9959_psfp_parse_gate(entry: a, sgi); |
2266 | ret = vsc9959_psfp_sgi_table_add(ocelot, sgi); |
2267 | if (ret) { |
2268 | kfree(objp: sgi); |
2269 | goto err; |
2270 | } |
2271 | sfi.sg_valid = 1; |
2272 | sfi.sgid = sgi->index; |
2273 | kfree(objp: sgi); |
2274 | break; |
2275 | case FLOW_ACTION_POLICE: |
2276 | index = a->hw_index + VSC9959_PSFP_POLICER_BASE; |
2277 | if (index > VSC9959_PSFP_POLICER_MAX) { |
2278 | ret = -EINVAL; |
2279 | goto err; |
2280 | } |
2281 | |
2282 | rate = a->police.rate_bytes_ps; |
2283 | burst = rate * PSCHED_NS2TICKS(a->police.burst); |
2284 | pol = (struct ocelot_policer) { |
2285 | .burst = div_u64(dividend: burst, PSCHED_TICKS_PER_SEC), |
2286 | .rate = div_u64(dividend: rate, divisor: 1000) * 8, |
2287 | }; |
2288 | ret = ocelot_vcap_policer_add(ocelot, pol_ix: index, pol: &pol); |
2289 | if (ret) |
2290 | goto err; |
2291 | |
2292 | sfi.fm_valid = 1; |
2293 | sfi.fmid = index; |
2294 | sfi.maxsdu = a->police.mtu; |
2295 | break; |
2296 | default: |
2297 | mutex_unlock(lock: &psfp->lock); |
2298 | return -EOPNOTSUPP; |
2299 | } |
2300 | } |
2301 | |
2302 | stream.ports = BIT(port); |
2303 | stream.port = port; |
2304 | |
2305 | sfi.portmask = stream.ports; |
2306 | sfi.prio_valid = (stream.prio < 0 ? 0 : 1); |
2307 | sfi.prio = (sfi.prio_valid ? stream.prio : 0); |
2308 | sfi.enable = 1; |
2309 | |
2310 | /* Check if stream is set. */ |
2311 | stream_entry = vsc9959_stream_table_lookup(stream_list: &psfp->stream_list, stream: &stream); |
2312 | if (stream_entry) { |
2313 | if (stream_entry->ports & BIT(port)) { |
2314 | NL_SET_ERR_MSG_MOD(extack, |
2315 | "The stream is added on this port" ); |
2316 | ret = -EEXIST; |
2317 | goto err; |
2318 | } |
2319 | |
2320 | if (stream_entry->ports != BIT(stream_entry->port)) { |
2321 | NL_SET_ERR_MSG_MOD(extack, |
2322 | "The stream is added on two ports" ); |
2323 | ret = -EEXIST; |
2324 | goto err; |
2325 | } |
2326 | |
2327 | stream_entry->ports |= BIT(port); |
2328 | stream.ports = stream_entry->ports; |
2329 | |
2330 | sfi_entry = vsc9959_psfp_sfi_table_get(sfi_list: &psfp->sfi_list, |
2331 | index: stream_entry->sfid); |
2332 | memcpy(&old_sfi, sfi_entry, sizeof(old_sfi)); |
2333 | |
2334 | vsc9959_psfp_sfi_table_del(ocelot, index: stream_entry->sfid); |
2335 | |
2336 | old_sfi.portmask = stream_entry->ports; |
2337 | sfi.portmask = stream.ports; |
2338 | |
2339 | if (stream_entry->port > port) { |
2340 | ret = vsc9959_psfp_sfi_table_add2(ocelot, sfi: &sfi, |
2341 | sfi2: &old_sfi); |
2342 | stream_entry->dummy = true; |
2343 | } else { |
2344 | ret = vsc9959_psfp_sfi_table_add2(ocelot, sfi: &old_sfi, |
2345 | sfi2: &sfi); |
2346 | stream.dummy = true; |
2347 | } |
2348 | if (ret) |
2349 | goto err; |
2350 | |
2351 | stream_entry->sfid = old_sfi.index; |
2352 | } else { |
2353 | ret = vsc9959_psfp_sfi_table_add(ocelot, sfi: &sfi); |
2354 | if (ret) |
2355 | goto err; |
2356 | } |
2357 | |
2358 | stream.sfid = sfi.index; |
2359 | stream.sfid_valid = 1; |
2360 | ret = vsc9959_stream_table_add(ocelot, stream_list: &psfp->stream_list, |
2361 | stream: &stream, extack); |
2362 | if (ret) { |
2363 | vsc9959_psfp_sfi_table_del(ocelot, index: stream.sfid); |
2364 | goto err; |
2365 | } |
2366 | |
2367 | mutex_unlock(lock: &psfp->lock); |
2368 | |
2369 | return 0; |
2370 | |
2371 | err: |
2372 | if (sfi.sg_valid) |
2373 | vsc9959_psfp_sgi_table_del(ocelot, index: sfi.sgid); |
2374 | |
2375 | if (sfi.fm_valid) |
2376 | ocelot_vcap_policer_del(ocelot, pol_ix: sfi.fmid); |
2377 | |
2378 | mutex_unlock(lock: &psfp->lock); |
2379 | |
2380 | return ret; |
2381 | } |
2382 | |
2383 | static int vsc9959_psfp_filter_del(struct ocelot *ocelot, |
2384 | struct flow_cls_offload *f) |
2385 | { |
2386 | struct felix_stream *stream, tmp, *stream_entry; |
2387 | struct ocelot_psfp_list *psfp = &ocelot->psfp; |
2388 | static struct felix_stream_filter *sfi; |
2389 | |
2390 | mutex_lock(&psfp->lock); |
2391 | |
2392 | stream = vsc9959_stream_table_get(stream_list: &psfp->stream_list, id: f->cookie); |
2393 | if (!stream) { |
2394 | mutex_unlock(lock: &psfp->lock); |
2395 | return -ENOMEM; |
2396 | } |
2397 | |
2398 | sfi = vsc9959_psfp_sfi_table_get(sfi_list: &psfp->sfi_list, index: stream->sfid); |
2399 | if (!sfi) { |
2400 | mutex_unlock(lock: &psfp->lock); |
2401 | return -ENOMEM; |
2402 | } |
2403 | |
2404 | if (sfi->sg_valid) |
2405 | vsc9959_psfp_sgi_table_del(ocelot, index: sfi->sgid); |
2406 | |
2407 | if (sfi->fm_valid) |
2408 | ocelot_vcap_policer_del(ocelot, pol_ix: sfi->fmid); |
2409 | |
2410 | vsc9959_psfp_sfi_table_del(ocelot, index: stream->sfid); |
2411 | |
2412 | memcpy(&tmp, stream, sizeof(tmp)); |
2413 | |
2414 | stream->sfid_valid = 0; |
2415 | vsc9959_stream_table_del(ocelot, stream); |
2416 | |
2417 | stream_entry = vsc9959_stream_table_lookup(stream_list: &psfp->stream_list, stream: &tmp); |
2418 | if (stream_entry) { |
2419 | stream_entry->ports = BIT(stream_entry->port); |
2420 | if (stream_entry->dummy) { |
2421 | stream_entry->dummy = false; |
2422 | vsc9959_mact_stream_set(ocelot, stream: stream_entry, NULL); |
2423 | } |
2424 | vsc9959_psfp_sfidmask_set(ocelot, sfid: stream_entry->sfid, |
2425 | ports: stream_entry->ports); |
2426 | } |
2427 | |
2428 | mutex_unlock(lock: &psfp->lock); |
2429 | |
2430 | return 0; |
2431 | } |
2432 | |
2433 | static void vsc9959_update_sfid_stats(struct ocelot *ocelot, |
2434 | struct felix_stream_filter *sfi) |
2435 | { |
2436 | struct felix_stream_filter_counters *s = &sfi->stats; |
2437 | u32 match, not_pass_gate, not_pass_sdu, red; |
2438 | u32 sfid = sfi->index; |
2439 | |
2440 | lockdep_assert_held(&ocelot->stat_view_lock); |
2441 | |
2442 | ocelot_rmw(ocelot, SYS_STAT_CFG_STAT_VIEW(sfid), |
2443 | SYS_STAT_CFG_STAT_VIEW_M, |
2444 | SYS_STAT_CFG); |
2445 | |
2446 | match = ocelot_read(ocelot, SYS_COUNT_SF_MATCHING_FRAMES); |
2447 | not_pass_gate = ocelot_read(ocelot, SYS_COUNT_SF_NOT_PASSING_FRAMES); |
2448 | not_pass_sdu = ocelot_read(ocelot, SYS_COUNT_SF_NOT_PASSING_SDU); |
2449 | red = ocelot_read(ocelot, SYS_COUNT_SF_RED_FRAMES); |
2450 | |
2451 | /* Clear the PSFP counter. */ |
2452 | ocelot_write(ocelot, |
2453 | SYS_STAT_CFG_STAT_VIEW(sfid) | |
2454 | SYS_STAT_CFG_STAT_CLEAR_SHOT(0x10), |
2455 | SYS_STAT_CFG); |
2456 | |
2457 | s->match += match; |
2458 | s->not_pass_gate += not_pass_gate; |
2459 | s->not_pass_sdu += not_pass_sdu; |
2460 | s->red += red; |
2461 | } |
2462 | |
2463 | /* Caller must hold &ocelot->stat_view_lock */ |
2464 | static void vsc9959_update_stats(struct ocelot *ocelot) |
2465 | { |
2466 | struct ocelot_psfp_list *psfp = &ocelot->psfp; |
2467 | struct felix_stream_filter *sfi; |
2468 | |
2469 | mutex_lock(&psfp->lock); |
2470 | |
2471 | list_for_each_entry(sfi, &psfp->sfi_list, list) |
2472 | vsc9959_update_sfid_stats(ocelot, sfi); |
2473 | |
2474 | mutex_unlock(lock: &psfp->lock); |
2475 | } |
2476 | |
2477 | static int vsc9959_psfp_stats_get(struct ocelot *ocelot, |
2478 | struct flow_cls_offload *f, |
2479 | struct flow_stats *stats) |
2480 | { |
2481 | struct ocelot_psfp_list *psfp = &ocelot->psfp; |
2482 | struct felix_stream_filter_counters *s; |
2483 | static struct felix_stream_filter *sfi; |
2484 | struct felix_stream *stream; |
2485 | |
2486 | stream = vsc9959_stream_table_get(stream_list: &psfp->stream_list, id: f->cookie); |
2487 | if (!stream) |
2488 | return -ENOMEM; |
2489 | |
2490 | sfi = vsc9959_psfp_sfi_table_get(sfi_list: &psfp->sfi_list, index: stream->sfid); |
2491 | if (!sfi) |
2492 | return -EINVAL; |
2493 | |
2494 | mutex_lock(&ocelot->stat_view_lock); |
2495 | |
2496 | vsc9959_update_sfid_stats(ocelot, sfi); |
2497 | |
2498 | s = &sfi->stats; |
2499 | stats->pkts = s->match; |
2500 | stats->drops = s->not_pass_gate + s->not_pass_sdu + s->red; |
2501 | |
2502 | memset(s, 0, sizeof(*s)); |
2503 | |
2504 | mutex_unlock(lock: &ocelot->stat_view_lock); |
2505 | |
2506 | return 0; |
2507 | } |
2508 | |
2509 | static void vsc9959_psfp_init(struct ocelot *ocelot) |
2510 | { |
2511 | struct ocelot_psfp_list *psfp = &ocelot->psfp; |
2512 | |
2513 | INIT_LIST_HEAD(list: &psfp->stream_list); |
2514 | INIT_LIST_HEAD(list: &psfp->sfi_list); |
2515 | INIT_LIST_HEAD(list: &psfp->sgi_list); |
2516 | mutex_init(&psfp->lock); |
2517 | } |
2518 | |
2519 | /* When using cut-through forwarding and the egress port runs at a higher data |
2520 | * rate than the ingress port, the packet currently under transmission would |
2521 | * suffer an underrun since it would be transmitted faster than it is received. |
2522 | * The Felix switch implementation of cut-through forwarding does not check in |
2523 | * hardware whether this condition is satisfied or not, so we must restrict the |
2524 | * list of ports that have cut-through forwarding enabled on egress to only be |
2525 | * the ports operating at the lowest link speed within their respective |
2526 | * forwarding domain. |
2527 | */ |
2528 | static void vsc9959_cut_through_fwd(struct ocelot *ocelot) |
2529 | { |
2530 | struct felix *felix = ocelot_to_felix(ocelot); |
2531 | struct dsa_switch *ds = felix->ds; |
2532 | int tc, port, other_port; |
2533 | |
2534 | lockdep_assert_held(&ocelot->fwd_domain_lock); |
2535 | |
2536 | for (port = 0; port < ocelot->num_phys_ports; port++) { |
2537 | struct ocelot_port *ocelot_port = ocelot->ports[port]; |
2538 | struct ocelot_mm_state *mm = &ocelot->mm[port]; |
2539 | int min_speed = ocelot_port->speed; |
2540 | unsigned long mask = 0; |
2541 | u32 tmp, val = 0; |
2542 | |
2543 | /* Disable cut-through on ports that are down */ |
2544 | if (ocelot_port->speed <= 0) |
2545 | goto set; |
2546 | |
2547 | if (dsa_is_cpu_port(ds, p: port)) { |
2548 | /* Ocelot switches forward from the NPI port towards |
2549 | * any port, regardless of it being in the NPI port's |
2550 | * forwarding domain or not. |
2551 | */ |
2552 | mask = dsa_user_ports(ds); |
2553 | } else { |
2554 | mask = ocelot_get_bridge_fwd_mask(ocelot, src_port: port); |
2555 | mask &= ~BIT(port); |
2556 | if (ocelot->npi >= 0) |
2557 | mask |= BIT(ocelot->npi); |
2558 | else |
2559 | mask |= ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot, |
2560 | port); |
2561 | } |
2562 | |
2563 | /* Calculate the minimum link speed, among the ports that are |
2564 | * up, of this source port's forwarding domain. |
2565 | */ |
2566 | for_each_set_bit(other_port, &mask, ocelot->num_phys_ports) { |
2567 | struct ocelot_port *other_ocelot_port; |
2568 | |
2569 | other_ocelot_port = ocelot->ports[other_port]; |
2570 | if (other_ocelot_port->speed <= 0) |
2571 | continue; |
2572 | |
2573 | if (min_speed > other_ocelot_port->speed) |
2574 | min_speed = other_ocelot_port->speed; |
2575 | } |
2576 | |
2577 | /* Enable cut-through forwarding for all traffic classes that |
2578 | * don't have oversized dropping enabled, since this check is |
2579 | * bypassed in cut-through mode. Also exclude preemptible |
2580 | * traffic classes, since these would hang the port for some |
2581 | * reason, if sent as cut-through. |
2582 | */ |
2583 | if (ocelot_port->speed == min_speed) { |
2584 | val = GENMASK(7, 0) & ~mm->active_preemptible_tcs; |
2585 | |
2586 | for (tc = 0; tc < OCELOT_NUM_TC; tc++) |
2587 | if (vsc9959_port_qmaxsdu_get(ocelot, port, tc)) |
2588 | val &= ~BIT(tc); |
2589 | } |
2590 | |
2591 | set: |
2592 | tmp = ocelot_read_rix(ocelot, ANA_CUT_THRU_CFG, port); |
2593 | if (tmp == val) |
2594 | continue; |
2595 | |
2596 | dev_dbg(ocelot->dev, |
2597 | "port %d fwd mask 0x%lx speed %d min_speed %d, %s cut-through forwarding on TC mask 0x%x\n" , |
2598 | port, mask, ocelot_port->speed, min_speed, |
2599 | val ? "enabling" : "disabling" , val); |
2600 | |
2601 | ocelot_write_rix(ocelot, val, ANA_CUT_THRU_CFG, port); |
2602 | } |
2603 | } |
2604 | |
2605 | static const struct ocelot_ops vsc9959_ops = { |
2606 | .reset = vsc9959_reset, |
2607 | .wm_enc = vsc9959_wm_enc, |
2608 | .wm_dec = vsc9959_wm_dec, |
2609 | .wm_stat = vsc9959_wm_stat, |
2610 | .port_to_netdev = felix_port_to_netdev, |
2611 | .netdev_to_port = felix_netdev_to_port, |
2612 | .psfp_init = vsc9959_psfp_init, |
2613 | .psfp_filter_add = vsc9959_psfp_filter_add, |
2614 | .psfp_filter_del = vsc9959_psfp_filter_del, |
2615 | .psfp_stats_get = vsc9959_psfp_stats_get, |
2616 | .cut_through_fwd = vsc9959_cut_through_fwd, |
2617 | .tas_clock_adjust = vsc9959_tas_clock_adjust, |
2618 | .update_stats = vsc9959_update_stats, |
2619 | .tas_guard_bands_update = vsc9959_tas_guard_bands_update, |
2620 | }; |
2621 | |
2622 | static const struct felix_info felix_info_vsc9959 = { |
2623 | .resources = vsc9959_resources, |
2624 | .num_resources = ARRAY_SIZE(vsc9959_resources), |
2625 | .resource_names = vsc9959_resource_names, |
2626 | .regfields = vsc9959_regfields, |
2627 | .map = vsc9959_regmap, |
2628 | .ops = &vsc9959_ops, |
2629 | .vcap = vsc9959_vcap_props, |
2630 | .vcap_pol_base = VSC9959_VCAP_POLICER_BASE, |
2631 | .vcap_pol_max = VSC9959_VCAP_POLICER_MAX, |
2632 | .vcap_pol_base2 = 0, |
2633 | .vcap_pol_max2 = 0, |
2634 | .num_mact_rows = 2048, |
2635 | .num_ports = VSC9959_NUM_PORTS, |
2636 | .num_tx_queues = OCELOT_NUM_TC, |
2637 | .quirks = FELIX_MAC_QUIRKS, |
2638 | .quirk_no_xtr_irq = true, |
2639 | .ptp_caps = &vsc9959_ptp_caps, |
2640 | .mdio_bus_alloc = vsc9959_mdio_bus_alloc, |
2641 | .mdio_bus_free = vsc9959_mdio_bus_free, |
2642 | .port_modes = vsc9959_port_modes, |
2643 | .port_setup_tc = vsc9959_port_setup_tc, |
2644 | .port_sched_speed_set = vsc9959_sched_speed_set, |
2645 | }; |
2646 | |
2647 | /* The INTB interrupt is shared between for PTP TX timestamp availability |
2648 | * notification and MAC Merge status change on each port. |
2649 | */ |
2650 | static irqreturn_t felix_irq_handler(int irq, void *data) |
2651 | { |
2652 | struct ocelot *ocelot = (struct ocelot *)data; |
2653 | |
2654 | ocelot_get_txtstamp(ocelot); |
2655 | ocelot_mm_irq(ocelot); |
2656 | |
2657 | return IRQ_HANDLED; |
2658 | } |
2659 | |
2660 | static int felix_pci_probe(struct pci_dev *pdev, |
2661 | const struct pci_device_id *id) |
2662 | { |
2663 | struct dsa_switch *ds; |
2664 | struct ocelot *ocelot; |
2665 | struct felix *felix; |
2666 | int err; |
2667 | |
2668 | if (pdev->dev.of_node && !of_device_is_available(device: pdev->dev.of_node)) { |
2669 | dev_info(&pdev->dev, "device is disabled, skipping\n" ); |
2670 | return -ENODEV; |
2671 | } |
2672 | |
2673 | err = pci_enable_device(dev: pdev); |
2674 | if (err) { |
2675 | dev_err(&pdev->dev, "device enable failed\n" ); |
2676 | goto err_pci_enable; |
2677 | } |
2678 | |
2679 | felix = kzalloc(size: sizeof(struct felix), GFP_KERNEL); |
2680 | if (!felix) { |
2681 | err = -ENOMEM; |
2682 | dev_err(&pdev->dev, "Failed to allocate driver memory\n" ); |
2683 | goto err_alloc_felix; |
2684 | } |
2685 | |
2686 | pci_set_drvdata(pdev, data: felix); |
2687 | ocelot = &felix->ocelot; |
2688 | ocelot->dev = &pdev->dev; |
2689 | ocelot->num_flooding_pgids = OCELOT_NUM_TC; |
2690 | felix->info = &felix_info_vsc9959; |
2691 | felix->switch_base = pci_resource_start(pdev, VSC9959_SWITCH_PCI_BAR); |
2692 | |
2693 | pci_set_master(dev: pdev); |
2694 | |
2695 | err = devm_request_threaded_irq(dev: &pdev->dev, irq: pdev->irq, NULL, |
2696 | thread_fn: &felix_irq_handler, IRQF_ONESHOT, |
2697 | devname: "felix-intb" , dev_id: ocelot); |
2698 | if (err) { |
2699 | dev_err(&pdev->dev, "Failed to request irq\n" ); |
2700 | goto err_alloc_irq; |
2701 | } |
2702 | |
2703 | ocelot->ptp = 1; |
2704 | ocelot->mm_supported = true; |
2705 | |
2706 | ds = kzalloc(size: sizeof(struct dsa_switch), GFP_KERNEL); |
2707 | if (!ds) { |
2708 | err = -ENOMEM; |
2709 | dev_err(&pdev->dev, "Failed to allocate DSA switch\n" ); |
2710 | goto err_alloc_ds; |
2711 | } |
2712 | |
2713 | ds->dev = &pdev->dev; |
2714 | ds->num_ports = felix->info->num_ports; |
2715 | ds->num_tx_queues = felix->info->num_tx_queues; |
2716 | ds->ops = &felix_switch_ops; |
2717 | ds->priv = ocelot; |
2718 | felix->ds = ds; |
2719 | felix->tag_proto = DSA_TAG_PROTO_OCELOT; |
2720 | |
2721 | err = dsa_register_switch(ds); |
2722 | if (err) { |
2723 | dev_err_probe(dev: &pdev->dev, err, fmt: "Failed to register DSA switch\n" ); |
2724 | goto err_register_ds; |
2725 | } |
2726 | |
2727 | return 0; |
2728 | |
2729 | err_register_ds: |
2730 | kfree(objp: ds); |
2731 | err_alloc_ds: |
2732 | err_alloc_irq: |
2733 | kfree(objp: felix); |
2734 | err_alloc_felix: |
2735 | pci_disable_device(dev: pdev); |
2736 | err_pci_enable: |
2737 | return err; |
2738 | } |
2739 | |
2740 | static void felix_pci_remove(struct pci_dev *pdev) |
2741 | { |
2742 | struct felix *felix = pci_get_drvdata(pdev); |
2743 | |
2744 | if (!felix) |
2745 | return; |
2746 | |
2747 | dsa_unregister_switch(ds: felix->ds); |
2748 | |
2749 | kfree(objp: felix->ds); |
2750 | kfree(objp: felix); |
2751 | |
2752 | pci_disable_device(dev: pdev); |
2753 | } |
2754 | |
2755 | static void felix_pci_shutdown(struct pci_dev *pdev) |
2756 | { |
2757 | struct felix *felix = pci_get_drvdata(pdev); |
2758 | |
2759 | if (!felix) |
2760 | return; |
2761 | |
2762 | dsa_switch_shutdown(ds: felix->ds); |
2763 | |
2764 | pci_set_drvdata(pdev, NULL); |
2765 | } |
2766 | |
2767 | static struct pci_device_id felix_ids[] = { |
2768 | { |
2769 | /* NXP LS1028A */ |
2770 | PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0xEEF0), |
2771 | }, |
2772 | { 0, } |
2773 | }; |
2774 | MODULE_DEVICE_TABLE(pci, felix_ids); |
2775 | |
2776 | static struct pci_driver felix_vsc9959_pci_driver = { |
2777 | .name = "mscc_felix" , |
2778 | .id_table = felix_ids, |
2779 | .probe = felix_pci_probe, |
2780 | .remove = felix_pci_remove, |
2781 | .shutdown = felix_pci_shutdown, |
2782 | }; |
2783 | module_pci_driver(felix_vsc9959_pci_driver); |
2784 | |
2785 | MODULE_DESCRIPTION("Felix Switch driver" ); |
2786 | MODULE_LICENSE("GPL v2" ); |
2787 | |