1// SPDX-License-Identifier: GPL-2.0
2//
3// rt1015.c -- RT1015 ALSA SoC audio amplifier driver
4//
5// Copyright 2019 Realtek Semiconductor Corp.
6//
7// Author: Jack Yu <jack.yu@realtek.com>
8//
9//
10
11#include <linux/acpi.h>
12#include <linux/delay.h>
13#include <linux/firmware.h>
14#include <linux/fs.h>
15#include <linux/i2c.h>
16#include <linux/init.h>
17#include <linux/module.h>
18#include <linux/moduleparam.h>
19#include <linux/platform_device.h>
20#include <linux/pm.h>
21#include <linux/regmap.h>
22#include <sound/core.h>
23#include <sound/initval.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/rt1015.h>
27#include <sound/soc-dapm.h>
28#include <sound/soc.h>
29#include <sound/tlv.h>
30
31#include "rl6231.h"
32#include "rt1015.h"
33
34static const struct rt1015_platform_data i2s_default_platform_data = {
35 .power_up_delay_ms = 50,
36};
37
38static const struct reg_default rt1015_reg[] = {
39 { 0x0000, 0x0000 },
40 { 0x0004, 0xa000 },
41 { 0x0006, 0x0003 },
42 { 0x000a, 0x081e },
43 { 0x000c, 0x0006 },
44 { 0x000e, 0x0000 },
45 { 0x0010, 0x0000 },
46 { 0x0012, 0x0000 },
47 { 0x0014, 0x0000 },
48 { 0x0016, 0x0000 },
49 { 0x0018, 0x0000 },
50 { 0x0020, 0x8000 },
51 { 0x0022, 0x8043 },
52 { 0x0076, 0x0000 },
53 { 0x0078, 0x0000 },
54 { 0x007a, 0x0002 },
55 { 0x007c, 0x10ec },
56 { 0x007d, 0x1015 },
57 { 0x00f0, 0x5000 },
58 { 0x00f2, 0x004c },
59 { 0x00f3, 0xecfe },
60 { 0x00f4, 0x0000 },
61 { 0x00f6, 0x0400 },
62 { 0x0100, 0x0028 },
63 { 0x0102, 0xff02 },
64 { 0x0104, 0xa213 },
65 { 0x0106, 0x200c },
66 { 0x010c, 0x0000 },
67 { 0x010e, 0x0058 },
68 { 0x0111, 0x0200 },
69 { 0x0112, 0x0400 },
70 { 0x0114, 0x0022 },
71 { 0x0116, 0x0000 },
72 { 0x0118, 0x0000 },
73 { 0x011a, 0x0123 },
74 { 0x011c, 0x4567 },
75 { 0x0300, 0x203d },
76 { 0x0302, 0x001e },
77 { 0x0311, 0x0000 },
78 { 0x0313, 0x6014 },
79 { 0x0314, 0x00a2 },
80 { 0x031a, 0x00a0 },
81 { 0x031c, 0x001f },
82 { 0x031d, 0xffff },
83 { 0x031e, 0x0000 },
84 { 0x031f, 0x0000 },
85 { 0x0320, 0x0000 },
86 { 0x0321, 0x0000 },
87 { 0x0322, 0xd7df },
88 { 0x0328, 0x10b2 },
89 { 0x0329, 0x0175 },
90 { 0x032a, 0x36ad },
91 { 0x032b, 0x7e55 },
92 { 0x032c, 0x0520 },
93 { 0x032d, 0xaa00 },
94 { 0x032e, 0x570e },
95 { 0x0330, 0xe180 },
96 { 0x0332, 0x0034 },
97 { 0x0334, 0x0001 },
98 { 0x0336, 0x0010 },
99 { 0x0338, 0x0000 },
100 { 0x04fa, 0x0030 },
101 { 0x04fc, 0x35c8 },
102 { 0x04fe, 0x0800 },
103 { 0x0500, 0x0400 },
104 { 0x0502, 0x1000 },
105 { 0x0504, 0x0000 },
106 { 0x0506, 0x04ff },
107 { 0x0508, 0x0010 },
108 { 0x050a, 0x001a },
109 { 0x0519, 0x1c68 },
110 { 0x051a, 0x0ccc },
111 { 0x051b, 0x0666 },
112 { 0x051d, 0x0000 },
113 { 0x051f, 0x0000 },
114 { 0x0536, 0x061c },
115 { 0x0538, 0x0000 },
116 { 0x053a, 0x0000 },
117 { 0x053c, 0x0000 },
118 { 0x053d, 0x0000 },
119 { 0x053e, 0x0000 },
120 { 0x053f, 0x0000 },
121 { 0x0540, 0x0000 },
122 { 0x0541, 0x0000 },
123 { 0x0542, 0x0000 },
124 { 0x0543, 0x0000 },
125 { 0x0544, 0x0000 },
126 { 0x0568, 0x0000 },
127 { 0x056a, 0x0000 },
128 { 0x1000, 0x0040 },
129 { 0x1002, 0x5405 },
130 { 0x1006, 0x5515 },
131 { 0x1007, 0x05f7 },
132 { 0x1009, 0x0b0a },
133 { 0x100a, 0x00ef },
134 { 0x100d, 0x0003 },
135 { 0x1010, 0xa433 },
136 { 0x1020, 0x0000 },
137 { 0x1200, 0x5a01 },
138 { 0x1202, 0x6524 },
139 { 0x1204, 0x1f00 },
140 { 0x1206, 0x0000 },
141 { 0x1208, 0x0000 },
142 { 0x120a, 0x0000 },
143 { 0x120c, 0x0000 },
144 { 0x120e, 0x0000 },
145 { 0x1210, 0x0000 },
146 { 0x1212, 0x0000 },
147 { 0x1300, 0x10a1 },
148 { 0x1302, 0x12ff },
149 { 0x1304, 0x0400 },
150 { 0x1305, 0x0844 },
151 { 0x1306, 0x4611 },
152 { 0x1308, 0x555e },
153 { 0x130a, 0x0000 },
154 { 0x130c, 0x2000 },
155 { 0x130e, 0x0100 },
156 { 0x130f, 0x0001 },
157 { 0x1310, 0x0000 },
158 { 0x1312, 0x0000 },
159 { 0x1314, 0x0000 },
160 { 0x1316, 0x0000 },
161 { 0x1318, 0x0000 },
162 { 0x131a, 0x0000 },
163 { 0x1322, 0x0029 },
164 { 0x1323, 0x4a52 },
165 { 0x1324, 0x002c },
166 { 0x1325, 0x0b02 },
167 { 0x1326, 0x002d },
168 { 0x1327, 0x6b5a },
169 { 0x1328, 0x002e },
170 { 0x1329, 0xcbb2 },
171 { 0x132a, 0x0030 },
172 { 0x132b, 0x2c0b },
173 { 0x1330, 0x0031 },
174 { 0x1331, 0x8c63 },
175 { 0x1332, 0x0032 },
176 { 0x1333, 0xecbb },
177 { 0x1334, 0x0034 },
178 { 0x1335, 0x4d13 },
179 { 0x1336, 0x0037 },
180 { 0x1337, 0x0dc3 },
181 { 0x1338, 0x003d },
182 { 0x1339, 0xef7b },
183 { 0x133a, 0x0044 },
184 { 0x133b, 0xd134 },
185 { 0x133c, 0x0047 },
186 { 0x133d, 0x91e4 },
187 { 0x133e, 0x004d },
188 { 0x133f, 0xc370 },
189 { 0x1340, 0x0053 },
190 { 0x1341, 0xf4fd },
191 { 0x1342, 0x0060 },
192 { 0x1343, 0x5816 },
193 { 0x1344, 0x006c },
194 { 0x1345, 0xbb2e },
195 { 0x1346, 0x0072 },
196 { 0x1347, 0xecbb },
197 { 0x1348, 0x0076 },
198 { 0x1349, 0x5d97 },
199};
200
201static bool rt1015_volatile_register(struct device *dev, unsigned int reg)
202{
203 switch (reg) {
204 case RT1015_RESET:
205 case RT1015_CLK_DET:
206 case RT1015_SIL_DET:
207 case RT1015_VER_ID:
208 case RT1015_VENDOR_ID:
209 case RT1015_DEVICE_ID:
210 case RT1015_PRO_ALT:
211 case RT1015_MAN_I2C:
212 case RT1015_DAC3:
213 case RT1015_VBAT_TEST_OUT1:
214 case RT1015_VBAT_TEST_OUT2:
215 case RT1015_VBAT_PROT_ATT:
216 case RT1015_VBAT_DET_CODE:
217 case RT1015_SMART_BST_CTRL1:
218 case RT1015_SPK_DC_DETECT1:
219 case RT1015_SPK_DC_DETECT4:
220 case RT1015_SPK_DC_DETECT5:
221 case RT1015_DC_CALIB_CLSD1:
222 case RT1015_DC_CALIB_CLSD5:
223 case RT1015_DC_CALIB_CLSD6:
224 case RT1015_DC_CALIB_CLSD7:
225 case RT1015_DC_CALIB_CLSD8:
226 case RT1015_S_BST_TIMING_INTER1:
227 case RT1015_OSCK_STA:
228 case RT1015_MONO_DYNA_CTRL1:
229 case RT1015_MONO_DYNA_CTRL5:
230 return true;
231
232 default:
233 return false;
234 }
235}
236
237static bool rt1015_readable_register(struct device *dev, unsigned int reg)
238{
239 switch (reg) {
240 case RT1015_RESET:
241 case RT1015_CLK2:
242 case RT1015_CLK3:
243 case RT1015_PLL1:
244 case RT1015_PLL2:
245 case RT1015_DUM_RW1:
246 case RT1015_DUM_RW2:
247 case RT1015_DUM_RW3:
248 case RT1015_DUM_RW4:
249 case RT1015_DUM_RW5:
250 case RT1015_DUM_RW6:
251 case RT1015_CLK_DET:
252 case RT1015_SIL_DET:
253 case RT1015_CUSTOMER_ID:
254 case RT1015_PCODE_FWVER:
255 case RT1015_VER_ID:
256 case RT1015_VENDOR_ID:
257 case RT1015_DEVICE_ID:
258 case RT1015_PAD_DRV1:
259 case RT1015_PAD_DRV2:
260 case RT1015_GAT_BOOST:
261 case RT1015_PRO_ALT:
262 case RT1015_OSCK_STA:
263 case RT1015_MAN_I2C:
264 case RT1015_DAC1:
265 case RT1015_DAC2:
266 case RT1015_DAC3:
267 case RT1015_ADC1:
268 case RT1015_ADC2:
269 case RT1015_TDM_MASTER:
270 case RT1015_TDM_TCON:
271 case RT1015_TDM1_1:
272 case RT1015_TDM1_2:
273 case RT1015_TDM1_3:
274 case RT1015_TDM1_4:
275 case RT1015_TDM1_5:
276 case RT1015_MIXER1:
277 case RT1015_MIXER2:
278 case RT1015_ANA_PROTECT1:
279 case RT1015_ANA_CTRL_SEQ1:
280 case RT1015_ANA_CTRL_SEQ2:
281 case RT1015_VBAT_DET_DEB:
282 case RT1015_VBAT_VOLT_DET1:
283 case RT1015_VBAT_VOLT_DET2:
284 case RT1015_VBAT_TEST_OUT1:
285 case RT1015_VBAT_TEST_OUT2:
286 case RT1015_VBAT_PROT_ATT:
287 case RT1015_VBAT_DET_CODE:
288 case RT1015_PWR1:
289 case RT1015_PWR4:
290 case RT1015_PWR5:
291 case RT1015_PWR6:
292 case RT1015_PWR7:
293 case RT1015_PWR8:
294 case RT1015_PWR9:
295 case RT1015_CLASSD_SEQ:
296 case RT1015_SMART_BST_CTRL1:
297 case RT1015_SMART_BST_CTRL2:
298 case RT1015_ANA_CTRL1:
299 case RT1015_ANA_CTRL2:
300 case RT1015_PWR_STATE_CTRL:
301 case RT1015_MONO_DYNA_CTRL:
302 case RT1015_MONO_DYNA_CTRL1:
303 case RT1015_MONO_DYNA_CTRL2:
304 case RT1015_MONO_DYNA_CTRL3:
305 case RT1015_MONO_DYNA_CTRL4:
306 case RT1015_MONO_DYNA_CTRL5:
307 case RT1015_SPK_VOL:
308 case RT1015_SHORT_DETTOP1:
309 case RT1015_SHORT_DETTOP2:
310 case RT1015_SPK_DC_DETECT1:
311 case RT1015_SPK_DC_DETECT2:
312 case RT1015_SPK_DC_DETECT3:
313 case RT1015_SPK_DC_DETECT4:
314 case RT1015_SPK_DC_DETECT5:
315 case RT1015_BAT_RPO_STEP1:
316 case RT1015_BAT_RPO_STEP2:
317 case RT1015_BAT_RPO_STEP3:
318 case RT1015_BAT_RPO_STEP4:
319 case RT1015_BAT_RPO_STEP5:
320 case RT1015_BAT_RPO_STEP6:
321 case RT1015_BAT_RPO_STEP7:
322 case RT1015_BAT_RPO_STEP8:
323 case RT1015_BAT_RPO_STEP9:
324 case RT1015_BAT_RPO_STEP10:
325 case RT1015_BAT_RPO_STEP11:
326 case RT1015_BAT_RPO_STEP12:
327 case RT1015_SPREAD_SPEC1:
328 case RT1015_SPREAD_SPEC2:
329 case RT1015_PAD_STATUS:
330 case RT1015_PADS_PULLING_CTRL1:
331 case RT1015_PADS_DRIVING:
332 case RT1015_SYS_RST1:
333 case RT1015_SYS_RST2:
334 case RT1015_SYS_GATING1:
335 case RT1015_TEST_MODE1:
336 case RT1015_TEST_MODE2:
337 case RT1015_TIMING_CTRL1:
338 case RT1015_PLL_INT:
339 case RT1015_TEST_OUT1:
340 case RT1015_DC_CALIB_CLSD1:
341 case RT1015_DC_CALIB_CLSD2:
342 case RT1015_DC_CALIB_CLSD3:
343 case RT1015_DC_CALIB_CLSD4:
344 case RT1015_DC_CALIB_CLSD5:
345 case RT1015_DC_CALIB_CLSD6:
346 case RT1015_DC_CALIB_CLSD7:
347 case RT1015_DC_CALIB_CLSD8:
348 case RT1015_DC_CALIB_CLSD9:
349 case RT1015_DC_CALIB_CLSD10:
350 case RT1015_CLSD_INTERNAL1:
351 case RT1015_CLSD_INTERNAL2:
352 case RT1015_CLSD_INTERNAL3:
353 case RT1015_CLSD_INTERNAL4:
354 case RT1015_CLSD_INTERNAL5:
355 case RT1015_CLSD_INTERNAL6:
356 case RT1015_CLSD_INTERNAL7:
357 case RT1015_CLSD_INTERNAL8:
358 case RT1015_CLSD_INTERNAL9:
359 case RT1015_CLSD_OCP_CTRL:
360 case RT1015_VREF_LV:
361 case RT1015_MBIAS1:
362 case RT1015_MBIAS2:
363 case RT1015_MBIAS3:
364 case RT1015_MBIAS4:
365 case RT1015_VREF_LV1:
366 case RT1015_S_BST_TIMING_INTER1:
367 case RT1015_S_BST_TIMING_INTER2:
368 case RT1015_S_BST_TIMING_INTER3:
369 case RT1015_S_BST_TIMING_INTER4:
370 case RT1015_S_BST_TIMING_INTER5:
371 case RT1015_S_BST_TIMING_INTER6:
372 case RT1015_S_BST_TIMING_INTER7:
373 case RT1015_S_BST_TIMING_INTER8:
374 case RT1015_S_BST_TIMING_INTER9:
375 case RT1015_S_BST_TIMING_INTER10:
376 case RT1015_S_BST_TIMING_INTER11:
377 case RT1015_S_BST_TIMING_INTER12:
378 case RT1015_S_BST_TIMING_INTER13:
379 case RT1015_S_BST_TIMING_INTER14:
380 case RT1015_S_BST_TIMING_INTER15:
381 case RT1015_S_BST_TIMING_INTER16:
382 case RT1015_S_BST_TIMING_INTER17:
383 case RT1015_S_BST_TIMING_INTER18:
384 case RT1015_S_BST_TIMING_INTER19:
385 case RT1015_S_BST_TIMING_INTER20:
386 case RT1015_S_BST_TIMING_INTER21:
387 case RT1015_S_BST_TIMING_INTER22:
388 case RT1015_S_BST_TIMING_INTER23:
389 case RT1015_S_BST_TIMING_INTER24:
390 case RT1015_S_BST_TIMING_INTER25:
391 case RT1015_S_BST_TIMING_INTER26:
392 case RT1015_S_BST_TIMING_INTER27:
393 case RT1015_S_BST_TIMING_INTER28:
394 case RT1015_S_BST_TIMING_INTER29:
395 case RT1015_S_BST_TIMING_INTER30:
396 case RT1015_S_BST_TIMING_INTER31:
397 case RT1015_S_BST_TIMING_INTER32:
398 case RT1015_S_BST_TIMING_INTER33:
399 case RT1015_S_BST_TIMING_INTER34:
400 case RT1015_S_BST_TIMING_INTER35:
401 case RT1015_S_BST_TIMING_INTER36:
402 return true;
403
404 default:
405 return false;
406 }
407}
408
409static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9525, 75, 0);
410
411static const char * const rt1015_din_source_select[] = {
412 "Left",
413 "Right",
414 "Left + Right average",
415};
416
417static SOC_ENUM_SINGLE_DECL(rt1015_mono_lr_sel, RT1015_PAD_DRV2, 4,
418 rt1015_din_source_select);
419
420static const char * const rt1015_boost_mode[] = {
421 "Bypass", "Adaptive", "Fixed Adaptive"
422};
423
424static SOC_ENUM_SINGLE_DECL(rt1015_boost_mode_enum, 0, 0,
425 rt1015_boost_mode);
426
427static int rt1015_boost_mode_get(struct snd_kcontrol *kcontrol,
428 struct snd_ctl_elem_value *ucontrol)
429{
430 struct snd_soc_component *component =
431 snd_soc_kcontrol_component(kcontrol);
432 struct rt1015_priv *rt1015 =
433 snd_soc_component_get_drvdata(c: component);
434
435 ucontrol->value.integer.value[0] = rt1015->boost_mode;
436
437 return 0;
438}
439
440static int rt1015_boost_mode_put(struct snd_kcontrol *kcontrol,
441 struct snd_ctl_elem_value *ucontrol)
442{
443 struct snd_soc_component *component =
444 snd_soc_kcontrol_component(kcontrol);
445 struct rt1015_priv *rt1015 =
446 snd_soc_component_get_drvdata(c: component);
447 int boost_mode = ucontrol->value.integer.value[0];
448
449 switch (boost_mode) {
450 case BYPASS:
451 snd_soc_component_update_bits(component,
452 RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK |
453 RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK,
454 RT1015_ABST_REG_MODE | RT1015_ABST_FIX_TGT_DIS |
455 RT1015_BYPASS_SWRREG_BYPASS);
456 break;
457 case ADAPTIVE:
458 snd_soc_component_update_bits(component,
459 RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK |
460 RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK,
461 RT1015_ABST_AUTO_MODE | RT1015_ABST_FIX_TGT_DIS |
462 RT1015_BYPASS_SWRREG_PASS);
463 break;
464 case FIXED_ADAPTIVE:
465 snd_soc_component_update_bits(component,
466 RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK |
467 RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK,
468 RT1015_ABST_AUTO_MODE | RT1015_ABST_FIX_TGT_EN |
469 RT1015_BYPASS_SWRREG_PASS);
470 break;
471 default:
472 dev_err(component->dev, "Unknown boost control.\n");
473 return -EINVAL;
474 }
475
476 rt1015->boost_mode = boost_mode;
477
478 return 0;
479}
480
481static int rt1015_bypass_boost_get(struct snd_kcontrol *kcontrol,
482 struct snd_ctl_elem_value *ucontrol)
483{
484 struct snd_soc_component *component =
485 snd_soc_kcontrol_component(kcontrol);
486 struct rt1015_priv *rt1015 =
487 snd_soc_component_get_drvdata(c: component);
488
489 ucontrol->value.integer.value[0] = rt1015->bypass_boost;
490
491 return 0;
492}
493
494static void rt1015_calibrate(struct rt1015_priv *rt1015)
495{
496 struct snd_soc_component *component = rt1015->component;
497 struct regmap *regmap = rt1015->regmap;
498
499 snd_soc_dapm_mutex_lock(&component->dapm);
500 regcache_cache_bypass(map: regmap, enable: true);
501
502 regmap_write(map: regmap, RT1015_CLK_DET, val: 0x0000);
503 regmap_write(map: regmap, RT1015_PWR4, val: 0x00B2);
504 regmap_write(map: regmap, RT1015_PWR_STATE_CTRL, val: 0x0009);
505 msleep(msecs: 100);
506 regmap_write(map: regmap, RT1015_PWR_STATE_CTRL, val: 0x000A);
507 msleep(msecs: 100);
508 regmap_write(map: regmap, RT1015_PWR_STATE_CTRL, val: 0x000C);
509 msleep(msecs: 100);
510 regmap_write(map: regmap, RT1015_CLSD_INTERNAL8, val: 0x2028);
511 regmap_write(map: regmap, RT1015_CLSD_INTERNAL9, val: 0x0140);
512 regmap_write(map: regmap, RT1015_PWR_STATE_CTRL, val: 0x000D);
513 msleep(msecs: 300);
514 regmap_write(map: regmap, RT1015_PWR_STATE_CTRL, val: 0x0008);
515 regmap_write(map: regmap, RT1015_SYS_RST1, val: 0x05F5);
516 regmap_write(map: regmap, RT1015_CLK_DET, val: 0x8000);
517
518 regcache_cache_bypass(map: regmap, enable: false);
519 regcache_mark_dirty(map: regmap);
520 regcache_sync(map: regmap);
521 snd_soc_dapm_mutex_unlock(&component->dapm);
522}
523
524static int rt1015_bypass_boost_put(struct snd_kcontrol *kcontrol,
525 struct snd_ctl_elem_value *ucontrol)
526{
527 struct snd_soc_component *component =
528 snd_soc_kcontrol_component(kcontrol);
529 struct rt1015_priv *rt1015 =
530 snd_soc_component_get_drvdata(c: component);
531
532 if (rt1015->dac_is_used) {
533 dev_err(component->dev, "DAC is being used!\n");
534 return -EBUSY;
535 }
536
537 rt1015->bypass_boost = ucontrol->value.integer.value[0];
538 if (rt1015->bypass_boost == RT1015_Bypass_Boost &&
539 !rt1015->cali_done) {
540 rt1015_calibrate(rt1015);
541 rt1015->cali_done = 1;
542
543 regmap_write(map: rt1015->regmap, RT1015_MONO_DYNA_CTRL, val: 0x0010);
544 }
545
546 return 0;
547}
548
549static const char * const rt1015_dac_output_vol_select[] = {
550 "immediate",
551 "zero detection + immediate change",
552 "zero detection + inc/dec change",
553 "zero detection + soft inc/dec change",
554};
555
556static SOC_ENUM_SINGLE_DECL(rt1015_dac_vol_ctl_enum,
557 RT1015_DAC3, 2, rt1015_dac_output_vol_select);
558
559static const struct snd_kcontrol_new rt1015_snd_controls[] = {
560 SOC_SINGLE_TLV("DAC Playback Volume", RT1015_DAC1, RT1015_DAC_VOL_SFT,
561 127, 0, dac_vol_tlv),
562 SOC_DOUBLE("DAC Playback Switch", RT1015_DAC3,
563 RT1015_DA_MUTE_SFT, RT1015_DVOL_MUTE_FLAG_SFT, 1, 1),
564 SOC_ENUM_EXT("Boost Mode", rt1015_boost_mode_enum,
565 rt1015_boost_mode_get, rt1015_boost_mode_put),
566 SOC_ENUM("Mono LR Select", rt1015_mono_lr_sel),
567 SOC_SINGLE_EXT("Bypass Boost", SND_SOC_NOPM, 0, 1, 0,
568 rt1015_bypass_boost_get, rt1015_bypass_boost_put),
569
570 /* DAC Output Volume Control */
571 SOC_ENUM("DAC Output Control", rt1015_dac_vol_ctl_enum),
572};
573
574static int rt1015_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
575 struct snd_soc_dapm_widget *sink)
576{
577 struct snd_soc_component *component =
578 snd_soc_dapm_to_component(dapm: source->dapm);
579 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(c: component);
580
581 if (rt1015->sysclk_src == RT1015_SCLK_S_PLL)
582 return 1;
583 else
584 return 0;
585}
586
587static int r1015_dac_event(struct snd_soc_dapm_widget *w,
588 struct snd_kcontrol *kcontrol, int event)
589{
590 struct snd_soc_component *component =
591 snd_soc_dapm_to_component(dapm: w->dapm);
592 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(c: component);
593
594 switch (event) {
595 case SND_SOC_DAPM_PRE_PMU:
596 rt1015->dac_is_used = 1;
597 if (rt1015->bypass_boost == RT1015_Enable_Boost) {
598 snd_soc_component_write(component,
599 RT1015_SYS_RST1, val: 0x05f7);
600 snd_soc_component_write(component,
601 RT1015_SYS_RST2, val: 0x0b0a);
602 snd_soc_component_write(component,
603 RT1015_GAT_BOOST, val: 0xacfe);
604 snd_soc_component_write(component,
605 RT1015_PWR9, val: 0xaa00);
606 snd_soc_component_write(component,
607 RT1015_GAT_BOOST, val: 0xecfe);
608 } else {
609 snd_soc_component_write(component,
610 reg: 0x032d, val: 0xaa60);
611 snd_soc_component_write(component,
612 RT1015_SYS_RST1, val: 0x05f7);
613 snd_soc_component_write(component,
614 RT1015_SYS_RST2, val: 0x0b0a);
615 snd_soc_component_write(component,
616 RT1015_PWR_STATE_CTRL, val: 0x008e);
617 }
618 break;
619
620 case SND_SOC_DAPM_POST_PMD:
621 if (rt1015->bypass_boost == RT1015_Enable_Boost) {
622 snd_soc_component_write(component,
623 RT1015_PWR9, val: 0xa800);
624 snd_soc_component_write(component,
625 RT1015_SYS_RST1, val: 0x05f5);
626 snd_soc_component_write(component,
627 RT1015_SYS_RST2, val: 0x0b9a);
628 } else {
629 snd_soc_component_write(component,
630 reg: 0x032d, val: 0xaa60);
631 snd_soc_component_write(component,
632 RT1015_PWR_STATE_CTRL, val: 0x0088);
633 snd_soc_component_write(component,
634 RT1015_SYS_RST1, val: 0x05f5);
635 snd_soc_component_write(component,
636 RT1015_SYS_RST2, val: 0x0b9a);
637 }
638 rt1015->dac_is_used = 0;
639 break;
640
641 default:
642 break;
643 }
644 return 0;
645}
646
647static int rt1015_amp_drv_event(struct snd_soc_dapm_widget *w,
648 struct snd_kcontrol *kcontrol, int event)
649{
650 struct snd_soc_component *component =
651 snd_soc_dapm_to_component(dapm: w->dapm);
652 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(c: component);
653 unsigned int ret, ret2;
654
655 switch (event) {
656 case SND_SOC_DAPM_PRE_PMU:
657 ret = snd_soc_component_read(component, RT1015_CLK_DET);
658 ret2 = snd_soc_component_read(component, RT1015_SPK_DC_DETECT1);
659 if (!((ret >> 15) & 0x1)) {
660 snd_soc_component_update_bits(component, RT1015_CLK_DET,
661 RT1015_EN_BCLK_DET_MASK, RT1015_EN_BCLK_DET);
662 dev_dbg(component->dev, "BCLK Detection Enabled.\n");
663 }
664 if (!((ret2 >> 12) & 0x1)) {
665 snd_soc_component_update_bits(component, RT1015_SPK_DC_DETECT1,
666 RT1015_EN_CLA_D_DC_DET_MASK, RT1015_EN_CLA_D_DC_DET);
667 dev_dbg(component->dev, "Class-D DC Detection Enabled.\n");
668 }
669 break;
670 case SND_SOC_DAPM_POST_PMU:
671 msleep(msecs: rt1015->pdata.power_up_delay_ms);
672 break;
673 default:
674 break;
675 }
676 return 0;
677}
678
679static const struct snd_soc_dapm_widget rt1015_dapm_widgets[] = {
680 SND_SOC_DAPM_SUPPLY("PLL", RT1015_PWR1, RT1015_PWR_PLL_BIT, 0,
681 NULL, 0),
682 SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0),
683 SND_SOC_DAPM_DAC_E("DAC", NULL, SND_SOC_NOPM, 0, 0,
684 r1015_dac_event, SND_SOC_DAPM_PRE_PMU |
685 SND_SOC_DAPM_POST_PMD),
686 SND_SOC_DAPM_OUT_DRV_E("Amp Drv", SND_SOC_NOPM, 0, 0, NULL, 0,
687 rt1015_amp_drv_event, SND_SOC_DAPM_PRE_PMU |
688 SND_SOC_DAPM_POST_PMU),
689 SND_SOC_DAPM_OUTPUT("SPO"),
690};
691
692static const struct snd_soc_dapm_route rt1015_dapm_routes[] = {
693 { "DAC", NULL, "AIFRX" },
694 { "DAC", NULL, "PLL", rt1015_is_sys_clk_from_pll},
695 { "Amp Drv", NULL, "DAC" },
696 { "SPO", NULL, "Amp Drv" },
697};
698
699static int rt1015_hw_params(struct snd_pcm_substream *substream,
700 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
701{
702 struct snd_soc_component *component = dai->component;
703 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(c: component);
704 int pre_div, frame_size, lrck;
705 unsigned int val_len = 0;
706
707 lrck = params_rate(p: params);
708 pre_div = rl6231_get_clk_info(sclk: rt1015->sysclk, rate: lrck);
709 if (pre_div < 0) {
710 dev_err(component->dev, "Unsupported clock rate\n");
711 return -EINVAL;
712 }
713
714 frame_size = snd_soc_params_to_frame_size(params);
715 if (frame_size < 0) {
716 dev_err(component->dev, "Unsupported frame size: %d\n",
717 frame_size);
718 return -EINVAL;
719 }
720
721 dev_dbg(component->dev, "pre_div is %d for iis %d\n", pre_div, dai->id);
722
723 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
724 lrck, pre_div, dai->id);
725
726 switch (params_width(p: params)) {
727 case 16:
728 break;
729 case 20:
730 val_len = RT1015_I2S_DL_20;
731 break;
732 case 24:
733 val_len = RT1015_I2S_DL_24;
734 break;
735 case 8:
736 val_len = RT1015_I2S_DL_8;
737 break;
738 default:
739 return -EINVAL;
740 }
741
742 snd_soc_component_update_bits(component, RT1015_TDM_MASTER,
743 RT1015_I2S_DL_MASK, val: val_len);
744 snd_soc_component_update_bits(component, RT1015_CLK2,
745 RT1015_FS_PD_MASK, val: pre_div << RT1015_FS_PD_SFT);
746
747 return 0;
748}
749
750static int rt1015_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
751{
752 struct snd_soc_component *component = dai->component;
753 unsigned int reg_val = 0, reg_val2 = 0;
754
755 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
756 case SND_SOC_DAIFMT_CBP_CFP:
757 reg_val |= RT1015_TCON_TDM_MS_M;
758 break;
759 case SND_SOC_DAIFMT_CBC_CFC:
760 reg_val |= RT1015_TCON_TDM_MS_S;
761 break;
762 default:
763 return -EINVAL;
764 }
765
766 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
767 case SND_SOC_DAIFMT_NB_NF:
768 break;
769 case SND_SOC_DAIFMT_IB_NF:
770 reg_val2 |= RT1015_TDM_INV_BCLK;
771 break;
772 default:
773 return -EINVAL;
774 }
775
776 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
777 case SND_SOC_DAIFMT_I2S:
778 break;
779
780 case SND_SOC_DAIFMT_LEFT_J:
781 reg_val |= RT1015_I2S_M_DF_LEFT;
782 break;
783
784 case SND_SOC_DAIFMT_DSP_A:
785 reg_val |= RT1015_I2S_M_DF_PCM_A;
786 break;
787
788 case SND_SOC_DAIFMT_DSP_B:
789 reg_val |= RT1015_I2S_M_DF_PCM_B;
790 break;
791
792 default:
793 return -EINVAL;
794 }
795
796 snd_soc_component_update_bits(component, RT1015_TDM_MASTER,
797 RT1015_TCON_TDM_MS_MASK | RT1015_I2S_M_DF_MASK,
798 val: reg_val);
799 snd_soc_component_update_bits(component, RT1015_TDM1_1,
800 RT1015_TDM_INV_BCLK_MASK, val: reg_val2);
801
802 return 0;
803}
804
805static int rt1015_set_component_sysclk(struct snd_soc_component *component,
806 int clk_id, int source, unsigned int freq, int dir)
807{
808 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(c: component);
809 unsigned int reg_val = 0;
810
811 if (freq == rt1015->sysclk && clk_id == rt1015->sysclk_src)
812 return 0;
813
814 switch (clk_id) {
815 case RT1015_SCLK_S_MCLK:
816 reg_val |= RT1015_CLK_SYS_PRE_SEL_MCLK;
817 break;
818
819 case RT1015_SCLK_S_PLL:
820 reg_val |= RT1015_CLK_SYS_PRE_SEL_PLL;
821 break;
822
823 default:
824 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
825 return -EINVAL;
826 }
827
828 rt1015->sysclk = freq;
829 rt1015->sysclk_src = clk_id;
830
831 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
832 freq, clk_id);
833
834 snd_soc_component_update_bits(component, RT1015_CLK2,
835 RT1015_CLK_SYS_PRE_SEL_MASK, val: reg_val);
836
837 return 0;
838}
839
840static int rt1015_set_component_pll(struct snd_soc_component *component,
841 int pll_id, int source, unsigned int freq_in,
842 unsigned int freq_out)
843{
844 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(c: component);
845 struct rl6231_pll_code pll_code;
846 int ret;
847
848 if (!freq_in || !freq_out) {
849 dev_dbg(component->dev, "PLL disabled\n");
850
851 rt1015->pll_in = 0;
852 rt1015->pll_out = 0;
853
854 return 0;
855 }
856
857 if (source == rt1015->pll_src && freq_in == rt1015->pll_in &&
858 freq_out == rt1015->pll_out)
859 return 0;
860
861 switch (source) {
862 case RT1015_PLL_S_MCLK:
863 snd_soc_component_update_bits(component, RT1015_CLK2,
864 RT1015_PLL_SEL_MASK, RT1015_PLL_SEL_PLL_SRC2);
865 break;
866
867 case RT1015_PLL_S_BCLK:
868 snd_soc_component_update_bits(component, RT1015_CLK2,
869 RT1015_PLL_SEL_MASK, RT1015_PLL_SEL_BCLK);
870 break;
871
872 default:
873 dev_err(component->dev, "Unknown PLL Source %d\n", source);
874 return -EINVAL;
875 }
876
877 ret = rl6231_pll_calc(freq_in, freq_out, pll_code: &pll_code);
878 if (ret < 0) {
879 dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
880 return ret;
881 }
882
883 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
884 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
885 pll_code.n_code, pll_code.k_code);
886
887 snd_soc_component_write(component, RT1015_PLL1,
888 val: ((pll_code.m_bp ? 0 : pll_code.m_code) << RT1015_PLL_M_SFT) |
889 (pll_code.m_bp << RT1015_PLL_M_BP_SFT) |
890 pll_code.n_code);
891 snd_soc_component_write(component, RT1015_PLL2,
892 val: pll_code.k_code);
893
894 rt1015->pll_in = freq_in;
895 rt1015->pll_out = freq_out;
896 rt1015->pll_src = source;
897
898 return 0;
899}
900
901static int rt1015_set_tdm_slot(struct snd_soc_dai *dai,
902 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
903{
904 struct snd_soc_component *component = dai->component;
905 unsigned int val = 0, rx_slotnum, tx_slotnum;
906 int ret = 0, first_bit;
907
908 switch (slots) {
909 case 2:
910 val |= RT1015_I2S_TX_2CH;
911 break;
912 case 4:
913 val |= RT1015_I2S_TX_4CH;
914 break;
915 case 6:
916 val |= RT1015_I2S_TX_6CH;
917 break;
918 case 8:
919 val |= RT1015_I2S_TX_8CH;
920 break;
921 default:
922 ret = -EINVAL;
923 goto _set_tdm_err_;
924 }
925
926 switch (slot_width) {
927 case 16:
928 val |= RT1015_I2S_CH_TX_LEN_16B;
929 break;
930 case 20:
931 val |= RT1015_I2S_CH_TX_LEN_20B;
932 break;
933 case 24:
934 val |= RT1015_I2S_CH_TX_LEN_24B;
935 break;
936 case 32:
937 val |= RT1015_I2S_CH_TX_LEN_32B;
938 break;
939 default:
940 ret = -EINVAL;
941 goto _set_tdm_err_;
942 }
943
944 /* Rx slot configuration */
945 rx_slotnum = hweight_long(w: rx_mask);
946 if (rx_slotnum != 1) {
947 ret = -EINVAL;
948 dev_err(component->dev, "too many rx slots or zero slot\n");
949 goto _set_tdm_err_;
950 }
951
952 /* This is an assumption that the system sends stereo audio to the amplifier typically.
953 * And the stereo audio is placed in slot 0/2/4/6 as the starting slot.
954 * The users could select the channel from L/R/L+R by "Mono LR Select" control.
955 */
956 first_bit = __ffs(rx_mask);
957 switch (first_bit) {
958 case 0:
959 case 2:
960 case 4:
961 case 6:
962 snd_soc_component_update_bits(component,
963 RT1015_TDM1_4,
964 RT1015_TDM_I2S_TX_L_DAC1_1_MASK |
965 RT1015_TDM_I2S_TX_R_DAC1_1_MASK,
966 val: (first_bit << RT1015_TDM_I2S_TX_L_DAC1_1_SFT) |
967 ((first_bit+1) << RT1015_TDM_I2S_TX_R_DAC1_1_SFT));
968 break;
969 case 1:
970 case 3:
971 case 5:
972 case 7:
973 snd_soc_component_update_bits(component,
974 RT1015_TDM1_4,
975 RT1015_TDM_I2S_TX_L_DAC1_1_MASK |
976 RT1015_TDM_I2S_TX_R_DAC1_1_MASK,
977 val: ((first_bit-1) << RT1015_TDM_I2S_TX_L_DAC1_1_SFT) |
978 (first_bit << RT1015_TDM_I2S_TX_R_DAC1_1_SFT));
979 break;
980 default:
981 ret = -EINVAL;
982 goto _set_tdm_err_;
983 }
984
985 /* Tx slot configuration */
986 tx_slotnum = hweight_long(w: tx_mask);
987 if (tx_slotnum) {
988 ret = -EINVAL;
989 dev_err(component->dev, "doesn't need to support tx slots\n");
990 goto _set_tdm_err_;
991 }
992
993 snd_soc_component_update_bits(component, RT1015_TDM1_1,
994 RT1015_I2S_CH_TX_MASK | RT1015_I2S_CH_RX_MASK |
995 RT1015_I2S_CH_TX_LEN_MASK | RT1015_I2S_CH_RX_LEN_MASK, val);
996
997_set_tdm_err_:
998 return ret;
999}
1000
1001static int rt1015_probe(struct snd_soc_component *component)
1002{
1003 struct rt1015_priv *rt1015 =
1004 snd_soc_component_get_drvdata(c: component);
1005
1006 rt1015->component = component;
1007
1008 return 0;
1009}
1010
1011static void rt1015_remove(struct snd_soc_component *component)
1012{
1013 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(c: component);
1014
1015 regmap_write(map: rt1015->regmap, RT1015_RESET, val: 0);
1016}
1017
1018#define RT1015_STEREO_RATES SNDRV_PCM_RATE_8000_192000
1019#define RT1015_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1020 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1021
1022static const struct snd_soc_dai_ops rt1015_aif_dai_ops = {
1023 .hw_params = rt1015_hw_params,
1024 .set_fmt = rt1015_set_dai_fmt,
1025 .set_tdm_slot = rt1015_set_tdm_slot,
1026};
1027
1028static struct snd_soc_dai_driver rt1015_dai[] = {
1029 {
1030 .name = "rt1015-aif",
1031 .id = 0,
1032 .playback = {
1033 .stream_name = "AIF Playback",
1034 .channels_min = 1,
1035 .channels_max = 4,
1036 .rates = RT1015_STEREO_RATES,
1037 .formats = RT1015_FORMATS,
1038 },
1039 .ops = &rt1015_aif_dai_ops,
1040 }
1041};
1042
1043#ifdef CONFIG_PM
1044static int rt1015_suspend(struct snd_soc_component *component)
1045{
1046 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(c: component);
1047
1048 regcache_cache_only(map: rt1015->regmap, enable: true);
1049 regcache_mark_dirty(map: rt1015->regmap);
1050
1051 return 0;
1052}
1053
1054static int rt1015_resume(struct snd_soc_component *component)
1055{
1056 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(c: component);
1057
1058 regcache_cache_only(map: rt1015->regmap, enable: false);
1059 regcache_sync(map: rt1015->regmap);
1060
1061 if (rt1015->cali_done)
1062 rt1015_calibrate(rt1015);
1063
1064 return 0;
1065}
1066#else
1067#define rt1015_suspend NULL
1068#define rt1015_resume NULL
1069#endif
1070
1071static const struct snd_soc_component_driver soc_component_dev_rt1015 = {
1072 .probe = rt1015_probe,
1073 .remove = rt1015_remove,
1074 .suspend = rt1015_suspend,
1075 .resume = rt1015_resume,
1076 .controls = rt1015_snd_controls,
1077 .num_controls = ARRAY_SIZE(rt1015_snd_controls),
1078 .dapm_widgets = rt1015_dapm_widgets,
1079 .num_dapm_widgets = ARRAY_SIZE(rt1015_dapm_widgets),
1080 .dapm_routes = rt1015_dapm_routes,
1081 .num_dapm_routes = ARRAY_SIZE(rt1015_dapm_routes),
1082 .set_sysclk = rt1015_set_component_sysclk,
1083 .set_pll = rt1015_set_component_pll,
1084 .use_pmdown_time = 1,
1085 .endianness = 1,
1086};
1087
1088static const struct regmap_config rt1015_regmap = {
1089 .reg_bits = 16,
1090 .val_bits = 16,
1091 .max_register = RT1015_S_BST_TIMING_INTER36,
1092 .volatile_reg = rt1015_volatile_register,
1093 .readable_reg = rt1015_readable_register,
1094 .cache_type = REGCACHE_RBTREE,
1095 .reg_defaults = rt1015_reg,
1096 .num_reg_defaults = ARRAY_SIZE(rt1015_reg),
1097};
1098
1099static const struct i2c_device_id rt1015_i2c_id[] = {
1100 { "rt1015" },
1101 { }
1102};
1103MODULE_DEVICE_TABLE(i2c, rt1015_i2c_id);
1104
1105#if defined(CONFIG_OF)
1106static const struct of_device_id rt1015_of_match[] = {
1107 { .compatible = "realtek,rt1015", },
1108 { }
1109};
1110MODULE_DEVICE_TABLE(of, rt1015_of_match);
1111#endif
1112
1113#ifdef CONFIG_ACPI
1114static const struct acpi_device_id rt1015_acpi_match[] = {
1115 { "10EC1015" },
1116 { }
1117};
1118MODULE_DEVICE_TABLE(acpi, rt1015_acpi_match);
1119#endif
1120
1121static void rt1015_parse_dt(struct rt1015_priv *rt1015, struct device *dev)
1122{
1123 device_property_read_u32(dev, propname: "realtek,power-up-delay-ms",
1124 val: &rt1015->pdata.power_up_delay_ms);
1125}
1126
1127static int rt1015_i2c_probe(struct i2c_client *i2c)
1128{
1129 struct rt1015_platform_data *pdata = dev_get_platdata(dev: &i2c->dev);
1130 struct rt1015_priv *rt1015;
1131 int ret;
1132 unsigned int val;
1133
1134 rt1015 = devm_kzalloc(dev: &i2c->dev, size: sizeof(*rt1015), GFP_KERNEL);
1135 if (!rt1015)
1136 return -ENOMEM;
1137
1138 i2c_set_clientdata(client: i2c, data: rt1015);
1139
1140 rt1015->pdata = i2s_default_platform_data;
1141
1142 if (pdata)
1143 rt1015->pdata = *pdata;
1144 else
1145 rt1015_parse_dt(rt1015, dev: &i2c->dev);
1146
1147 rt1015->regmap = devm_regmap_init_i2c(i2c, &rt1015_regmap);
1148 if (IS_ERR(ptr: rt1015->regmap)) {
1149 ret = PTR_ERR(ptr: rt1015->regmap);
1150 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1151 ret);
1152 return ret;
1153 }
1154
1155 ret = regmap_read(map: rt1015->regmap, RT1015_DEVICE_ID, val: &val);
1156 if (ret) {
1157 dev_err(&i2c->dev,
1158 "Failed to read device register: %d\n", ret);
1159 return ret;
1160 } else if ((val != RT1015_DEVICE_ID_VAL) &&
1161 (val != RT1015_DEVICE_ID_VAL2)) {
1162 dev_err(&i2c->dev,
1163 "Device with ID register %x is not rt1015\n", val);
1164 return -ENODEV;
1165 }
1166
1167 return devm_snd_soc_register_component(dev: &i2c->dev,
1168 component_driver: &soc_component_dev_rt1015,
1169 dai_drv: rt1015_dai, ARRAY_SIZE(rt1015_dai));
1170}
1171
1172static void rt1015_i2c_shutdown(struct i2c_client *client)
1173{
1174 struct rt1015_priv *rt1015 = i2c_get_clientdata(client);
1175
1176 regmap_write(map: rt1015->regmap, RT1015_RESET, val: 0);
1177}
1178
1179static struct i2c_driver rt1015_i2c_driver = {
1180 .driver = {
1181 .name = "rt1015",
1182 .of_match_table = of_match_ptr(rt1015_of_match),
1183 .acpi_match_table = ACPI_PTR(rt1015_acpi_match),
1184 },
1185 .probe = rt1015_i2c_probe,
1186 .shutdown = rt1015_i2c_shutdown,
1187 .id_table = rt1015_i2c_id,
1188};
1189module_i2c_driver(rt1015_i2c_driver);
1190
1191MODULE_DESCRIPTION("ASoC RT1015 driver");
1192MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
1193MODULE_LICENSE("GPL v2");
1194

source code of linux/sound/soc/codecs/rt1015.c