1// SPDX-License-Identifier: GPL-2.0
2//
3// rt1015.c -- RT1015 ALSA SoC audio amplifier driver
4//
5// Copyright 2019 Realtek Semiconductor Corp.
6//
7// Author: Jack Yu <jack.yu@realtek.com>
8//
9//
10
11#include <linux/acpi.h>
12#include <linux/delay.h>
13#include <linux/firmware.h>
14#include <linux/fs.h>
15#include <linux/i2c.h>
16#include <linux/init.h>
17#include <linux/module.h>
18#include <linux/moduleparam.h>
19#include <linux/platform_device.h>
20#include <linux/pm.h>
21#include <linux/regmap.h>
22#include <sound/core.h>
23#include <sound/initval.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/rt1015.h>
27#include <sound/soc-dapm.h>
28#include <sound/soc.h>
29#include <sound/tlv.h>
30
31#include "rl6231.h"
32#include "rt1015.h"
33
34static const struct rt1015_platform_data i2s_default_platform_data = {
35 .power_up_delay_ms = 50,
36};
37
38static const struct reg_default rt1015_reg[] = {
39 { 0x0000, 0x0000 },
40 { 0x0004, 0xa000 },
41 { 0x0006, 0x0003 },
42 { 0x000a, 0x081e },
43 { 0x000c, 0x0006 },
44 { 0x000e, 0x0000 },
45 { 0x0010, 0x0000 },
46 { 0x0012, 0x0000 },
47 { 0x0014, 0x0000 },
48 { 0x0016, 0x0000 },
49 { 0x0018, 0x0000 },
50 { 0x0020, 0x8000 },
51 { 0x0022, 0x8043 },
52 { 0x0076, 0x0000 },
53 { 0x0078, 0x0000 },
54 { 0x007a, 0x0002 },
55 { 0x007c, 0x10ec },
56 { 0x007d, 0x1015 },
57 { 0x00f0, 0x5000 },
58 { 0x00f2, 0x004c },
59 { 0x00f3, 0xecfe },
60 { 0x00f4, 0x0000 },
61 { 0x00f6, 0x0400 },
62 { 0x0100, 0x0028 },
63 { 0x0102, 0xff02 },
64 { 0x0104, 0xa213 },
65 { 0x0106, 0x200c },
66 { 0x010c, 0x0000 },
67 { 0x010e, 0x0058 },
68 { 0x0111, 0x0200 },
69 { 0x0112, 0x0400 },
70 { 0x0114, 0x0022 },
71 { 0x0116, 0x0000 },
72 { 0x0118, 0x0000 },
73 { 0x011a, 0x0123 },
74 { 0x011c, 0x4567 },
75 { 0x0300, 0x203d },
76 { 0x0302, 0x001e },
77 { 0x0311, 0x0000 },
78 { 0x0313, 0x6014 },
79 { 0x0314, 0x00a2 },
80 { 0x031a, 0x00a0 },
81 { 0x031c, 0x001f },
82 { 0x031d, 0xffff },
83 { 0x031e, 0x0000 },
84 { 0x031f, 0x0000 },
85 { 0x0320, 0x0000 },
86 { 0x0321, 0x0000 },
87 { 0x0322, 0xd7df },
88 { 0x0328, 0x10b2 },
89 { 0x0329, 0x0175 },
90 { 0x032a, 0x36ad },
91 { 0x032b, 0x7e55 },
92 { 0x032c, 0x0520 },
93 { 0x032d, 0xaa00 },
94 { 0x032e, 0x570e },
95 { 0x0330, 0xe180 },
96 { 0x0332, 0x0034 },
97 { 0x0334, 0x0001 },
98 { 0x0336, 0x0010 },
99 { 0x0338, 0x0000 },
100 { 0x04fa, 0x0030 },
101 { 0x04fc, 0x35c8 },
102 { 0x04fe, 0x0800 },
103 { 0x0500, 0x0400 },
104 { 0x0502, 0x1000 },
105 { 0x0504, 0x0000 },
106 { 0x0506, 0x04ff },
107 { 0x0508, 0x0010 },
108 { 0x050a, 0x001a },
109 { 0x0519, 0x1c68 },
110 { 0x051a, 0x0ccc },
111 { 0x051b, 0x0666 },
112 { 0x051d, 0x0000 },
113 { 0x051f, 0x0000 },
114 { 0x0536, 0x061c },
115 { 0x0538, 0x0000 },
116 { 0x053a, 0x0000 },
117 { 0x053c, 0x0000 },
118 { 0x053d, 0x0000 },
119 { 0x053e, 0x0000 },
120 { 0x053f, 0x0000 },
121 { 0x0540, 0x0000 },
122 { 0x0541, 0x0000 },
123 { 0x0542, 0x0000 },
124 { 0x0543, 0x0000 },
125 { 0x0544, 0x0000 },
126 { 0x0568, 0x0000 },
127 { 0x056a, 0x0000 },
128 { 0x1000, 0x0040 },
129 { 0x1002, 0x5405 },
130 { 0x1006, 0x5515 },
131 { 0x1007, 0x05f7 },
132 { 0x1009, 0x0b0a },
133 { 0x100a, 0x00ef },
134 { 0x100d, 0x0003 },
135 { 0x1010, 0xa433 },
136 { 0x1020, 0x0000 },
137 { 0x1200, 0x5a01 },
138 { 0x1202, 0x6524 },
139 { 0x1204, 0x1f00 },
140 { 0x1206, 0x0000 },
141 { 0x1208, 0x0000 },
142 { 0x120a, 0x0000 },
143 { 0x120c, 0x0000 },
144 { 0x120e, 0x0000 },
145 { 0x1210, 0x0000 },
146 { 0x1212, 0x0000 },
147 { 0x1300, 0x10a1 },
148 { 0x1302, 0x12ff },
149 { 0x1304, 0x0400 },
150 { 0x1305, 0x0844 },
151 { 0x1306, 0x4611 },
152 { 0x1308, 0x555e },
153 { 0x130a, 0x0000 },
154 { 0x130c, 0x2000 },
155 { 0x130e, 0x0100 },
156 { 0x130f, 0x0001 },
157 { 0x1310, 0x0000 },
158 { 0x1312, 0x0000 },
159 { 0x1314, 0x0000 },
160 { 0x1316, 0x0000 },
161 { 0x1318, 0x0000 },
162 { 0x131a, 0x0000 },
163 { 0x1322, 0x0029 },
164 { 0x1323, 0x4a52 },
165 { 0x1324, 0x002c },
166 { 0x1325, 0x0b02 },
167 { 0x1326, 0x002d },
168 { 0x1327, 0x6b5a },
169 { 0x1328, 0x002e },
170 { 0x1329, 0xcbb2 },
171 { 0x132a, 0x0030 },
172 { 0x132b, 0x2c0b },
173 { 0x1330, 0x0031 },
174 { 0x1331, 0x8c63 },
175 { 0x1332, 0x0032 },
176 { 0x1333, 0xecbb },
177 { 0x1334, 0x0034 },
178 { 0x1335, 0x4d13 },
179 { 0x1336, 0x0037 },
180 { 0x1337, 0x0dc3 },
181 { 0x1338, 0x003d },
182 { 0x1339, 0xef7b },
183 { 0x133a, 0x0044 },
184 { 0x133b, 0xd134 },
185 { 0x133c, 0x0047 },
186 { 0x133d, 0x91e4 },
187 { 0x133e, 0x004d },
188 { 0x133f, 0xc370 },
189 { 0x1340, 0x0053 },
190 { 0x1341, 0xf4fd },
191 { 0x1342, 0x0060 },
192 { 0x1343, 0x5816 },
193 { 0x1344, 0x006c },
194 { 0x1345, 0xbb2e },
195 { 0x1346, 0x0072 },
196 { 0x1347, 0xecbb },
197 { 0x1348, 0x0076 },
198 { 0x1349, 0x5d97 },
199};
200
201static bool rt1015_volatile_register(struct device *dev, unsigned int reg)
202{
203 switch (reg) {
204 case RT1015_RESET:
205 case RT1015_CLK_DET:
206 case RT1015_SIL_DET:
207 case RT1015_VER_ID:
208 case RT1015_VENDOR_ID:
209 case RT1015_DEVICE_ID:
210 case RT1015_PRO_ALT:
211 case RT1015_MAN_I2C:
212 case RT1015_DAC3:
213 case RT1015_VBAT_TEST_OUT1:
214 case RT1015_VBAT_TEST_OUT2:
215 case RT1015_VBAT_PROT_ATT:
216 case RT1015_VBAT_DET_CODE:
217 case RT1015_SMART_BST_CTRL1:
218 case RT1015_SPK_DC_DETECT1:
219 case RT1015_SPK_DC_DETECT4:
220 case RT1015_SPK_DC_DETECT5:
221 case RT1015_DC_CALIB_CLSD1:
222 case RT1015_DC_CALIB_CLSD5:
223 case RT1015_DC_CALIB_CLSD6:
224 case RT1015_DC_CALIB_CLSD7:
225 case RT1015_DC_CALIB_CLSD8:
226 case RT1015_S_BST_TIMING_INTER1:
227 case RT1015_OSCK_STA:
228 case RT1015_MONO_DYNA_CTRL1:
229 case RT1015_MONO_DYNA_CTRL5:
230 return true;
231
232 default:
233 return false;
234 }
235}
236
237static bool rt1015_readable_register(struct device *dev, unsigned int reg)
238{
239 switch (reg) {
240 case RT1015_RESET:
241 case RT1015_CLK2:
242 case RT1015_CLK3:
243 case RT1015_PLL1:
244 case RT1015_PLL2:
245 case RT1015_DUM_RW1:
246 case RT1015_DUM_RW2:
247 case RT1015_DUM_RW3:
248 case RT1015_DUM_RW4:
249 case RT1015_DUM_RW5:
250 case RT1015_DUM_RW6:
251 case RT1015_CLK_DET:
252 case RT1015_SIL_DET:
253 case RT1015_CUSTOMER_ID:
254 case RT1015_PCODE_FWVER:
255 case RT1015_VER_ID:
256 case RT1015_VENDOR_ID:
257 case RT1015_DEVICE_ID:
258 case RT1015_PAD_DRV1:
259 case RT1015_PAD_DRV2:
260 case RT1015_GAT_BOOST:
261 case RT1015_PRO_ALT:
262 case RT1015_OSCK_STA:
263 case RT1015_MAN_I2C:
264 case RT1015_DAC1:
265 case RT1015_DAC2:
266 case RT1015_DAC3:
267 case RT1015_ADC1:
268 case RT1015_ADC2:
269 case RT1015_TDM_MASTER:
270 case RT1015_TDM_TCON:
271 case RT1015_TDM1_1:
272 case RT1015_TDM1_2:
273 case RT1015_TDM1_3:
274 case RT1015_TDM1_4:
275 case RT1015_TDM1_5:
276 case RT1015_MIXER1:
277 case RT1015_MIXER2:
278 case RT1015_ANA_PROTECT1:
279 case RT1015_ANA_CTRL_SEQ1:
280 case RT1015_ANA_CTRL_SEQ2:
281 case RT1015_VBAT_DET_DEB:
282 case RT1015_VBAT_VOLT_DET1:
283 case RT1015_VBAT_VOLT_DET2:
284 case RT1015_VBAT_TEST_OUT1:
285 case RT1015_VBAT_TEST_OUT2:
286 case RT1015_VBAT_PROT_ATT:
287 case RT1015_VBAT_DET_CODE:
288 case RT1015_PWR1:
289 case RT1015_PWR4:
290 case RT1015_PWR5:
291 case RT1015_PWR6:
292 case RT1015_PWR7:
293 case RT1015_PWR8:
294 case RT1015_PWR9:
295 case RT1015_CLASSD_SEQ:
296 case RT1015_SMART_BST_CTRL1:
297 case RT1015_SMART_BST_CTRL2:
298 case RT1015_ANA_CTRL1:
299 case RT1015_ANA_CTRL2:
300 case RT1015_PWR_STATE_CTRL:
301 case RT1015_MONO_DYNA_CTRL:
302 case RT1015_MONO_DYNA_CTRL1:
303 case RT1015_MONO_DYNA_CTRL2:
304 case RT1015_MONO_DYNA_CTRL3:
305 case RT1015_MONO_DYNA_CTRL4:
306 case RT1015_MONO_DYNA_CTRL5:
307 case RT1015_SPK_VOL:
308 case RT1015_SHORT_DETTOP1:
309 case RT1015_SHORT_DETTOP2:
310 case RT1015_SPK_DC_DETECT1:
311 case RT1015_SPK_DC_DETECT2:
312 case RT1015_SPK_DC_DETECT3:
313 case RT1015_SPK_DC_DETECT4:
314 case RT1015_SPK_DC_DETECT5:
315 case RT1015_BAT_RPO_STEP1:
316 case RT1015_BAT_RPO_STEP2:
317 case RT1015_BAT_RPO_STEP3:
318 case RT1015_BAT_RPO_STEP4:
319 case RT1015_BAT_RPO_STEP5:
320 case RT1015_BAT_RPO_STEP6:
321 case RT1015_BAT_RPO_STEP7:
322 case RT1015_BAT_RPO_STEP8:
323 case RT1015_BAT_RPO_STEP9:
324 case RT1015_BAT_RPO_STEP10:
325 case RT1015_BAT_RPO_STEP11:
326 case RT1015_BAT_RPO_STEP12:
327 case RT1015_SPREAD_SPEC1:
328 case RT1015_SPREAD_SPEC2:
329 case RT1015_PAD_STATUS:
330 case RT1015_PADS_PULLING_CTRL1:
331 case RT1015_PADS_DRIVING:
332 case RT1015_SYS_RST1:
333 case RT1015_SYS_RST2:
334 case RT1015_SYS_GATING1:
335 case RT1015_TEST_MODE1:
336 case RT1015_TEST_MODE2:
337 case RT1015_TIMING_CTRL1:
338 case RT1015_PLL_INT:
339 case RT1015_TEST_OUT1:
340 case RT1015_DC_CALIB_CLSD1:
341 case RT1015_DC_CALIB_CLSD2:
342 case RT1015_DC_CALIB_CLSD3:
343 case RT1015_DC_CALIB_CLSD4:
344 case RT1015_DC_CALIB_CLSD5:
345 case RT1015_DC_CALIB_CLSD6:
346 case RT1015_DC_CALIB_CLSD7:
347 case RT1015_DC_CALIB_CLSD8:
348 case RT1015_DC_CALIB_CLSD9:
349 case RT1015_DC_CALIB_CLSD10:
350 case RT1015_CLSD_INTERNAL1:
351 case RT1015_CLSD_INTERNAL2:
352 case RT1015_CLSD_INTERNAL3:
353 case RT1015_CLSD_INTERNAL4:
354 case RT1015_CLSD_INTERNAL5:
355 case RT1015_CLSD_INTERNAL6:
356 case RT1015_CLSD_INTERNAL7:
357 case RT1015_CLSD_INTERNAL8:
358 case RT1015_CLSD_INTERNAL9:
359 case RT1015_CLSD_OCP_CTRL:
360 case RT1015_VREF_LV:
361 case RT1015_MBIAS1:
362 case RT1015_MBIAS2:
363 case RT1015_MBIAS3:
364 case RT1015_MBIAS4:
365 case RT1015_VREF_LV1:
366 case RT1015_S_BST_TIMING_INTER1:
367 case RT1015_S_BST_TIMING_INTER2:
368 case RT1015_S_BST_TIMING_INTER3:
369 case RT1015_S_BST_TIMING_INTER4:
370 case RT1015_S_BST_TIMING_INTER5:
371 case RT1015_S_BST_TIMING_INTER6:
372 case RT1015_S_BST_TIMING_INTER7:
373 case RT1015_S_BST_TIMING_INTER8:
374 case RT1015_S_BST_TIMING_INTER9:
375 case RT1015_S_BST_TIMING_INTER10:
376 case RT1015_S_BST_TIMING_INTER11:
377 case RT1015_S_BST_TIMING_INTER12:
378 case RT1015_S_BST_TIMING_INTER13:
379 case RT1015_S_BST_TIMING_INTER14:
380 case RT1015_S_BST_TIMING_INTER15:
381 case RT1015_S_BST_TIMING_INTER16:
382 case RT1015_S_BST_TIMING_INTER17:
383 case RT1015_S_BST_TIMING_INTER18:
384 case RT1015_S_BST_TIMING_INTER19:
385 case RT1015_S_BST_TIMING_INTER20:
386 case RT1015_S_BST_TIMING_INTER21:
387 case RT1015_S_BST_TIMING_INTER22:
388 case RT1015_S_BST_TIMING_INTER23:
389 case RT1015_S_BST_TIMING_INTER24:
390 case RT1015_S_BST_TIMING_INTER25:
391 case RT1015_S_BST_TIMING_INTER26:
392 case RT1015_S_BST_TIMING_INTER27:
393 case RT1015_S_BST_TIMING_INTER28:
394 case RT1015_S_BST_TIMING_INTER29:
395 case RT1015_S_BST_TIMING_INTER30:
396 case RT1015_S_BST_TIMING_INTER31:
397 case RT1015_S_BST_TIMING_INTER32:
398 case RT1015_S_BST_TIMING_INTER33:
399 case RT1015_S_BST_TIMING_INTER34:
400 case RT1015_S_BST_TIMING_INTER35:
401 case RT1015_S_BST_TIMING_INTER36:
402 return true;
403
404 default:
405 return false;
406 }
407}
408
409static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9525, 75, 0);
410
411static const char * const rt1015_din_source_select[] = {
412 "Left",
413 "Right",
414 "Left + Right average",
415};
416
417static SOC_ENUM_SINGLE_DECL(rt1015_mono_lr_sel, RT1015_PAD_DRV2, 4,
418 rt1015_din_source_select);
419
420static const char * const rt1015_boost_mode[] = {
421 "Bypass", "Adaptive", "Fixed Adaptive"
422};
423
424static SOC_ENUM_SINGLE_DECL(rt1015_boost_mode_enum, 0, 0,
425 rt1015_boost_mode);
426
427static int rt1015_boost_mode_get(struct snd_kcontrol *kcontrol,
428 struct snd_ctl_elem_value *ucontrol)
429{
430 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
431 struct rt1015_priv *rt1015 =
432 snd_soc_component_get_drvdata(c: component);
433
434 ucontrol->value.integer.value[0] = rt1015->boost_mode;
435
436 return 0;
437}
438
439static int rt1015_boost_mode_put(struct snd_kcontrol *kcontrol,
440 struct snd_ctl_elem_value *ucontrol)
441{
442 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
443 struct rt1015_priv *rt1015 =
444 snd_soc_component_get_drvdata(c: component);
445 int boost_mode = ucontrol->value.integer.value[0];
446
447 switch (boost_mode) {
448 case BYPASS:
449 snd_soc_component_update_bits(component,
450 RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK |
451 RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK,
452 RT1015_ABST_REG_MODE | RT1015_ABST_FIX_TGT_DIS |
453 RT1015_BYPASS_SWRREG_BYPASS);
454 break;
455 case ADAPTIVE:
456 snd_soc_component_update_bits(component,
457 RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK |
458 RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK,
459 RT1015_ABST_AUTO_MODE | RT1015_ABST_FIX_TGT_DIS |
460 RT1015_BYPASS_SWRREG_PASS);
461 break;
462 case FIXED_ADAPTIVE:
463 snd_soc_component_update_bits(component,
464 RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK |
465 RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK,
466 RT1015_ABST_AUTO_MODE | RT1015_ABST_FIX_TGT_EN |
467 RT1015_BYPASS_SWRREG_PASS);
468 break;
469 default:
470 dev_err(component->dev, "Unknown boost control.\n");
471 return -EINVAL;
472 }
473
474 rt1015->boost_mode = boost_mode;
475
476 return 0;
477}
478
479static int rt1015_bypass_boost_get(struct snd_kcontrol *kcontrol,
480 struct snd_ctl_elem_value *ucontrol)
481{
482 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
483 struct rt1015_priv *rt1015 =
484 snd_soc_component_get_drvdata(c: component);
485
486 ucontrol->value.integer.value[0] = rt1015->bypass_boost;
487
488 return 0;
489}
490
491static void rt1015_calibrate(struct rt1015_priv *rt1015)
492{
493 struct snd_soc_component *component = rt1015->component;
494 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
495 struct regmap *regmap = rt1015->regmap;
496
497 snd_soc_dapm_mutex_lock(dapm);
498 regcache_cache_bypass(map: regmap, enable: true);
499
500 regmap_write(map: regmap, RT1015_CLK_DET, val: 0x0000);
501 regmap_write(map: regmap, RT1015_PWR4, val: 0x00B2);
502 regmap_write(map: regmap, RT1015_PWR_STATE_CTRL, val: 0x0009);
503 msleep(msecs: 100);
504 regmap_write(map: regmap, RT1015_PWR_STATE_CTRL, val: 0x000A);
505 msleep(msecs: 100);
506 regmap_write(map: regmap, RT1015_PWR_STATE_CTRL, val: 0x000C);
507 msleep(msecs: 100);
508 regmap_write(map: regmap, RT1015_CLSD_INTERNAL8, val: 0x2028);
509 regmap_write(map: regmap, RT1015_CLSD_INTERNAL9, val: 0x0140);
510 regmap_write(map: regmap, RT1015_PWR_STATE_CTRL, val: 0x000D);
511 msleep(msecs: 300);
512 regmap_write(map: regmap, RT1015_PWR_STATE_CTRL, val: 0x0008);
513 regmap_write(map: regmap, RT1015_SYS_RST1, val: 0x05F5);
514 regmap_write(map: regmap, RT1015_CLK_DET, val: 0x8000);
515
516 regcache_cache_bypass(map: regmap, enable: false);
517 regcache_mark_dirty(map: regmap);
518 regcache_sync(map: regmap);
519 snd_soc_dapm_mutex_unlock(dapm);
520}
521
522static int rt1015_bypass_boost_put(struct snd_kcontrol *kcontrol,
523 struct snd_ctl_elem_value *ucontrol)
524{
525 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
526 struct rt1015_priv *rt1015 =
527 snd_soc_component_get_drvdata(c: component);
528
529 if (rt1015->dac_is_used) {
530 dev_err(component->dev, "DAC is being used!\n");
531 return -EBUSY;
532 }
533
534 rt1015->bypass_boost = ucontrol->value.integer.value[0];
535 if (rt1015->bypass_boost == RT1015_Bypass_Boost &&
536 !rt1015->cali_done) {
537 rt1015_calibrate(rt1015);
538 rt1015->cali_done = 1;
539
540 regmap_write(map: rt1015->regmap, RT1015_MONO_DYNA_CTRL, val: 0x0010);
541 }
542
543 return 0;
544}
545
546static const char * const rt1015_dac_output_vol_select[] = {
547 "immediate",
548 "zero detection + immediate change",
549 "zero detection + inc/dec change",
550 "zero detection + soft inc/dec change",
551};
552
553static SOC_ENUM_SINGLE_DECL(rt1015_dac_vol_ctl_enum,
554 RT1015_DAC3, 2, rt1015_dac_output_vol_select);
555
556static const struct snd_kcontrol_new rt1015_snd_controls[] = {
557 SOC_SINGLE_TLV("DAC Playback Volume", RT1015_DAC1, RT1015_DAC_VOL_SFT,
558 127, 0, dac_vol_tlv),
559 SOC_DOUBLE("DAC Playback Switch", RT1015_DAC3,
560 RT1015_DA_MUTE_SFT, RT1015_DVOL_MUTE_FLAG_SFT, 1, 1),
561 SOC_ENUM_EXT("Boost Mode", rt1015_boost_mode_enum,
562 rt1015_boost_mode_get, rt1015_boost_mode_put),
563 SOC_ENUM("Mono LR Select", rt1015_mono_lr_sel),
564 SOC_SINGLE_EXT("Bypass Boost", SND_SOC_NOPM, 0, 1, 0,
565 rt1015_bypass_boost_get, rt1015_bypass_boost_put),
566
567 /* DAC Output Volume Control */
568 SOC_ENUM("DAC Output Control", rt1015_dac_vol_ctl_enum),
569};
570
571static int rt1015_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
572 struct snd_soc_dapm_widget *sink)
573{
574 struct snd_soc_component *component =
575 snd_soc_dapm_to_component(dapm: source->dapm);
576 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(c: component);
577
578 if (rt1015->sysclk_src == RT1015_SCLK_S_PLL)
579 return 1;
580 else
581 return 0;
582}
583
584static int r1015_dac_event(struct snd_soc_dapm_widget *w,
585 struct snd_kcontrol *kcontrol, int event)
586{
587 struct snd_soc_component *component =
588 snd_soc_dapm_to_component(dapm: w->dapm);
589 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(c: component);
590
591 switch (event) {
592 case SND_SOC_DAPM_PRE_PMU:
593 rt1015->dac_is_used = 1;
594 if (rt1015->bypass_boost == RT1015_Enable_Boost) {
595 snd_soc_component_write(component,
596 RT1015_SYS_RST1, val: 0x05f7);
597 snd_soc_component_write(component,
598 RT1015_SYS_RST2, val: 0x0b0a);
599 snd_soc_component_write(component,
600 RT1015_GAT_BOOST, val: 0xacfe);
601 snd_soc_component_write(component,
602 RT1015_PWR9, val: 0xaa00);
603 snd_soc_component_write(component,
604 RT1015_GAT_BOOST, val: 0xecfe);
605 } else {
606 snd_soc_component_write(component,
607 reg: 0x032d, val: 0xaa60);
608 snd_soc_component_write(component,
609 RT1015_SYS_RST1, val: 0x05f7);
610 snd_soc_component_write(component,
611 RT1015_SYS_RST2, val: 0x0b0a);
612 snd_soc_component_write(component,
613 RT1015_PWR_STATE_CTRL, val: 0x008e);
614 }
615 break;
616
617 case SND_SOC_DAPM_POST_PMD:
618 if (rt1015->bypass_boost == RT1015_Enable_Boost) {
619 snd_soc_component_write(component,
620 RT1015_PWR9, val: 0xa800);
621 snd_soc_component_write(component,
622 RT1015_SYS_RST1, val: 0x05f5);
623 snd_soc_component_write(component,
624 RT1015_SYS_RST2, val: 0x0b9a);
625 } else {
626 snd_soc_component_write(component,
627 reg: 0x032d, val: 0xaa60);
628 snd_soc_component_write(component,
629 RT1015_PWR_STATE_CTRL, val: 0x0088);
630 snd_soc_component_write(component,
631 RT1015_SYS_RST1, val: 0x05f5);
632 snd_soc_component_write(component,
633 RT1015_SYS_RST2, val: 0x0b9a);
634 }
635 rt1015->dac_is_used = 0;
636 break;
637
638 default:
639 break;
640 }
641 return 0;
642}
643
644static int rt1015_amp_drv_event(struct snd_soc_dapm_widget *w,
645 struct snd_kcontrol *kcontrol, int event)
646{
647 struct snd_soc_component *component =
648 snd_soc_dapm_to_component(dapm: w->dapm);
649 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(c: component);
650 unsigned int ret, ret2;
651
652 switch (event) {
653 case SND_SOC_DAPM_PRE_PMU:
654 ret = snd_soc_component_read(component, RT1015_CLK_DET);
655 ret2 = snd_soc_component_read(component, RT1015_SPK_DC_DETECT1);
656 if (!((ret >> 15) & 0x1)) {
657 snd_soc_component_update_bits(component, RT1015_CLK_DET,
658 RT1015_EN_BCLK_DET_MASK, RT1015_EN_BCLK_DET);
659 dev_dbg(component->dev, "BCLK Detection Enabled.\n");
660 }
661 if (!((ret2 >> 12) & 0x1)) {
662 snd_soc_component_update_bits(component, RT1015_SPK_DC_DETECT1,
663 RT1015_EN_CLA_D_DC_DET_MASK, RT1015_EN_CLA_D_DC_DET);
664 dev_dbg(component->dev, "Class-D DC Detection Enabled.\n");
665 }
666 break;
667 case SND_SOC_DAPM_POST_PMU:
668 msleep(msecs: rt1015->pdata.power_up_delay_ms);
669 break;
670 default:
671 break;
672 }
673 return 0;
674}
675
676static const struct snd_soc_dapm_widget rt1015_dapm_widgets[] = {
677 SND_SOC_DAPM_SUPPLY("PLL", RT1015_PWR1, RT1015_PWR_PLL_BIT, 0,
678 NULL, 0),
679 SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0),
680 SND_SOC_DAPM_DAC_E("DAC", NULL, SND_SOC_NOPM, 0, 0,
681 r1015_dac_event, SND_SOC_DAPM_PRE_PMU |
682 SND_SOC_DAPM_POST_PMD),
683 SND_SOC_DAPM_OUT_DRV_E("Amp Drv", SND_SOC_NOPM, 0, 0, NULL, 0,
684 rt1015_amp_drv_event, SND_SOC_DAPM_PRE_PMU |
685 SND_SOC_DAPM_POST_PMU),
686 SND_SOC_DAPM_OUTPUT("SPO"),
687};
688
689static const struct snd_soc_dapm_route rt1015_dapm_routes[] = {
690 { "DAC", NULL, "AIFRX" },
691 { "DAC", NULL, "PLL", rt1015_is_sys_clk_from_pll},
692 { "Amp Drv", NULL, "DAC" },
693 { "SPO", NULL, "Amp Drv" },
694};
695
696static int rt1015_hw_params(struct snd_pcm_substream *substream,
697 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
698{
699 struct snd_soc_component *component = dai->component;
700 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(c: component);
701 int pre_div, frame_size, lrck;
702 unsigned int val_len = 0;
703
704 lrck = params_rate(p: params);
705 pre_div = rl6231_get_clk_info(sclk: rt1015->sysclk, rate: lrck);
706 if (pre_div < 0) {
707 dev_err(component->dev, "Unsupported clock rate\n");
708 return -EINVAL;
709 }
710
711 frame_size = snd_soc_params_to_frame_size(params);
712 if (frame_size < 0) {
713 dev_err(component->dev, "Unsupported frame size: %d\n",
714 frame_size);
715 return -EINVAL;
716 }
717
718 dev_dbg(component->dev, "pre_div is %d for iis %d\n", pre_div, dai->id);
719
720 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
721 lrck, pre_div, dai->id);
722
723 switch (params_width(p: params)) {
724 case 16:
725 break;
726 case 20:
727 val_len = RT1015_I2S_DL_20;
728 break;
729 case 24:
730 val_len = RT1015_I2S_DL_24;
731 break;
732 case 8:
733 val_len = RT1015_I2S_DL_8;
734 break;
735 default:
736 return -EINVAL;
737 }
738
739 snd_soc_component_update_bits(component, RT1015_TDM_MASTER,
740 RT1015_I2S_DL_MASK, val: val_len);
741 snd_soc_component_update_bits(component, RT1015_CLK2,
742 RT1015_FS_PD_MASK, val: pre_div << RT1015_FS_PD_SFT);
743
744 return 0;
745}
746
747static int rt1015_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
748{
749 struct snd_soc_component *component = dai->component;
750 unsigned int reg_val = 0, reg_val2 = 0;
751
752 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
753 case SND_SOC_DAIFMT_CBP_CFP:
754 reg_val |= RT1015_TCON_TDM_MS_M;
755 break;
756 case SND_SOC_DAIFMT_CBC_CFC:
757 reg_val |= RT1015_TCON_TDM_MS_S;
758 break;
759 default:
760 return -EINVAL;
761 }
762
763 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
764 case SND_SOC_DAIFMT_NB_NF:
765 break;
766 case SND_SOC_DAIFMT_IB_NF:
767 reg_val2 |= RT1015_TDM_INV_BCLK;
768 break;
769 default:
770 return -EINVAL;
771 }
772
773 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
774 case SND_SOC_DAIFMT_I2S:
775 break;
776
777 case SND_SOC_DAIFMT_LEFT_J:
778 reg_val |= RT1015_I2S_M_DF_LEFT;
779 break;
780
781 case SND_SOC_DAIFMT_DSP_A:
782 reg_val |= RT1015_I2S_M_DF_PCM_A;
783 break;
784
785 case SND_SOC_DAIFMT_DSP_B:
786 reg_val |= RT1015_I2S_M_DF_PCM_B;
787 break;
788
789 default:
790 return -EINVAL;
791 }
792
793 snd_soc_component_update_bits(component, RT1015_TDM_MASTER,
794 RT1015_TCON_TDM_MS_MASK | RT1015_I2S_M_DF_MASK,
795 val: reg_val);
796 snd_soc_component_update_bits(component, RT1015_TDM1_1,
797 RT1015_TDM_INV_BCLK_MASK, val: reg_val2);
798
799 return 0;
800}
801
802static int rt1015_set_component_sysclk(struct snd_soc_component *component,
803 int clk_id, int source, unsigned int freq, int dir)
804{
805 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(c: component);
806 unsigned int reg_val = 0;
807
808 if (freq == rt1015->sysclk && clk_id == rt1015->sysclk_src)
809 return 0;
810
811 switch (clk_id) {
812 case RT1015_SCLK_S_MCLK:
813 reg_val |= RT1015_CLK_SYS_PRE_SEL_MCLK;
814 break;
815
816 case RT1015_SCLK_S_PLL:
817 reg_val |= RT1015_CLK_SYS_PRE_SEL_PLL;
818 break;
819
820 default:
821 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
822 return -EINVAL;
823 }
824
825 rt1015->sysclk = freq;
826 rt1015->sysclk_src = clk_id;
827
828 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
829 freq, clk_id);
830
831 snd_soc_component_update_bits(component, RT1015_CLK2,
832 RT1015_CLK_SYS_PRE_SEL_MASK, val: reg_val);
833
834 return 0;
835}
836
837static int rt1015_set_component_pll(struct snd_soc_component *component,
838 int pll_id, int source, unsigned int freq_in,
839 unsigned int freq_out)
840{
841 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(c: component);
842 struct rl6231_pll_code pll_code;
843 int ret;
844
845 if (!freq_in || !freq_out) {
846 dev_dbg(component->dev, "PLL disabled\n");
847
848 rt1015->pll_in = 0;
849 rt1015->pll_out = 0;
850
851 return 0;
852 }
853
854 if (source == rt1015->pll_src && freq_in == rt1015->pll_in &&
855 freq_out == rt1015->pll_out)
856 return 0;
857
858 switch (source) {
859 case RT1015_PLL_S_MCLK:
860 snd_soc_component_update_bits(component, RT1015_CLK2,
861 RT1015_PLL_SEL_MASK, RT1015_PLL_SEL_PLL_SRC2);
862 break;
863
864 case RT1015_PLL_S_BCLK:
865 snd_soc_component_update_bits(component, RT1015_CLK2,
866 RT1015_PLL_SEL_MASK, RT1015_PLL_SEL_BCLK);
867 break;
868
869 default:
870 dev_err(component->dev, "Unknown PLL Source %d\n", source);
871 return -EINVAL;
872 }
873
874 ret = rl6231_pll_calc(freq_in, freq_out, pll_code: &pll_code);
875 if (ret < 0) {
876 dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
877 return ret;
878 }
879
880 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
881 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
882 pll_code.n_code, pll_code.k_code);
883
884 snd_soc_component_write(component, RT1015_PLL1,
885 val: ((pll_code.m_bp ? 0 : pll_code.m_code) << RT1015_PLL_M_SFT) |
886 (pll_code.m_bp << RT1015_PLL_M_BP_SFT) |
887 pll_code.n_code);
888 snd_soc_component_write(component, RT1015_PLL2,
889 val: pll_code.k_code);
890
891 rt1015->pll_in = freq_in;
892 rt1015->pll_out = freq_out;
893 rt1015->pll_src = source;
894
895 return 0;
896}
897
898static int rt1015_set_tdm_slot(struct snd_soc_dai *dai,
899 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
900{
901 struct snd_soc_component *component = dai->component;
902 unsigned int val = 0, rx_slotnum, tx_slotnum;
903 int ret = 0, first_bit;
904
905 switch (slots) {
906 case 2:
907 val |= RT1015_I2S_TX_2CH;
908 break;
909 case 4:
910 val |= RT1015_I2S_TX_4CH;
911 break;
912 case 6:
913 val |= RT1015_I2S_TX_6CH;
914 break;
915 case 8:
916 val |= RT1015_I2S_TX_8CH;
917 break;
918 default:
919 ret = -EINVAL;
920 goto _set_tdm_err_;
921 }
922
923 switch (slot_width) {
924 case 16:
925 val |= RT1015_I2S_CH_TX_LEN_16B;
926 break;
927 case 20:
928 val |= RT1015_I2S_CH_TX_LEN_20B;
929 break;
930 case 24:
931 val |= RT1015_I2S_CH_TX_LEN_24B;
932 break;
933 case 32:
934 val |= RT1015_I2S_CH_TX_LEN_32B;
935 break;
936 default:
937 ret = -EINVAL;
938 goto _set_tdm_err_;
939 }
940
941 /* Rx slot configuration */
942 rx_slotnum = hweight_long(w: rx_mask);
943 if (rx_slotnum != 1) {
944 ret = -EINVAL;
945 dev_err(component->dev, "too many rx slots or zero slot\n");
946 goto _set_tdm_err_;
947 }
948
949 /* This is an assumption that the system sends stereo audio to the amplifier typically.
950 * And the stereo audio is placed in slot 0/2/4/6 as the starting slot.
951 * The users could select the channel from L/R/L+R by "Mono LR Select" control.
952 */
953 first_bit = __ffs(rx_mask);
954 switch (first_bit) {
955 case 0:
956 case 2:
957 case 4:
958 case 6:
959 snd_soc_component_update_bits(component,
960 RT1015_TDM1_4,
961 RT1015_TDM_I2S_TX_L_DAC1_1_MASK |
962 RT1015_TDM_I2S_TX_R_DAC1_1_MASK,
963 val: (first_bit << RT1015_TDM_I2S_TX_L_DAC1_1_SFT) |
964 ((first_bit+1) << RT1015_TDM_I2S_TX_R_DAC1_1_SFT));
965 break;
966 case 1:
967 case 3:
968 case 5:
969 case 7:
970 snd_soc_component_update_bits(component,
971 RT1015_TDM1_4,
972 RT1015_TDM_I2S_TX_L_DAC1_1_MASK |
973 RT1015_TDM_I2S_TX_R_DAC1_1_MASK,
974 val: ((first_bit-1) << RT1015_TDM_I2S_TX_L_DAC1_1_SFT) |
975 (first_bit << RT1015_TDM_I2S_TX_R_DAC1_1_SFT));
976 break;
977 default:
978 ret = -EINVAL;
979 goto _set_tdm_err_;
980 }
981
982 /* Tx slot configuration */
983 tx_slotnum = hweight_long(w: tx_mask);
984 if (tx_slotnum) {
985 ret = -EINVAL;
986 dev_err(component->dev, "doesn't need to support tx slots\n");
987 goto _set_tdm_err_;
988 }
989
990 snd_soc_component_update_bits(component, RT1015_TDM1_1,
991 RT1015_I2S_CH_TX_MASK | RT1015_I2S_CH_RX_MASK |
992 RT1015_I2S_CH_TX_LEN_MASK | RT1015_I2S_CH_RX_LEN_MASK, val);
993
994_set_tdm_err_:
995 return ret;
996}
997
998static int rt1015_probe(struct snd_soc_component *component)
999{
1000 struct rt1015_priv *rt1015 =
1001 snd_soc_component_get_drvdata(c: component);
1002
1003 rt1015->component = component;
1004
1005 return 0;
1006}
1007
1008static void rt1015_remove(struct snd_soc_component *component)
1009{
1010 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(c: component);
1011
1012 regmap_write(map: rt1015->regmap, RT1015_RESET, val: 0);
1013}
1014
1015#define RT1015_STEREO_RATES SNDRV_PCM_RATE_8000_192000
1016#define RT1015_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1017 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1018
1019static const struct snd_soc_dai_ops rt1015_aif_dai_ops = {
1020 .hw_params = rt1015_hw_params,
1021 .set_fmt = rt1015_set_dai_fmt,
1022 .set_tdm_slot = rt1015_set_tdm_slot,
1023};
1024
1025static struct snd_soc_dai_driver rt1015_dai[] = {
1026 {
1027 .name = "rt1015-aif",
1028 .id = 0,
1029 .playback = {
1030 .stream_name = "AIF Playback",
1031 .channels_min = 1,
1032 .channels_max = 4,
1033 .rates = RT1015_STEREO_RATES,
1034 .formats = RT1015_FORMATS,
1035 },
1036 .ops = &rt1015_aif_dai_ops,
1037 }
1038};
1039
1040#ifdef CONFIG_PM
1041static int rt1015_suspend(struct snd_soc_component *component)
1042{
1043 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(c: component);
1044
1045 regcache_cache_only(map: rt1015->regmap, enable: true);
1046 regcache_mark_dirty(map: rt1015->regmap);
1047
1048 return 0;
1049}
1050
1051static int rt1015_resume(struct snd_soc_component *component)
1052{
1053 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(c: component);
1054
1055 regcache_cache_only(map: rt1015->regmap, enable: false);
1056 regcache_sync(map: rt1015->regmap);
1057
1058 if (rt1015->cali_done)
1059 rt1015_calibrate(rt1015);
1060
1061 return 0;
1062}
1063#else
1064#define rt1015_suspend NULL
1065#define rt1015_resume NULL
1066#endif
1067
1068static const struct snd_soc_component_driver soc_component_dev_rt1015 = {
1069 .probe = rt1015_probe,
1070 .remove = rt1015_remove,
1071 .suspend = rt1015_suspend,
1072 .resume = rt1015_resume,
1073 .controls = rt1015_snd_controls,
1074 .num_controls = ARRAY_SIZE(rt1015_snd_controls),
1075 .dapm_widgets = rt1015_dapm_widgets,
1076 .num_dapm_widgets = ARRAY_SIZE(rt1015_dapm_widgets),
1077 .dapm_routes = rt1015_dapm_routes,
1078 .num_dapm_routes = ARRAY_SIZE(rt1015_dapm_routes),
1079 .set_sysclk = rt1015_set_component_sysclk,
1080 .set_pll = rt1015_set_component_pll,
1081 .use_pmdown_time = 1,
1082 .endianness = 1,
1083};
1084
1085static const struct regmap_config rt1015_regmap = {
1086 .reg_bits = 16,
1087 .val_bits = 16,
1088 .max_register = RT1015_S_BST_TIMING_INTER36,
1089 .volatile_reg = rt1015_volatile_register,
1090 .readable_reg = rt1015_readable_register,
1091 .cache_type = REGCACHE_RBTREE,
1092 .reg_defaults = rt1015_reg,
1093 .num_reg_defaults = ARRAY_SIZE(rt1015_reg),
1094};
1095
1096static const struct i2c_device_id rt1015_i2c_id[] = {
1097 { "rt1015" },
1098 { }
1099};
1100MODULE_DEVICE_TABLE(i2c, rt1015_i2c_id);
1101
1102#if defined(CONFIG_OF)
1103static const struct of_device_id rt1015_of_match[] = {
1104 { .compatible = "realtek,rt1015", },
1105 { }
1106};
1107MODULE_DEVICE_TABLE(of, rt1015_of_match);
1108#endif
1109
1110#ifdef CONFIG_ACPI
1111static const struct acpi_device_id rt1015_acpi_match[] = {
1112 { "10EC1015" },
1113 { }
1114};
1115MODULE_DEVICE_TABLE(acpi, rt1015_acpi_match);
1116#endif
1117
1118static void rt1015_parse_dt(struct rt1015_priv *rt1015, struct device *dev)
1119{
1120 device_property_read_u32(dev, propname: "realtek,power-up-delay-ms",
1121 val: &rt1015->pdata.power_up_delay_ms);
1122}
1123
1124static int rt1015_i2c_probe(struct i2c_client *i2c)
1125{
1126 struct rt1015_platform_data *pdata = dev_get_platdata(dev: &i2c->dev);
1127 struct rt1015_priv *rt1015;
1128 int ret;
1129 unsigned int val;
1130
1131 rt1015 = devm_kzalloc(dev: &i2c->dev, size: sizeof(*rt1015), GFP_KERNEL);
1132 if (!rt1015)
1133 return -ENOMEM;
1134
1135 i2c_set_clientdata(client: i2c, data: rt1015);
1136
1137 rt1015->pdata = i2s_default_platform_data;
1138
1139 if (pdata)
1140 rt1015->pdata = *pdata;
1141 else
1142 rt1015_parse_dt(rt1015, dev: &i2c->dev);
1143
1144 rt1015->regmap = devm_regmap_init_i2c(i2c, &rt1015_regmap);
1145 if (IS_ERR(ptr: rt1015->regmap)) {
1146 ret = PTR_ERR(ptr: rt1015->regmap);
1147 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1148 ret);
1149 return ret;
1150 }
1151
1152 ret = regmap_read(map: rt1015->regmap, RT1015_DEVICE_ID, val: &val);
1153 if (ret) {
1154 dev_err(&i2c->dev,
1155 "Failed to read device register: %d\n", ret);
1156 return ret;
1157 } else if ((val != RT1015_DEVICE_ID_VAL) &&
1158 (val != RT1015_DEVICE_ID_VAL2)) {
1159 dev_err(&i2c->dev,
1160 "Device with ID register %x is not rt1015\n", val);
1161 return -ENODEV;
1162 }
1163
1164 return devm_snd_soc_register_component(dev: &i2c->dev,
1165 component_driver: &soc_component_dev_rt1015,
1166 dai_drv: rt1015_dai, ARRAY_SIZE(rt1015_dai));
1167}
1168
1169static void rt1015_i2c_shutdown(struct i2c_client *client)
1170{
1171 struct rt1015_priv *rt1015 = i2c_get_clientdata(client);
1172
1173 regmap_write(map: rt1015->regmap, RT1015_RESET, val: 0);
1174}
1175
1176static struct i2c_driver rt1015_i2c_driver = {
1177 .driver = {
1178 .name = "rt1015",
1179 .of_match_table = of_match_ptr(rt1015_of_match),
1180 .acpi_match_table = ACPI_PTR(rt1015_acpi_match),
1181 },
1182 .probe = rt1015_i2c_probe,
1183 .shutdown = rt1015_i2c_shutdown,
1184 .id_table = rt1015_i2c_id,
1185};
1186module_i2c_driver(rt1015_i2c_driver);
1187
1188MODULE_DESCRIPTION("ASoC RT1015 driver");
1189MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
1190MODULE_LICENSE("GPL v2");
1191

source code of linux/sound/soc/codecs/rt1015.c