1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * rt1305.c -- RT1305 ALSA SoC amplifier component driver
4 *
5 * Copyright 2018 Realtek Semiconductor Corp.
6 * Author: Shuming Fan <shumingf@realtek.com>
7 */
8
9#include <linux/module.h>
10#include <linux/moduleparam.h>
11#include <linux/init.h>
12#include <linux/delay.h>
13#include <linux/pm.h>
14#include <linux/acpi.h>
15#include <linux/i2c.h>
16#include <linux/regmap.h>
17#include <linux/platform_device.h>
18#include <linux/firmware.h>
19#include <sound/core.h>
20#include <sound/pcm.h>
21#include <sound/pcm_params.h>
22#include <sound/soc.h>
23#include <sound/soc-dapm.h>
24#include <sound/initval.h>
25#include <sound/tlv.h>
26
27#include "rl6231.h"
28#include "rt1305.h"
29
30
31#define RT1305_PR_RANGE_BASE (0xff + 1)
32#define RT1305_PR_SPACING 0x100
33
34#define RT1305_PR_BASE (RT1305_PR_RANGE_BASE + (0 * RT1305_PR_SPACING))
35
36
37static const struct regmap_range_cfg rt1305_ranges[] = {
38 {
39 .name = "PR",
40 .range_min = RT1305_PR_BASE,
41 .range_max = RT1305_PR_BASE + 0xff,
42 .selector_reg = RT1305_PRIV_INDEX,
43 .selector_mask = 0xff,
44 .selector_shift = 0x0,
45 .window_start = RT1305_PRIV_DATA,
46 .window_len = 0x1,
47 },
48};
49
50
51static const struct reg_sequence init_list[] = {
52
53 { RT1305_PR_BASE + 0xcf, 0x5548 },
54 { RT1305_PR_BASE + 0x5d, 0x0442 },
55 { RT1305_PR_BASE + 0xc1, 0x0320 },
56
57 { RT1305_POWER_STATUS, 0x0000 },
58
59 { RT1305_SPK_TEMP_PROTECTION_1, 0xd6de },
60 { RT1305_SPK_TEMP_PROTECTION_2, 0x0707 },
61 { RT1305_SPK_TEMP_PROTECTION_3, 0x4090 },
62
63 { RT1305_DAC_SET_1, 0xdfdf }, /* 4 ohm 2W */
64 { RT1305_ADC_SET_3, 0x0219 },
65 { RT1305_ADC_SET_1, 0x170f }, /* 0.2 ohm RSense*/
66
67};
68#define RT1305_INIT_REG_LEN ARRAY_SIZE(init_list)
69
70struct rt1305_priv {
71 struct snd_soc_component *component;
72 struct regmap *regmap;
73
74 int sysclk;
75 int sysclk_src;
76 int lrck;
77 int bclk;
78 int master;
79
80 int pll_src;
81 int pll_in;
82 int pll_out;
83};
84
85static const struct reg_default rt1305_reg[] = {
86
87 { 0x04, 0x0400 },
88 { 0x05, 0x0880 },
89 { 0x06, 0x0000 },
90 { 0x07, 0x3100 },
91 { 0x08, 0x8000 },
92 { 0x09, 0x0000 },
93 { 0x0a, 0x087e },
94 { 0x0b, 0x0020 },
95 { 0x0c, 0x0802 },
96 { 0x0d, 0x0020 },
97 { 0x10, 0x1d1d },
98 { 0x11, 0x1d1d },
99 { 0x12, 0xffff },
100 { 0x14, 0x000c },
101 { 0x16, 0x1717 },
102 { 0x17, 0x4000 },
103 { 0x18, 0x0019 },
104 { 0x20, 0x0000 },
105 { 0x22, 0x0000 },
106 { 0x24, 0x0000 },
107 { 0x26, 0x0000 },
108 { 0x28, 0x0000 },
109 { 0x2a, 0x4000 },
110 { 0x2b, 0x3000 },
111 { 0x2d, 0x6000 },
112 { 0x2e, 0x0000 },
113 { 0x2f, 0x8000 },
114 { 0x32, 0x0000 },
115 { 0x39, 0x0001 },
116 { 0x3a, 0x0000 },
117 { 0x3b, 0x1020 },
118 { 0x3c, 0x0000 },
119 { 0x3d, 0x0000 },
120 { 0x3e, 0x4c00 },
121 { 0x3f, 0x3000 },
122 { 0x40, 0x000c },
123 { 0x42, 0x0400 },
124 { 0x46, 0xc22c },
125 { 0x47, 0x0000 },
126 { 0x4b, 0x0000 },
127 { 0x4c, 0x0300 },
128 { 0x4f, 0xf000 },
129 { 0x50, 0xc200 },
130 { 0x51, 0x1f1f },
131 { 0x52, 0x01f0 },
132 { 0x53, 0x407f },
133 { 0x54, 0xffff },
134 { 0x58, 0x4005 },
135 { 0x5e, 0x0000 },
136 { 0x5f, 0x0000 },
137 { 0x60, 0xee13 },
138 { 0x62, 0x0000 },
139 { 0x63, 0x5f5f },
140 { 0x64, 0x0040 },
141 { 0x65, 0x4000 },
142 { 0x66, 0x4004 },
143 { 0x67, 0x0306 },
144 { 0x68, 0x8c04 },
145 { 0x69, 0xe021 },
146 { 0x6a, 0x0000 },
147 { 0x6c, 0xaaaa },
148 { 0x70, 0x0333 },
149 { 0x71, 0x3330 },
150 { 0x72, 0x3333 },
151 { 0x73, 0x3300 },
152 { 0x74, 0x0000 },
153 { 0x75, 0x0000 },
154 { 0x76, 0x0000 },
155 { 0x7a, 0x0003 },
156 { 0x7c, 0x10ec },
157 { 0x7e, 0x6251 },
158 { 0x80, 0x0800 },
159 { 0x81, 0x4000 },
160 { 0x82, 0x0000 },
161 { 0x90, 0x7a01 },
162 { 0x91, 0x8431 },
163 { 0x92, 0x0180 },
164 { 0x93, 0x0000 },
165 { 0x94, 0x0000 },
166 { 0x95, 0x0000 },
167 { 0x96, 0x0000 },
168 { 0x97, 0x0000 },
169 { 0x98, 0x0000 },
170 { 0x99, 0x0000 },
171 { 0x9a, 0x0000 },
172 { 0x9b, 0x0000 },
173 { 0x9c, 0x0000 },
174 { 0x9d, 0x0000 },
175 { 0x9e, 0x0000 },
176 { 0x9f, 0x0000 },
177 { 0xa0, 0x0000 },
178 { 0xb0, 0x8200 },
179 { 0xb1, 0x00ff },
180 { 0xb2, 0x0008 },
181 { 0xc0, 0x0200 },
182 { 0xc1, 0x0000 },
183 { 0xc2, 0x0000 },
184 { 0xc3, 0x0000 },
185 { 0xc4, 0x0000 },
186 { 0xc5, 0x0000 },
187 { 0xc6, 0x0000 },
188 { 0xc7, 0x0000 },
189 { 0xc8, 0x0000 },
190 { 0xc9, 0x0000 },
191 { 0xca, 0x0200 },
192 { 0xcb, 0x0000 },
193 { 0xcc, 0x0000 },
194 { 0xcd, 0x0000 },
195 { 0xce, 0x0000 },
196 { 0xcf, 0x0000 },
197 { 0xd0, 0x0000 },
198 { 0xd1, 0x0000 },
199 { 0xd2, 0x0000 },
200 { 0xd3, 0x0000 },
201 { 0xd4, 0x0200 },
202 { 0xd5, 0x0000 },
203 { 0xd6, 0x0000 },
204 { 0xd7, 0x0000 },
205 { 0xd8, 0x0000 },
206 { 0xd9, 0x0000 },
207 { 0xda, 0x0000 },
208 { 0xdb, 0x0000 },
209 { 0xdc, 0x0000 },
210 { 0xdd, 0x0000 },
211 { 0xde, 0x0200 },
212 { 0xdf, 0x0000 },
213 { 0xe0, 0x0000 },
214 { 0xe1, 0x0000 },
215 { 0xe2, 0x0000 },
216 { 0xe3, 0x0000 },
217 { 0xe4, 0x0000 },
218 { 0xe5, 0x0000 },
219 { 0xe6, 0x0000 },
220 { 0xe7, 0x0000 },
221 { 0xe8, 0x0200 },
222 { 0xe9, 0x0000 },
223 { 0xea, 0x0000 },
224 { 0xeb, 0x0000 },
225 { 0xec, 0x0000 },
226 { 0xed, 0x0000 },
227 { 0xee, 0x0000 },
228 { 0xef, 0x0000 },
229 { 0xf0, 0x0000 },
230 { 0xf1, 0x0000 },
231 { 0xf2, 0x0200 },
232 { 0xf3, 0x0000 },
233 { 0xf4, 0x0000 },
234 { 0xf5, 0x0000 },
235 { 0xf6, 0x0000 },
236 { 0xf7, 0x0000 },
237 { 0xf8, 0x0000 },
238 { 0xf9, 0x0000 },
239 { 0xfa, 0x0000 },
240 { 0xfb, 0x0000 },
241};
242
243static int rt1305_reg_init(struct snd_soc_component *component)
244{
245 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(c: component);
246
247 regmap_multi_reg_write(map: rt1305->regmap, regs: init_list, RT1305_INIT_REG_LEN);
248 return 0;
249}
250
251static bool rt1305_volatile_register(struct device *dev, unsigned int reg)
252{
253 int i;
254
255 for (i = 0; i < ARRAY_SIZE(rt1305_ranges); i++) {
256 if (reg >= rt1305_ranges[i].range_min &&
257 reg <= rt1305_ranges[i].range_max) {
258 return true;
259 }
260 }
261
262 switch (reg) {
263 case RT1305_RESET:
264 case RT1305_SPDIF_IN_SET_1:
265 case RT1305_SPDIF_IN_SET_2:
266 case RT1305_SPDIF_IN_SET_3:
267 case RT1305_POWER_CTRL_2:
268 case RT1305_CLOCK_DETECT:
269 case RT1305_BIQUAD_SET_1:
270 case RT1305_BIQUAD_SET_2:
271 case RT1305_EQ_SET_2:
272 case RT1305_SPK_TEMP_PROTECTION_0:
273 case RT1305_SPK_TEMP_PROTECTION_2:
274 case RT1305_SPK_DC_DETECT_1:
275 case RT1305_SILENCE_DETECT:
276 case RT1305_VERSION_ID:
277 case RT1305_VENDOR_ID:
278 case RT1305_DEVICE_ID:
279 case RT1305_EFUSE_1:
280 case RT1305_EFUSE_3:
281 case RT1305_DC_CALIB_1:
282 case RT1305_DC_CALIB_3:
283 case RT1305_DAC_OFFSET_1:
284 case RT1305_DAC_OFFSET_2:
285 case RT1305_DAC_OFFSET_3:
286 case RT1305_DAC_OFFSET_4:
287 case RT1305_DAC_OFFSET_5:
288 case RT1305_DAC_OFFSET_6:
289 case RT1305_DAC_OFFSET_7:
290 case RT1305_DAC_OFFSET_8:
291 case RT1305_DAC_OFFSET_9:
292 case RT1305_DAC_OFFSET_10:
293 case RT1305_DAC_OFFSET_11:
294 case RT1305_TRIM_1:
295 case RT1305_TRIM_2:
296 return true;
297
298 default:
299 return false;
300 }
301}
302
303static bool rt1305_readable_register(struct device *dev, unsigned int reg)
304{
305 int i;
306
307 for (i = 0; i < ARRAY_SIZE(rt1305_ranges); i++) {
308 if (reg >= rt1305_ranges[i].range_min &&
309 reg <= rt1305_ranges[i].range_max) {
310 return true;
311 }
312 }
313
314 switch (reg) {
315 case RT1305_RESET:
316 case RT1305_CLK_1 ... RT1305_CAL_EFUSE_CLOCK:
317 case RT1305_PLL0_1 ... RT1305_PLL1_2:
318 case RT1305_MIXER_CTRL_1:
319 case RT1305_MIXER_CTRL_2:
320 case RT1305_DAC_SET_1:
321 case RT1305_DAC_SET_2:
322 case RT1305_ADC_SET_1:
323 case RT1305_ADC_SET_2:
324 case RT1305_ADC_SET_3:
325 case RT1305_PATH_SET:
326 case RT1305_SPDIF_IN_SET_1:
327 case RT1305_SPDIF_IN_SET_2:
328 case RT1305_SPDIF_IN_SET_3:
329 case RT1305_SPDIF_OUT_SET_1:
330 case RT1305_SPDIF_OUT_SET_2:
331 case RT1305_SPDIF_OUT_SET_3:
332 case RT1305_I2S_SET_1:
333 case RT1305_I2S_SET_2:
334 case RT1305_PBTL_MONO_MODE_SRC:
335 case RT1305_MANUALLY_I2C_DEVICE:
336 case RT1305_POWER_STATUS:
337 case RT1305_POWER_CTRL_1:
338 case RT1305_POWER_CTRL_2:
339 case RT1305_POWER_CTRL_3:
340 case RT1305_POWER_CTRL_4:
341 case RT1305_POWER_CTRL_5:
342 case RT1305_CLOCK_DETECT:
343 case RT1305_BIQUAD_SET_1:
344 case RT1305_BIQUAD_SET_2:
345 case RT1305_ADJUSTED_HPF_1:
346 case RT1305_ADJUSTED_HPF_2:
347 case RT1305_EQ_SET_1:
348 case RT1305_EQ_SET_2:
349 case RT1305_SPK_TEMP_PROTECTION_0:
350 case RT1305_SPK_TEMP_PROTECTION_1:
351 case RT1305_SPK_TEMP_PROTECTION_2:
352 case RT1305_SPK_TEMP_PROTECTION_3:
353 case RT1305_SPK_DC_DETECT_1:
354 case RT1305_SPK_DC_DETECT_2:
355 case RT1305_LOUDNESS:
356 case RT1305_THERMAL_FOLD_BACK_1:
357 case RT1305_THERMAL_FOLD_BACK_2:
358 case RT1305_SILENCE_DETECT ... RT1305_SPK_EXCURSION_LIMITER_7:
359 case RT1305_VERSION_ID:
360 case RT1305_VENDOR_ID:
361 case RT1305_DEVICE_ID:
362 case RT1305_EFUSE_1:
363 case RT1305_EFUSE_2:
364 case RT1305_EFUSE_3:
365 case RT1305_DC_CALIB_1:
366 case RT1305_DC_CALIB_2:
367 case RT1305_DC_CALIB_3:
368 case RT1305_DAC_OFFSET_1 ... RT1305_DAC_OFFSET_14:
369 case RT1305_TRIM_1:
370 case RT1305_TRIM_2:
371 case RT1305_TUNE_INTERNAL_OSC:
372 case RT1305_BIQUAD1_H0_L_28_16 ... RT1305_BIQUAD3_A2_R_15_0:
373 return true;
374 default:
375 return false;
376 }
377}
378
379static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9435, 37, 0);
380
381static const char * const rt1305_rx_data_ch_select[] = {
382 "LR",
383 "RL",
384 "Copy L",
385 "Copy R",
386};
387
388static SOC_ENUM_SINGLE_DECL(rt1305_rx_data_ch_enum, RT1305_I2S_SET_2, 2,
389 rt1305_rx_data_ch_select);
390
391static void rt1305_reset(struct regmap *regmap)
392{
393 regmap_write(map: regmap, RT1305_RESET, val: 0);
394}
395
396static const struct snd_kcontrol_new rt1305_snd_controls[] = {
397 SOC_DOUBLE_TLV("DAC Playback Volume", RT1305_DAC_SET_1,
398 8, 0, 0xff, 0, dac_vol_tlv),
399
400 /* I2S Data Channel Selection */
401 SOC_ENUM("RX Channel Select", rt1305_rx_data_ch_enum),
402};
403
404static int rt1305_is_rc_clk_from_pll(struct snd_soc_dapm_widget *source,
405 struct snd_soc_dapm_widget *sink)
406{
407 struct snd_soc_component *component =
408 snd_soc_dapm_to_component(dapm: source->dapm);
409 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(c: component);
410 unsigned int val;
411
412 val = snd_soc_component_read(component, RT1305_CLK_1);
413
414 if (rt1305->sysclk_src == RT1305_FS_SYS_PRE_S_PLL1 &&
415 (val & RT1305_SEL_PLL_SRC_2_RCCLK))
416 return 1;
417 else
418 return 0;
419}
420
421static int rt1305_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
422 struct snd_soc_dapm_widget *sink)
423{
424 struct snd_soc_component *component =
425 snd_soc_dapm_to_component(dapm: source->dapm);
426 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(c: component);
427
428 if (rt1305->sysclk_src == RT1305_FS_SYS_PRE_S_PLL1)
429 return 1;
430 else
431 return 0;
432}
433
434static int rt1305_classd_event(struct snd_soc_dapm_widget *w,
435 struct snd_kcontrol *kcontrol, int event)
436{
437 struct snd_soc_component *component =
438 snd_soc_dapm_to_component(dapm: w->dapm);
439
440 switch (event) {
441 case SND_SOC_DAPM_POST_PMU:
442 snd_soc_component_update_bits(component, RT1305_POWER_CTRL_1,
443 RT1305_POW_PDB_JD_MASK, RT1305_POW_PDB_JD);
444 break;
445 case SND_SOC_DAPM_PRE_PMD:
446 snd_soc_component_update_bits(component, RT1305_POWER_CTRL_1,
447 RT1305_POW_PDB_JD_MASK, val: 0);
448 usleep_range(min: 150000, max: 200000);
449 break;
450
451 default:
452 return 0;
453 }
454
455 return 0;
456}
457
458static const struct snd_kcontrol_new rt1305_sto_dac_l =
459 SOC_DAPM_SINGLE("Switch", RT1305_DAC_SET_2,
460 RT1305_DVOL_MUTE_L_EN_SFT, 1, 1);
461
462static const struct snd_kcontrol_new rt1305_sto_dac_r =
463 SOC_DAPM_SINGLE("Switch", RT1305_DAC_SET_2,
464 RT1305_DVOL_MUTE_R_EN_SFT, 1, 1);
465
466static const struct snd_soc_dapm_widget rt1305_dapm_widgets[] = {
467 SND_SOC_DAPM_SUPPLY("PLL0", RT1305_POWER_CTRL_1,
468 RT1305_POW_PLL0_EN_BIT, 0, NULL, 0),
469 SND_SOC_DAPM_SUPPLY("PLL1", RT1305_POWER_CTRL_1,
470 RT1305_POW_PLL1_EN_BIT, 0, NULL, 0),
471 SND_SOC_DAPM_SUPPLY("MBIAS", RT1305_POWER_CTRL_1,
472 RT1305_POW_MBIAS_LV_BIT, 0, NULL, 0),
473 SND_SOC_DAPM_SUPPLY("BG MBIAS", RT1305_POWER_CTRL_1,
474 RT1305_POW_BG_MBIAS_LV_BIT, 0, NULL, 0),
475 SND_SOC_DAPM_SUPPLY("LDO2", RT1305_POWER_CTRL_1,
476 RT1305_POW_LDO2_BIT, 0, NULL, 0),
477 SND_SOC_DAPM_SUPPLY("BG2", RT1305_POWER_CTRL_1,
478 RT1305_POW_BG2_BIT, 0, NULL, 0),
479 SND_SOC_DAPM_SUPPLY("LDO2 IB2", RT1305_POWER_CTRL_1,
480 RT1305_POW_LDO2_IB2_BIT, 0, NULL, 0),
481 SND_SOC_DAPM_SUPPLY("VREF", RT1305_POWER_CTRL_1,
482 RT1305_POW_VREF_BIT, 0, NULL, 0),
483 SND_SOC_DAPM_SUPPLY("VREF1", RT1305_POWER_CTRL_1,
484 RT1305_POW_VREF1_BIT, 0, NULL, 0),
485 SND_SOC_DAPM_SUPPLY("VREF2", RT1305_POWER_CTRL_1,
486 RT1305_POW_VREF2_BIT, 0, NULL, 0),
487
488
489 SND_SOC_DAPM_SUPPLY("DISC VREF", RT1305_POWER_CTRL_2,
490 RT1305_POW_DISC_VREF_BIT, 0, NULL, 0),
491 SND_SOC_DAPM_SUPPLY("FASTB VREF", RT1305_POWER_CTRL_2,
492 RT1305_POW_FASTB_VREF_BIT, 0, NULL, 0),
493 SND_SOC_DAPM_SUPPLY("ULTRA FAST VREF", RT1305_POWER_CTRL_2,
494 RT1305_POW_ULTRA_FAST_VREF_BIT, 0, NULL, 0),
495 SND_SOC_DAPM_SUPPLY("CHOP DAC", RT1305_POWER_CTRL_2,
496 RT1305_POW_CKXEN_DAC_BIT, 0, NULL, 0),
497 SND_SOC_DAPM_SUPPLY("CKGEN DAC", RT1305_POWER_CTRL_2,
498 RT1305_POW_EN_CKGEN_DAC_BIT, 0, NULL, 0),
499 SND_SOC_DAPM_SUPPLY("CLAMP", RT1305_POWER_CTRL_2,
500 RT1305_POW_CLAMP_BIT, 0, NULL, 0),
501 SND_SOC_DAPM_SUPPLY("BUFL", RT1305_POWER_CTRL_2,
502 RT1305_POW_BUFL_BIT, 0, NULL, 0),
503 SND_SOC_DAPM_SUPPLY("BUFR", RT1305_POWER_CTRL_2,
504 RT1305_POW_BUFR_BIT, 0, NULL, 0),
505 SND_SOC_DAPM_SUPPLY("CKGEN ADC", RT1305_POWER_CTRL_2,
506 RT1305_POW_EN_CKGEN_ADC_BIT, 0, NULL, 0),
507 SND_SOC_DAPM_SUPPLY("ADC3 L", RT1305_POWER_CTRL_2,
508 RT1305_POW_ADC3_L_BIT, 0, NULL, 0),
509 SND_SOC_DAPM_SUPPLY("ADC3 R", RT1305_POWER_CTRL_2,
510 RT1305_POW_ADC3_R_BIT, 0, NULL, 0),
511 SND_SOC_DAPM_SUPPLY("TRIOSC", RT1305_POWER_CTRL_2,
512 RT1305_POW_TRIOSC_BIT, 0, NULL, 0),
513 SND_SOC_DAPM_SUPPLY("AVDD1", RT1305_POWER_CTRL_2,
514 RT1305_POR_AVDD1_BIT, 0, NULL, 0),
515 SND_SOC_DAPM_SUPPLY("AVDD2", RT1305_POWER_CTRL_2,
516 RT1305_POR_AVDD2_BIT, 0, NULL, 0),
517
518
519 SND_SOC_DAPM_SUPPLY("VSENSE R", RT1305_POWER_CTRL_3,
520 RT1305_POW_VSENSE_RCH_BIT, 0, NULL, 0),
521 SND_SOC_DAPM_SUPPLY("VSENSE L", RT1305_POWER_CTRL_3,
522 RT1305_POW_VSENSE_LCH_BIT, 0, NULL, 0),
523 SND_SOC_DAPM_SUPPLY("ISENSE R", RT1305_POWER_CTRL_3,
524 RT1305_POW_ISENSE_RCH_BIT, 0, NULL, 0),
525 SND_SOC_DAPM_SUPPLY("ISENSE L", RT1305_POWER_CTRL_3,
526 RT1305_POW_ISENSE_LCH_BIT, 0, NULL, 0),
527 SND_SOC_DAPM_SUPPLY("POR AVDD1", RT1305_POWER_CTRL_3,
528 RT1305_POW_POR_AVDD1_BIT, 0, NULL, 0),
529 SND_SOC_DAPM_SUPPLY("POR AVDD2", RT1305_POWER_CTRL_3,
530 RT1305_POW_POR_AVDD2_BIT, 0, NULL, 0),
531 SND_SOC_DAPM_SUPPLY("VCM 6172", RT1305_POWER_CTRL_3,
532 RT1305_EN_VCM_6172_BIT, 0, NULL, 0),
533
534
535 /* Audio Interface */
536 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
537
538 /* Digital Interface */
539 SND_SOC_DAPM_SUPPLY("DAC L Power", RT1305_POWER_CTRL_2,
540 RT1305_POW_DAC1_L_BIT, 0, NULL, 0),
541 SND_SOC_DAPM_SUPPLY("DAC R Power", RT1305_POWER_CTRL_2,
542 RT1305_POW_DAC1_R_BIT, 0, NULL, 0),
543 SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
544 SND_SOC_DAPM_SWITCH("DAC L", SND_SOC_NOPM, 0, 0, &rt1305_sto_dac_l),
545 SND_SOC_DAPM_SWITCH("DAC R", SND_SOC_NOPM, 0, 0, &rt1305_sto_dac_r),
546
547 /* Output Lines */
548 SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0,
549 rt1305_classd_event,
550 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
551 SND_SOC_DAPM_OUTPUT("SPOL"),
552 SND_SOC_DAPM_OUTPUT("SPOR"),
553};
554
555static const struct snd_soc_dapm_route rt1305_dapm_routes[] = {
556
557 { "DAC", NULL, "AIF1RX" },
558
559 { "DAC", NULL, "PLL0", rt1305_is_rc_clk_from_pll },
560 { "DAC", NULL, "PLL1", rt1305_is_sys_clk_from_pll },
561
562 { "DAC", NULL, "MBIAS" },
563 { "DAC", NULL, "BG MBIAS" },
564 { "DAC", NULL, "LDO2" },
565 { "DAC", NULL, "BG2" },
566 { "DAC", NULL, "LDO2 IB2" },
567 { "DAC", NULL, "VREF" },
568 { "DAC", NULL, "VREF1" },
569 { "DAC", NULL, "VREF2" },
570
571 { "DAC", NULL, "DISC VREF" },
572 { "DAC", NULL, "FASTB VREF" },
573 { "DAC", NULL, "ULTRA FAST VREF" },
574 { "DAC", NULL, "CHOP DAC" },
575 { "DAC", NULL, "CKGEN DAC" },
576 { "DAC", NULL, "CLAMP" },
577 { "DAC", NULL, "CKGEN ADC" },
578 { "DAC", NULL, "TRIOSC" },
579 { "DAC", NULL, "AVDD1" },
580 { "DAC", NULL, "AVDD2" },
581
582 { "DAC", NULL, "POR AVDD1" },
583 { "DAC", NULL, "POR AVDD2" },
584 { "DAC", NULL, "VCM 6172" },
585
586 { "DAC L", "Switch", "DAC" },
587 { "DAC R", "Switch", "DAC" },
588
589 { "DAC R", NULL, "VSENSE R" },
590 { "DAC L", NULL, "VSENSE L" },
591 { "DAC R", NULL, "ISENSE R" },
592 { "DAC L", NULL, "ISENSE L" },
593 { "DAC L", NULL, "ADC3 L" },
594 { "DAC R", NULL, "ADC3 R" },
595 { "DAC L", NULL, "BUFL" },
596 { "DAC R", NULL, "BUFR" },
597 { "DAC L", NULL, "DAC L Power" },
598 { "DAC R", NULL, "DAC R Power" },
599
600 { "CLASS D", NULL, "DAC L" },
601 { "CLASS D", NULL, "DAC R" },
602
603 { "SPOL", NULL, "CLASS D" },
604 { "SPOR", NULL, "CLASS D" },
605};
606
607static int rt1305_get_clk_info(int sclk, int rate)
608{
609 int i;
610 static const int pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
611
612 if (sclk <= 0 || rate <= 0)
613 return -EINVAL;
614
615 rate = rate << 8;
616 for (i = 0; i < ARRAY_SIZE(pd); i++)
617 if (sclk == rate * pd[i])
618 return i;
619
620 return -EINVAL;
621}
622
623static int rt1305_hw_params(struct snd_pcm_substream *substream,
624 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
625{
626 struct snd_soc_component *component = dai->component;
627 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(c: component);
628 unsigned int val_len = 0, val_clk, mask_clk;
629 int pre_div, bclk_ms, frame_size;
630
631 rt1305->lrck = params_rate(p: params);
632 pre_div = rt1305_get_clk_info(sclk: rt1305->sysclk, rate: rt1305->lrck);
633 if (pre_div < 0) {
634 dev_warn(component->dev, "Force using PLL ");
635 snd_soc_dai_set_pll(dai, pll_id: 0, source: RT1305_PLL1_S_BCLK,
636 freq_in: rt1305->lrck * 64, freq_out: rt1305->lrck * 256);
637 snd_soc_dai_set_sysclk(dai, clk_id: RT1305_FS_SYS_PRE_S_PLL1,
638 freq: rt1305->lrck * 256, SND_SOC_CLOCK_IN);
639 pre_div = 0;
640 }
641 frame_size = snd_soc_params_to_frame_size(params);
642 if (frame_size < 0) {
643 dev_err(component->dev, "Unsupported frame size: %d\n",
644 frame_size);
645 return -EINVAL;
646 }
647
648 bclk_ms = frame_size > 32;
649 rt1305->bclk = rt1305->lrck * (32 << bclk_ms);
650
651 dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
652 bclk_ms, pre_div, dai->id);
653
654 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
655 rt1305->lrck, pre_div, dai->id);
656
657 switch (params_width(p: params)) {
658 case 16:
659 val_len |= RT1305_I2S_DL_SEL_16B;
660 break;
661 case 20:
662 val_len |= RT1305_I2S_DL_SEL_20B;
663 break;
664 case 24:
665 val_len |= RT1305_I2S_DL_SEL_24B;
666 break;
667 case 8:
668 val_len |= RT1305_I2S_DL_SEL_8B;
669 break;
670 default:
671 return -EINVAL;
672 }
673
674 switch (dai->id) {
675 case RT1305_AIF1:
676 mask_clk = RT1305_DIV_FS_SYS_MASK;
677 val_clk = pre_div << RT1305_DIV_FS_SYS_SFT;
678 snd_soc_component_update_bits(component, RT1305_I2S_SET_2,
679 RT1305_I2S_DL_SEL_MASK,
680 val: val_len);
681 break;
682 default:
683 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
684 return -EINVAL;
685 }
686
687 snd_soc_component_update_bits(component, RT1305_CLK_2,
688 mask: mask_clk, val: val_clk);
689
690 return 0;
691}
692
693static int rt1305_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
694{
695 struct snd_soc_component *component = dai->component;
696 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(c: component);
697 unsigned int reg_val = 0, reg1_val = 0;
698
699 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
700 case SND_SOC_DAIFMT_CBP_CFP:
701 reg_val |= RT1305_SEL_I2S_OUT_MODE_M;
702 rt1305->master = 1;
703 break;
704 case SND_SOC_DAIFMT_CBC_CFC:
705 reg_val |= RT1305_SEL_I2S_OUT_MODE_S;
706 rt1305->master = 0;
707 break;
708 default:
709 return -EINVAL;
710 }
711
712 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
713 case SND_SOC_DAIFMT_NB_NF:
714 break;
715 case SND_SOC_DAIFMT_IB_NF:
716 reg1_val |= RT1305_I2S_BCLK_INV;
717 break;
718 default:
719 return -EINVAL;
720 }
721
722 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
723 case SND_SOC_DAIFMT_I2S:
724 break;
725 case SND_SOC_DAIFMT_LEFT_J:
726 reg1_val |= RT1305_I2S_DF_SEL_LEFT;
727 break;
728 case SND_SOC_DAIFMT_DSP_A:
729 reg1_val |= RT1305_I2S_DF_SEL_PCM_A;
730 break;
731 case SND_SOC_DAIFMT_DSP_B:
732 reg1_val |= RT1305_I2S_DF_SEL_PCM_B;
733 break;
734 default:
735 return -EINVAL;
736 }
737
738 switch (dai->id) {
739 case RT1305_AIF1:
740 snd_soc_component_update_bits(component, RT1305_I2S_SET_1,
741 RT1305_SEL_I2S_OUT_MODE_MASK, val: reg_val);
742 snd_soc_component_update_bits(component, RT1305_I2S_SET_2,
743 RT1305_I2S_DF_SEL_MASK | RT1305_I2S_BCLK_MASK,
744 val: reg1_val);
745 break;
746 default:
747 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
748 return -EINVAL;
749 }
750 return 0;
751}
752
753static int rt1305_set_component_sysclk(struct snd_soc_component *component,
754 int clk_id, int source, unsigned int freq, int dir)
755{
756 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(c: component);
757 unsigned int reg_val = 0;
758
759 if (freq == rt1305->sysclk && clk_id == rt1305->sysclk_src)
760 return 0;
761
762 switch (clk_id) {
763 case RT1305_FS_SYS_PRE_S_MCLK:
764 reg_val |= RT1305_SEL_FS_SYS_PRE_MCLK;
765 snd_soc_component_update_bits(component,
766 RT1305_CLOCK_DETECT, RT1305_SEL_CLK_DET_SRC_MASK,
767 RT1305_SEL_CLK_DET_SRC_MCLK);
768 break;
769 case RT1305_FS_SYS_PRE_S_PLL1:
770 reg_val |= RT1305_SEL_FS_SYS_PRE_PLL;
771 break;
772 case RT1305_FS_SYS_PRE_S_RCCLK:
773 reg_val |= RT1305_SEL_FS_SYS_PRE_RCCLK;
774 break;
775 default:
776 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
777 return -EINVAL;
778 }
779 snd_soc_component_update_bits(component, RT1305_CLK_1,
780 RT1305_SEL_FS_SYS_PRE_MASK, val: reg_val);
781 rt1305->sysclk = freq;
782 rt1305->sysclk_src = clk_id;
783
784 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
785 freq, clk_id);
786
787 return 0;
788}
789
790static int rt1305_set_component_pll(struct snd_soc_component *component,
791 int pll_id, int source, unsigned int freq_in,
792 unsigned int freq_out)
793{
794 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(c: component);
795 struct rl6231_pll_code pll_code;
796 int ret;
797
798 if (source == rt1305->pll_src && freq_in == rt1305->pll_in &&
799 freq_out == rt1305->pll_out)
800 return 0;
801
802 if (!freq_in || !freq_out) {
803 dev_dbg(component->dev, "PLL disabled\n");
804
805 rt1305->pll_in = 0;
806 rt1305->pll_out = 0;
807 snd_soc_component_update_bits(component, RT1305_CLK_1,
808 RT1305_SEL_FS_SYS_PRE_MASK | RT1305_SEL_PLL_SRC_1_MASK,
809 RT1305_SEL_FS_SYS_PRE_PLL | RT1305_SEL_PLL_SRC_1_BCLK);
810 return 0;
811 }
812
813 switch (source) {
814 case RT1305_PLL2_S_MCLK:
815 snd_soc_component_update_bits(component, RT1305_CLK_1,
816 RT1305_SEL_PLL_SRC_2_MASK | RT1305_SEL_PLL_SRC_1_MASK |
817 RT1305_DIV_PLL_SRC_2_MASK,
818 RT1305_SEL_PLL_SRC_2_MCLK | RT1305_SEL_PLL_SRC_1_PLL2);
819 snd_soc_component_update_bits(component,
820 RT1305_CLOCK_DETECT, RT1305_SEL_CLK_DET_SRC_MASK,
821 RT1305_SEL_CLK_DET_SRC_MCLK);
822 break;
823 case RT1305_PLL1_S_BCLK:
824 snd_soc_component_update_bits(component,
825 RT1305_CLK_1, RT1305_SEL_PLL_SRC_1_MASK,
826 RT1305_SEL_PLL_SRC_1_BCLK);
827 break;
828 case RT1305_PLL2_S_RCCLK:
829 snd_soc_component_update_bits(component, RT1305_CLK_1,
830 RT1305_SEL_PLL_SRC_2_MASK | RT1305_SEL_PLL_SRC_1_MASK |
831 RT1305_DIV_PLL_SRC_2_MASK,
832 RT1305_SEL_PLL_SRC_2_RCCLK | RT1305_SEL_PLL_SRC_1_PLL2);
833 freq_in = 98304000;
834 break;
835 default:
836 dev_err(component->dev, "Unknown PLL Source %d\n", source);
837 return -EINVAL;
838 }
839
840 ret = rl6231_pll_calc(freq_in, freq_out, pll_code: &pll_code);
841 if (ret < 0) {
842 dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
843 return ret;
844 }
845
846 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
847 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
848 pll_code.n_code, pll_code.k_code);
849
850 snd_soc_component_write(component, RT1305_PLL1_1,
851 val: ((pll_code.m_bp ? 0 : pll_code.m_code) << RT1305_PLL_1_M_SFT) |
852 (pll_code.m_bp << RT1305_PLL_1_M_BYPASS_SFT) |
853 pll_code.n_code);
854 snd_soc_component_write(component, RT1305_PLL1_2,
855 val: pll_code.k_code);
856
857 rt1305->pll_in = freq_in;
858 rt1305->pll_out = freq_out;
859 rt1305->pll_src = source;
860
861 return 0;
862}
863
864static int rt1305_probe(struct snd_soc_component *component)
865{
866 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(c: component);
867
868 rt1305->component = component;
869
870 /* initial settings */
871 rt1305_reg_init(component);
872
873 return 0;
874}
875
876static void rt1305_remove(struct snd_soc_component *component)
877{
878 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(c: component);
879
880 rt1305_reset(regmap: rt1305->regmap);
881}
882
883#ifdef CONFIG_PM
884static int rt1305_suspend(struct snd_soc_component *component)
885{
886 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(c: component);
887
888 regcache_cache_only(map: rt1305->regmap, enable: true);
889 regcache_mark_dirty(map: rt1305->regmap);
890
891 return 0;
892}
893
894static int rt1305_resume(struct snd_soc_component *component)
895{
896 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(c: component);
897
898 regcache_cache_only(map: rt1305->regmap, enable: false);
899 regcache_sync(map: rt1305->regmap);
900
901 return 0;
902}
903#else
904#define rt1305_suspend NULL
905#define rt1305_resume NULL
906#endif
907
908#define RT1305_STEREO_RATES SNDRV_PCM_RATE_8000_192000
909#define RT1305_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
910 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \
911 SNDRV_PCM_FMTBIT_S24_LE)
912
913static const struct snd_soc_dai_ops rt1305_aif_dai_ops = {
914 .hw_params = rt1305_hw_params,
915 .set_fmt = rt1305_set_dai_fmt,
916};
917
918static struct snd_soc_dai_driver rt1305_dai[] = {
919 {
920 .name = "rt1305-aif",
921 .playback = {
922 .stream_name = "AIF1 Playback",
923 .channels_min = 1,
924 .channels_max = 2,
925 .rates = RT1305_STEREO_RATES,
926 .formats = RT1305_FORMATS,
927 },
928 .ops = &rt1305_aif_dai_ops,
929 },
930};
931
932static const struct snd_soc_component_driver soc_component_dev_rt1305 = {
933 .probe = rt1305_probe,
934 .remove = rt1305_remove,
935 .suspend = rt1305_suspend,
936 .resume = rt1305_resume,
937 .controls = rt1305_snd_controls,
938 .num_controls = ARRAY_SIZE(rt1305_snd_controls),
939 .dapm_widgets = rt1305_dapm_widgets,
940 .num_dapm_widgets = ARRAY_SIZE(rt1305_dapm_widgets),
941 .dapm_routes = rt1305_dapm_routes,
942 .num_dapm_routes = ARRAY_SIZE(rt1305_dapm_routes),
943 .set_sysclk = rt1305_set_component_sysclk,
944 .set_pll = rt1305_set_component_pll,
945 .use_pmdown_time = 1,
946 .endianness = 1,
947};
948
949static const struct regmap_config rt1305_regmap = {
950 .reg_bits = 8,
951 .val_bits = 16,
952 .max_register = RT1305_MAX_REG + 1 + (ARRAY_SIZE(rt1305_ranges) *
953 RT1305_PR_SPACING),
954 .volatile_reg = rt1305_volatile_register,
955 .readable_reg = rt1305_readable_register,
956 .cache_type = REGCACHE_MAPLE,
957 .reg_defaults = rt1305_reg,
958 .num_reg_defaults = ARRAY_SIZE(rt1305_reg),
959 .ranges = rt1305_ranges,
960 .num_ranges = ARRAY_SIZE(rt1305_ranges),
961 .use_single_read = true,
962 .use_single_write = true,
963};
964
965#if defined(CONFIG_OF)
966static const struct of_device_id rt1305_of_match[] = {
967 { .compatible = "realtek,rt1305", },
968 { .compatible = "realtek,rt1306", },
969 { }
970};
971MODULE_DEVICE_TABLE(of, rt1305_of_match);
972#endif
973
974#ifdef CONFIG_ACPI
975static const struct acpi_device_id rt1305_acpi_match[] = {
976 { "10EC1305" },
977 { "10EC1306" },
978 { }
979};
980MODULE_DEVICE_TABLE(acpi, rt1305_acpi_match);
981#endif
982
983static const struct i2c_device_id rt1305_i2c_id[] = {
984 { "rt1305" },
985 { "rt1306" },
986 { }
987};
988MODULE_DEVICE_TABLE(i2c, rt1305_i2c_id);
989
990static void rt1305_calibrate(struct rt1305_priv *rt1305)
991{
992 unsigned int valmsb, vallsb, offsetl, offsetr;
993 unsigned int rh, rl, rhl, r0ohm;
994 u64 r0l, r0r;
995
996 regcache_cache_bypass(map: rt1305->regmap, enable: true);
997
998 rt1305_reset(regmap: rt1305->regmap);
999 regmap_write(map: rt1305->regmap, RT1305_ADC_SET_3, val: 0x0219);
1000 regmap_write(map: rt1305->regmap, RT1305_PR_BASE + 0xcf, val: 0x5548);
1001 regmap_write(map: rt1305->regmap, RT1305_PR_BASE + 0xc1, val: 0x0320);
1002 regmap_write(map: rt1305->regmap, RT1305_CLOCK_DETECT, val: 0x1000);
1003 regmap_write(map: rt1305->regmap, RT1305_CLK_1, val: 0x0600);
1004 regmap_write(map: rt1305->regmap, RT1305_POWER_CTRL_3, val: 0xffd0);
1005 regmap_write(map: rt1305->regmap, RT1305_EFUSE_1, val: 0x0080);
1006 regmap_write(map: rt1305->regmap, RT1305_EFUSE_1, val: 0x0880);
1007 regmap_write(map: rt1305->regmap, RT1305_POWER_CTRL_1, val: 0x0dfe);
1008
1009 /* Sin Gen */
1010 regmap_write(map: rt1305->regmap, RT1305_PR_BASE + 0x5d, val: 0x0442);
1011
1012 regmap_write(map: rt1305->regmap, RT1305_CAL_EFUSE_CLOCK, val: 0xb000);
1013 regmap_write(map: rt1305->regmap, RT1305_PR_BASE + 0xc3, val: 0xd4a0);
1014 regmap_write(map: rt1305->regmap, RT1305_PR_BASE + 0xcc, val: 0x00cc);
1015 regmap_write(map: rt1305->regmap, RT1305_PR_BASE + 0xc1, val: 0x0320);
1016 regmap_write(map: rt1305->regmap, RT1305_POWER_STATUS, val: 0x0000);
1017 regmap_write(map: rt1305->regmap, RT1305_POWER_CTRL_2, val: 0xffff);
1018 regmap_write(map: rt1305->regmap, RT1305_POWER_CTRL_3, val: 0xfc20);
1019 regmap_write(map: rt1305->regmap, RT1305_PR_BASE + 0x06, val: 0x00c0);
1020 regmap_write(map: rt1305->regmap, RT1305_POWER_CTRL_3, val: 0xfca0);
1021 regmap_write(map: rt1305->regmap, RT1305_POWER_CTRL_3, val: 0xfce0);
1022 regmap_write(map: rt1305->regmap, RT1305_POWER_CTRL_3, val: 0xfcf0);
1023
1024 /* EFUSE read */
1025 regmap_write(map: rt1305->regmap, RT1305_EFUSE_1, val: 0x0080);
1026 regmap_write(map: rt1305->regmap, RT1305_EFUSE_1, val: 0x0880);
1027 regmap_write(map: rt1305->regmap, RT1305_EFUSE_1, val: 0x0880);
1028 regmap_write(map: rt1305->regmap, RT1305_POWER_CTRL_3, val: 0xfce0);
1029 regmap_write(map: rt1305->regmap, RT1305_POWER_CTRL_3, val: 0xfca0);
1030 regmap_write(map: rt1305->regmap, RT1305_POWER_CTRL_3, val: 0xfc20);
1031 regmap_write(map: rt1305->regmap, RT1305_PR_BASE + 0x06, val: 0x0000);
1032 regmap_write(map: rt1305->regmap, RT1305_EFUSE_1, val: 0x0000);
1033
1034 regmap_read(map: rt1305->regmap, RT1305_DAC_OFFSET_5, val: &valmsb);
1035 regmap_read(map: rt1305->regmap, RT1305_DAC_OFFSET_6, val: &vallsb);
1036 offsetl = valmsb << 16 | vallsb;
1037 regmap_read(map: rt1305->regmap, RT1305_DAC_OFFSET_7, val: &valmsb);
1038 regmap_read(map: rt1305->regmap, RT1305_DAC_OFFSET_8, val: &vallsb);
1039 offsetr = valmsb << 16 | vallsb;
1040 pr_info("DC offsetl=0x%x, offsetr=0x%x\n", offsetl, offsetr);
1041
1042 /* R0 calibration */
1043 regmap_write(map: rt1305->regmap, RT1305_PR_BASE + 0x5d, val: 0x9542);
1044 regmap_write(map: rt1305->regmap, RT1305_POWER_CTRL_3, val: 0xfcf0);
1045 regmap_write(map: rt1305->regmap, RT1305_POWER_CTRL_2, val: 0xffff);
1046 regmap_write(map: rt1305->regmap, RT1305_POWER_CTRL_1, val: 0x1dfe);
1047 regmap_write(map: rt1305->regmap, RT1305_SILENCE_DETECT, val: 0x0e13);
1048 regmap_write(map: rt1305->regmap, RT1305_CLK_1, val: 0x0650);
1049
1050 regmap_write(map: rt1305->regmap, RT1305_PR_BASE + 0x50, val: 0x0064);
1051 regmap_write(map: rt1305->regmap, RT1305_PR_BASE + 0x51, val: 0x0770);
1052 regmap_write(map: rt1305->regmap, RT1305_PR_BASE + 0x52, val: 0xc30c);
1053 regmap_write(map: rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, val: 0x8200);
1054 regmap_write(map: rt1305->regmap, RT1305_PR_BASE + 0xd4, val: 0xfb00);
1055 regmap_write(map: rt1305->regmap, RT1305_PR_BASE + 0xd4, val: 0xff80);
1056 msleep(msecs: 2000);
1057 regmap_read(map: rt1305->regmap, RT1305_PR_BASE + 0x55, val: &rh);
1058 regmap_read(map: rt1305->regmap, RT1305_PR_BASE + 0x56, val: &rl);
1059 rhl = (rh << 16) | rl;
1060 r0ohm = (rhl*10) / 33554432;
1061
1062 pr_debug("Left_rhl = 0x%x rh=0x%x rl=0x%x\n", rhl, rh, rl);
1063 pr_info("Left channel %d.%dohm\n", (r0ohm/10), (r0ohm%10));
1064
1065 r0l = 562949953421312ULL;
1066 if (rhl != 0)
1067 do_div(r0l, rhl);
1068 pr_debug("Left_r0 = 0x%llx\n", r0l);
1069
1070 regmap_write(map: rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, val: 0x9200);
1071 regmap_write(map: rt1305->regmap, RT1305_PR_BASE + 0xd4, val: 0xfb00);
1072 regmap_write(map: rt1305->regmap, RT1305_PR_BASE + 0xd4, val: 0xff80);
1073 msleep(msecs: 2000);
1074 regmap_read(map: rt1305->regmap, RT1305_PR_BASE + 0x55, val: &rh);
1075 regmap_read(map: rt1305->regmap, RT1305_PR_BASE + 0x56, val: &rl);
1076 rhl = (rh << 16) | rl;
1077 r0ohm = (rhl*10) / 33554432;
1078
1079 pr_debug("Right_rhl = 0x%x rh=0x%x rl=0x%x\n", rhl, rh, rl);
1080 pr_info("Right channel %d.%dohm\n", (r0ohm/10), (r0ohm%10));
1081
1082 r0r = 562949953421312ULL;
1083 if (rhl != 0)
1084 do_div(r0r, rhl);
1085 pr_debug("Right_r0 = 0x%llx\n", r0r);
1086
1087 regmap_write(map: rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, val: 0xc2ec);
1088
1089 if ((r0l > R0_UPPER) && (r0l < R0_LOWER) &&
1090 (r0r > R0_UPPER) && (r0r < R0_LOWER)) {
1091 regmap_write(map: rt1305->regmap, RT1305_PR_BASE + 0x4e,
1092 val: (r0l >> 16) & 0xffff);
1093 regmap_write(map: rt1305->regmap, RT1305_PR_BASE + 0x4f,
1094 val: r0l & 0xffff);
1095 regmap_write(map: rt1305->regmap, RT1305_PR_BASE + 0xfe,
1096 val: ((r0r >> 16) & 0xffff) | 0xf800);
1097 regmap_write(map: rt1305->regmap, RT1305_PR_BASE + 0xfd,
1098 val: r0r & 0xffff);
1099 } else {
1100 pr_err("R0 calibration failed\n");
1101 }
1102
1103 /* restore some registers */
1104 regmap_write(map: rt1305->regmap, RT1305_POWER_CTRL_1, val: 0x0dfe);
1105 usleep_range(min: 200000, max: 400000);
1106 regmap_write(map: rt1305->regmap, RT1305_PR_BASE + 0x5d, val: 0x0442);
1107 regmap_write(map: rt1305->regmap, RT1305_CLOCK_DETECT, val: 0x3000);
1108 regmap_write(map: rt1305->regmap, RT1305_CLK_1, val: 0x0400);
1109 regmap_write(map: rt1305->regmap, RT1305_POWER_CTRL_1, val: 0x0000);
1110 regmap_write(map: rt1305->regmap, RT1305_CAL_EFUSE_CLOCK, val: 0x8000);
1111 regmap_write(map: rt1305->regmap, RT1305_POWER_CTRL_2, val: 0x1020);
1112 regmap_write(map: rt1305->regmap, RT1305_POWER_CTRL_3, val: 0x0000);
1113
1114 regcache_cache_bypass(map: rt1305->regmap, enable: false);
1115}
1116
1117static int rt1305_i2c_probe(struct i2c_client *i2c)
1118{
1119 struct rt1305_priv *rt1305;
1120 int ret;
1121 unsigned int val;
1122
1123 rt1305 = devm_kzalloc(dev: &i2c->dev, size: sizeof(struct rt1305_priv),
1124 GFP_KERNEL);
1125 if (rt1305 == NULL)
1126 return -ENOMEM;
1127
1128 i2c_set_clientdata(client: i2c, data: rt1305);
1129
1130 rt1305->regmap = devm_regmap_init_i2c(i2c, &rt1305_regmap);
1131 if (IS_ERR(ptr: rt1305->regmap)) {
1132 ret = PTR_ERR(ptr: rt1305->regmap);
1133 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1134 ret);
1135 return ret;
1136 }
1137
1138 regmap_read(map: rt1305->regmap, RT1305_DEVICE_ID, val: &val);
1139 if (val != RT1305_DEVICE_ID_NUM) {
1140 dev_err(&i2c->dev,
1141 "Device with ID register %x is not rt1305\n", val);
1142 return -ENODEV;
1143 }
1144
1145 rt1305_reset(regmap: rt1305->regmap);
1146 rt1305_calibrate(rt1305);
1147
1148 return devm_snd_soc_register_component(dev: &i2c->dev,
1149 component_driver: &soc_component_dev_rt1305,
1150 dai_drv: rt1305_dai, ARRAY_SIZE(rt1305_dai));
1151}
1152
1153static void rt1305_i2c_shutdown(struct i2c_client *client)
1154{
1155 struct rt1305_priv *rt1305 = i2c_get_clientdata(client);
1156
1157 rt1305_reset(regmap: rt1305->regmap);
1158}
1159
1160
1161static struct i2c_driver rt1305_i2c_driver = {
1162 .driver = {
1163 .name = "rt1305",
1164#if defined(CONFIG_OF)
1165 .of_match_table = rt1305_of_match,
1166#endif
1167#if defined(CONFIG_ACPI)
1168 .acpi_match_table = ACPI_PTR(rt1305_acpi_match)
1169#endif
1170 },
1171 .probe = rt1305_i2c_probe,
1172 .shutdown = rt1305_i2c_shutdown,
1173 .id_table = rt1305_i2c_id,
1174};
1175module_i2c_driver(rt1305_i2c_driver);
1176
1177MODULE_DESCRIPTION("ASoC RT1305 amplifier driver");
1178MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>");
1179MODULE_LICENSE("GPL v2");
1180

source code of linux/sound/soc/codecs/rt1305.c