1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * wm8400.c -- WM8400 ALSA Soc Audio driver
4 *
5 * Copyright 2008-11 Wolfson Microelectronics PLC.
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 */
8
9#include <linux/module.h>
10#include <linux/moduleparam.h>
11#include <linux/kernel.h>
12#include <linux/slab.h>
13#include <linux/init.h>
14#include <linux/delay.h>
15#include <linux/pm.h>
16#include <linux/platform_device.h>
17#include <linux/regulator/consumer.h>
18#include <linux/mfd/wm8400-audio.h>
19#include <linux/mfd/wm8400-private.h>
20#include <linux/mfd/core.h>
21#include <sound/core.h>
22#include <sound/pcm.h>
23#include <sound/pcm_params.h>
24#include <sound/soc.h>
25#include <sound/initval.h>
26#include <sound/tlv.h>
27
28#include "wm8400.h"
29
30static struct regulator_bulk_data power[] = {
31 {
32 .supply = "I2S1VDD",
33 },
34 {
35 .supply = "I2S2VDD",
36 },
37 {
38 .supply = "DCVDD",
39 },
40 {
41 .supply = "AVDD",
42 },
43 {
44 .supply = "FLLVDD",
45 },
46 {
47 .supply = "HPVDD",
48 },
49 {
50 .supply = "SPKVDD",
51 },
52};
53
54/* codec private data */
55struct wm8400_priv {
56 struct wm8400 *wm8400;
57 u16 fake_register;
58 unsigned int sysclk;
59 unsigned int pcmclk;
60 int fll_in, fll_out;
61};
62
63static void wm8400_component_reset(struct snd_soc_component *component)
64{
65 struct wm8400_priv *wm8400 = snd_soc_component_get_drvdata(c: component);
66
67 wm8400_reset_codec_reg_cache(wm8400: wm8400->wm8400);
68}
69
70static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1650, 3000, 0);
71
72static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -2100, 0, 0);
73
74static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -7300, 600, 0);
75
76static const DECLARE_TLV_DB_SCALE(out_dac_tlv, -7163, 0, 0);
77
78static const DECLARE_TLV_DB_SCALE(in_adc_tlv, -7163, 1763, 0);
79
80static const DECLARE_TLV_DB_SCALE(out_sidetone_tlv, -3600, 0, 0);
81
82static int wm8400_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol,
83 struct snd_ctl_elem_value *ucontrol)
84{
85 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
86 struct soc_mixer_control *mc =
87 (struct soc_mixer_control *)kcontrol->private_value;
88 int reg = mc->reg;
89 int ret;
90 u16 val;
91
92 ret = snd_soc_put_volsw(kcontrol, ucontrol);
93 if (ret < 0)
94 return ret;
95
96 /* now hit the volume update bits (always bit 8) */
97 val = snd_soc_component_read(component, reg);
98 return snd_soc_component_write(component, reg, val: val | 0x0100);
99}
100
101#define WM8400_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert, tlv_array) \
102 SOC_SINGLE_EXT_TLV(xname, reg, shift, max, invert, \
103 snd_soc_get_volsw, wm8400_outpga_put_volsw_vu, tlv_array)
104
105
106static const char *wm8400_digital_sidetone[] =
107 {"None", "Left ADC", "Right ADC", "Reserved"};
108
109static SOC_ENUM_SINGLE_DECL(wm8400_left_digital_sidetone_enum,
110 WM8400_DIGITAL_SIDE_TONE,
111 WM8400_ADC_TO_DACL_SHIFT,
112 wm8400_digital_sidetone);
113
114static SOC_ENUM_SINGLE_DECL(wm8400_right_digital_sidetone_enum,
115 WM8400_DIGITAL_SIDE_TONE,
116 WM8400_ADC_TO_DACR_SHIFT,
117 wm8400_digital_sidetone);
118
119static const char *wm8400_adcmode[] =
120 {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"};
121
122static SOC_ENUM_SINGLE_DECL(wm8400_right_adcmode_enum,
123 WM8400_ADC_CTRL,
124 WM8400_ADC_HPF_CUT_SHIFT,
125 wm8400_adcmode);
126
127static const struct snd_kcontrol_new wm8400_snd_controls[] = {
128/* INMIXL */
129SOC_SINGLE("LIN12 PGA Boost", WM8400_INPUT_MIXER3, WM8400_L12MNBST_SHIFT,
130 1, 0),
131SOC_SINGLE("LIN34 PGA Boost", WM8400_INPUT_MIXER3, WM8400_L34MNBST_SHIFT,
132 1, 0),
133/* INMIXR */
134SOC_SINGLE("RIN12 PGA Boost", WM8400_INPUT_MIXER3, WM8400_R12MNBST_SHIFT,
135 1, 0),
136SOC_SINGLE("RIN34 PGA Boost", WM8400_INPUT_MIXER3, WM8400_R34MNBST_SHIFT,
137 1, 0),
138
139/* LOMIX */
140SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8400_OUTPUT_MIXER3,
141 WM8400_LLI3LOVOL_SHIFT, 7, 0, out_mix_tlv),
142SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER3,
143 WM8400_LR12LOVOL_SHIFT, 7, 0, out_mix_tlv),
144SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER3,
145 WM8400_LL12LOVOL_SHIFT, 7, 0, out_mix_tlv),
146SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8400_OUTPUT_MIXER5,
147 WM8400_LRI3LOVOL_SHIFT, 7, 0, out_mix_tlv),
148SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8400_OUTPUT_MIXER5,
149 WM8400_LRBLOVOL_SHIFT, 7, 0, out_mix_tlv),
150SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8400_OUTPUT_MIXER5,
151 WM8400_LRBLOVOL_SHIFT, 7, 0, out_mix_tlv),
152
153/* ROMIX */
154SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8400_OUTPUT_MIXER4,
155 WM8400_RRI3ROVOL_SHIFT, 7, 0, out_mix_tlv),
156SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER4,
157 WM8400_RL12ROVOL_SHIFT, 7, 0, out_mix_tlv),
158SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER4,
159 WM8400_RR12ROVOL_SHIFT, 7, 0, out_mix_tlv),
160SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8400_OUTPUT_MIXER6,
161 WM8400_RLI3ROVOL_SHIFT, 7, 0, out_mix_tlv),
162SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8400_OUTPUT_MIXER6,
163 WM8400_RLBROVOL_SHIFT, 7, 0, out_mix_tlv),
164SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8400_OUTPUT_MIXER6,
165 WM8400_RRBROVOL_SHIFT, 7, 0, out_mix_tlv),
166
167/* LOUT */
168WM8400_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8400_LEFT_OUTPUT_VOLUME,
169 WM8400_LOUTVOL_SHIFT, WM8400_LOUTVOL_MASK, 0, out_pga_tlv),
170SOC_SINGLE("LOUT ZC", WM8400_LEFT_OUTPUT_VOLUME, WM8400_LOZC_SHIFT, 1, 0),
171
172/* ROUT */
173WM8400_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8400_RIGHT_OUTPUT_VOLUME,
174 WM8400_ROUTVOL_SHIFT, WM8400_ROUTVOL_MASK, 0, out_pga_tlv),
175SOC_SINGLE("ROUT ZC", WM8400_RIGHT_OUTPUT_VOLUME, WM8400_ROZC_SHIFT, 1, 0),
176
177/* LOPGA */
178WM8400_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8400_LEFT_OPGA_VOLUME,
179 WM8400_LOPGAVOL_SHIFT, WM8400_LOPGAVOL_MASK, 0, out_pga_tlv),
180SOC_SINGLE("LOPGA ZC Switch", WM8400_LEFT_OPGA_VOLUME,
181 WM8400_LOPGAZC_SHIFT, 1, 0),
182
183/* ROPGA */
184WM8400_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8400_RIGHT_OPGA_VOLUME,
185 WM8400_ROPGAVOL_SHIFT, WM8400_ROPGAVOL_MASK, 0, out_pga_tlv),
186SOC_SINGLE("ROPGA ZC Switch", WM8400_RIGHT_OPGA_VOLUME,
187 WM8400_ROPGAZC_SHIFT, 1, 0),
188
189SOC_SINGLE("LON Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
190 WM8400_LONMUTE_SHIFT, 1, 0),
191SOC_SINGLE("LOP Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
192 WM8400_LOPMUTE_SHIFT, 1, 0),
193SOC_SINGLE("LOP Attenuation Switch", WM8400_LINE_OUTPUTS_VOLUME,
194 WM8400_LOATTN_SHIFT, 1, 0),
195SOC_SINGLE("RON Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
196 WM8400_RONMUTE_SHIFT, 1, 0),
197SOC_SINGLE("ROP Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
198 WM8400_ROPMUTE_SHIFT, 1, 0),
199SOC_SINGLE("ROP Attenuation Switch", WM8400_LINE_OUTPUTS_VOLUME,
200 WM8400_ROATTN_SHIFT, 1, 0),
201
202SOC_SINGLE("OUT3 Mute Switch", WM8400_OUT3_4_VOLUME,
203 WM8400_OUT3MUTE_SHIFT, 1, 0),
204SOC_SINGLE("OUT3 Attenuation Switch", WM8400_OUT3_4_VOLUME,
205 WM8400_OUT3ATTN_SHIFT, 1, 0),
206
207SOC_SINGLE("OUT4 Mute Switch", WM8400_OUT3_4_VOLUME,
208 WM8400_OUT4MUTE_SHIFT, 1, 0),
209SOC_SINGLE("OUT4 Attenuation Switch", WM8400_OUT3_4_VOLUME,
210 WM8400_OUT4ATTN_SHIFT, 1, 0),
211
212SOC_SINGLE("Speaker Mode Switch", WM8400_CLASSD1,
213 WM8400_CDMODE_SHIFT, 1, 0),
214
215SOC_SINGLE("Speaker Output Attenuation Volume", WM8400_SPEAKER_VOLUME,
216 WM8400_SPKATTN_SHIFT, WM8400_SPKATTN_MASK, 0),
217SOC_SINGLE("Speaker DC Boost Volume", WM8400_CLASSD3,
218 WM8400_DCGAIN_SHIFT, 6, 0),
219SOC_SINGLE("Speaker AC Boost Volume", WM8400_CLASSD3,
220 WM8400_ACGAIN_SHIFT, 6, 0),
221
222WM8400_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume",
223 WM8400_LEFT_DAC_DIGITAL_VOLUME, WM8400_DACL_VOL_SHIFT,
224 127, 0, out_dac_tlv),
225
226WM8400_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume",
227 WM8400_RIGHT_DAC_DIGITAL_VOLUME, WM8400_DACR_VOL_SHIFT,
228 127, 0, out_dac_tlv),
229
230SOC_ENUM("Left Digital Sidetone", wm8400_left_digital_sidetone_enum),
231SOC_ENUM("Right Digital Sidetone", wm8400_right_digital_sidetone_enum),
232
233SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8400_DIGITAL_SIDE_TONE,
234 WM8400_ADCL_DAC_SVOL_SHIFT, 15, 0, out_sidetone_tlv),
235SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8400_DIGITAL_SIDE_TONE,
236 WM8400_ADCR_DAC_SVOL_SHIFT, 15, 0, out_sidetone_tlv),
237
238SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8400_ADC_CTRL,
239 WM8400_ADC_HPF_ENA_SHIFT, 1, 0),
240
241SOC_ENUM("ADC HPF Mode", wm8400_right_adcmode_enum),
242
243WM8400_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume",
244 WM8400_LEFT_ADC_DIGITAL_VOLUME,
245 WM8400_ADCL_VOL_SHIFT,
246 WM8400_ADCL_VOL_MASK,
247 0,
248 in_adc_tlv),
249
250WM8400_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume",
251 WM8400_RIGHT_ADC_DIGITAL_VOLUME,
252 WM8400_ADCR_VOL_SHIFT,
253 WM8400_ADCR_VOL_MASK,
254 0,
255 in_adc_tlv),
256
257WM8400_OUTPGA_SINGLE_R_TLV("LIN12 Volume",
258 WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
259 WM8400_LIN12VOL_SHIFT,
260 WM8400_LIN12VOL_MASK,
261 0,
262 in_pga_tlv),
263
264SOC_SINGLE("LIN12 ZC Switch", WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
265 WM8400_LI12ZC_SHIFT, 1, 0),
266
267SOC_SINGLE("LIN12 Mute Switch", WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
268 WM8400_LI12MUTE_SHIFT, 1, 0),
269
270WM8400_OUTPGA_SINGLE_R_TLV("LIN34 Volume",
271 WM8400_LEFT_LINE_INPUT_3_4_VOLUME,
272 WM8400_LIN34VOL_SHIFT,
273 WM8400_LIN34VOL_MASK,
274 0,
275 in_pga_tlv),
276
277SOC_SINGLE("LIN34 ZC Switch", WM8400_LEFT_LINE_INPUT_3_4_VOLUME,
278 WM8400_LI34ZC_SHIFT, 1, 0),
279
280SOC_SINGLE("LIN34 Mute Switch", WM8400_LEFT_LINE_INPUT_3_4_VOLUME,
281 WM8400_LI34MUTE_SHIFT, 1, 0),
282
283WM8400_OUTPGA_SINGLE_R_TLV("RIN12 Volume",
284 WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
285 WM8400_RIN12VOL_SHIFT,
286 WM8400_RIN12VOL_MASK,
287 0,
288 in_pga_tlv),
289
290SOC_SINGLE("RIN12 ZC Switch", WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
291 WM8400_RI12ZC_SHIFT, 1, 0),
292
293SOC_SINGLE("RIN12 Mute Switch", WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
294 WM8400_RI12MUTE_SHIFT, 1, 0),
295
296WM8400_OUTPGA_SINGLE_R_TLV("RIN34 Volume",
297 WM8400_RIGHT_LINE_INPUT_3_4_VOLUME,
298 WM8400_RIN34VOL_SHIFT,
299 WM8400_RIN34VOL_MASK,
300 0,
301 in_pga_tlv),
302
303SOC_SINGLE("RIN34 ZC Switch", WM8400_RIGHT_LINE_INPUT_3_4_VOLUME,
304 WM8400_RI34ZC_SHIFT, 1, 0),
305
306SOC_SINGLE("RIN34 Mute Switch", WM8400_RIGHT_LINE_INPUT_3_4_VOLUME,
307 WM8400_RI34MUTE_SHIFT, 1, 0),
308
309};
310
311/*
312 * _DAPM_ Controls
313 */
314
315static int outmixer_event (struct snd_soc_dapm_widget *w,
316 struct snd_kcontrol * kcontrol, int event)
317{
318 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm);
319 struct soc_mixer_control *mc =
320 (struct soc_mixer_control *)kcontrol->private_value;
321 struct wm8400_priv *wm8400 = snd_soc_component_get_drvdata(c: component);
322 u32 reg_shift = mc->shift;
323 int ret = 0;
324 u16 reg;
325
326 switch (reg_shift) {
327 case WM8400_SPEAKER_MIXER | (WM8400_LDSPK << 8) :
328 reg = snd_soc_component_read(component, WM8400_OUTPUT_MIXER1);
329 if (reg & WM8400_LDLO) {
330 dev_warn(wm8400->wm8400->dev,
331 "Cannot set as Output Mixer 1 LDLO Set\n");
332 ret = -1;
333 }
334 break;
335 case WM8400_SPEAKER_MIXER | (WM8400_RDSPK << 8):
336 reg = snd_soc_component_read(component, WM8400_OUTPUT_MIXER2);
337 if (reg & WM8400_RDRO) {
338 dev_warn(wm8400->wm8400->dev,
339 "Cannot set as Output Mixer 2 RDRO Set\n");
340 ret = -1;
341 }
342 break;
343 case WM8400_OUTPUT_MIXER1 | (WM8400_LDLO << 8):
344 reg = snd_soc_component_read(component, WM8400_SPEAKER_MIXER);
345 if (reg & WM8400_LDSPK) {
346 dev_warn(wm8400->wm8400->dev,
347 "Cannot set as Speaker Mixer LDSPK Set\n");
348 ret = -1;
349 }
350 break;
351 case WM8400_OUTPUT_MIXER2 | (WM8400_RDRO << 8):
352 reg = snd_soc_component_read(component, WM8400_SPEAKER_MIXER);
353 if (reg & WM8400_RDSPK) {
354 dev_warn(wm8400->wm8400->dev,
355 "Cannot set as Speaker Mixer RDSPK Set\n");
356 ret = -1;
357 }
358 break;
359 }
360
361 return ret;
362}
363
364/* INMIX dB values */
365static const DECLARE_TLV_DB_SCALE(in_mix_tlv, -1200, 600, 0);
366
367/* Left In PGA Connections */
368static const struct snd_kcontrol_new wm8400_dapm_lin12_pga_controls[] = {
369SOC_DAPM_SINGLE("LIN1 Switch", WM8400_INPUT_MIXER2, WM8400_LMN1_SHIFT, 1, 0),
370SOC_DAPM_SINGLE("LIN2 Switch", WM8400_INPUT_MIXER2, WM8400_LMP2_SHIFT, 1, 0),
371};
372
373static const struct snd_kcontrol_new wm8400_dapm_lin34_pga_controls[] = {
374SOC_DAPM_SINGLE("LIN3 Switch", WM8400_INPUT_MIXER2, WM8400_LMN3_SHIFT, 1, 0),
375SOC_DAPM_SINGLE("LIN4 Switch", WM8400_INPUT_MIXER2, WM8400_LMP4_SHIFT, 1, 0),
376};
377
378/* Right In PGA Connections */
379static const struct snd_kcontrol_new wm8400_dapm_rin12_pga_controls[] = {
380SOC_DAPM_SINGLE("RIN1 Switch", WM8400_INPUT_MIXER2, WM8400_RMN1_SHIFT, 1, 0),
381SOC_DAPM_SINGLE("RIN2 Switch", WM8400_INPUT_MIXER2, WM8400_RMP2_SHIFT, 1, 0),
382};
383
384static const struct snd_kcontrol_new wm8400_dapm_rin34_pga_controls[] = {
385SOC_DAPM_SINGLE("RIN3 Switch", WM8400_INPUT_MIXER2, WM8400_RMN3_SHIFT, 1, 0),
386SOC_DAPM_SINGLE("RIN4 Switch", WM8400_INPUT_MIXER2, WM8400_RMP4_SHIFT, 1, 0),
387};
388
389/* INMIXL */
390static const struct snd_kcontrol_new wm8400_dapm_inmixl_controls[] = {
391SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8400_INPUT_MIXER3,
392 WM8400_LDBVOL_SHIFT, WM8400_LDBVOL_MASK, 0, in_mix_tlv),
393SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8400_INPUT_MIXER5, WM8400_LI2BVOL_SHIFT,
394 7, 0, in_mix_tlv),
395SOC_DAPM_SINGLE("LINPGA12 Switch", WM8400_INPUT_MIXER3, WM8400_L12MNB_SHIFT,
396 1, 0),
397SOC_DAPM_SINGLE("LINPGA34 Switch", WM8400_INPUT_MIXER3, WM8400_L34MNB_SHIFT,
398 1, 0),
399};
400
401/* INMIXR */
402static const struct snd_kcontrol_new wm8400_dapm_inmixr_controls[] = {
403SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8400_INPUT_MIXER4,
404 WM8400_RDBVOL_SHIFT, WM8400_RDBVOL_MASK, 0, in_mix_tlv),
405SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8400_INPUT_MIXER6, WM8400_RI2BVOL_SHIFT,
406 7, 0, in_mix_tlv),
407SOC_DAPM_SINGLE("RINPGA12 Switch", WM8400_INPUT_MIXER3, WM8400_L12MNB_SHIFT,
408 1, 0),
409SOC_DAPM_SINGLE("RINPGA34 Switch", WM8400_INPUT_MIXER3, WM8400_L34MNB_SHIFT,
410 1, 0),
411};
412
413/* AINLMUX */
414static const char *wm8400_ainlmux[] =
415 {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"};
416
417static SOC_ENUM_SINGLE_DECL(wm8400_ainlmux_enum,
418 WM8400_INPUT_MIXER1,
419 WM8400_AINLMODE_SHIFT,
420 wm8400_ainlmux);
421
422static const struct snd_kcontrol_new wm8400_dapm_ainlmux_controls =
423SOC_DAPM_ENUM("Route", wm8400_ainlmux_enum);
424
425/* DIFFINL */
426
427/* AINRMUX */
428static const char *wm8400_ainrmux[] =
429 {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"};
430
431static SOC_ENUM_SINGLE_DECL(wm8400_ainrmux_enum,
432 WM8400_INPUT_MIXER1,
433 WM8400_AINRMODE_SHIFT,
434 wm8400_ainrmux);
435
436static const struct snd_kcontrol_new wm8400_dapm_ainrmux_controls =
437SOC_DAPM_ENUM("Route", wm8400_ainrmux_enum);
438
439/* LOMIX */
440static const struct snd_kcontrol_new wm8400_dapm_lomix_controls[] = {
441SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8400_OUTPUT_MIXER1,
442 WM8400_LRBLO_SHIFT, 1, 0),
443SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8400_OUTPUT_MIXER1,
444 WM8400_LLBLO_SHIFT, 1, 0),
445SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8400_OUTPUT_MIXER1,
446 WM8400_LRI3LO_SHIFT, 1, 0),
447SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8400_OUTPUT_MIXER1,
448 WM8400_LLI3LO_SHIFT, 1, 0),
449SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER1,
450 WM8400_LR12LO_SHIFT, 1, 0),
451SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER1,
452 WM8400_LL12LO_SHIFT, 1, 0),
453SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8400_OUTPUT_MIXER1,
454 WM8400_LDLO_SHIFT, 1, 0),
455};
456
457/* ROMIX */
458static const struct snd_kcontrol_new wm8400_dapm_romix_controls[] = {
459SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8400_OUTPUT_MIXER2,
460 WM8400_RLBRO_SHIFT, 1, 0),
461SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8400_OUTPUT_MIXER2,
462 WM8400_RRBRO_SHIFT, 1, 0),
463SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8400_OUTPUT_MIXER2,
464 WM8400_RLI3RO_SHIFT, 1, 0),
465SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8400_OUTPUT_MIXER2,
466 WM8400_RRI3RO_SHIFT, 1, 0),
467SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER2,
468 WM8400_RL12RO_SHIFT, 1, 0),
469SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER2,
470 WM8400_RR12RO_SHIFT, 1, 0),
471SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8400_OUTPUT_MIXER2,
472 WM8400_RDRO_SHIFT, 1, 0),
473};
474
475/* LONMIX */
476static const struct snd_kcontrol_new wm8400_dapm_lonmix_controls[] = {
477SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8400_LINE_MIXER1,
478 WM8400_LLOPGALON_SHIFT, 1, 0),
479SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8400_LINE_MIXER1,
480 WM8400_LROPGALON_SHIFT, 1, 0),
481SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8400_LINE_MIXER1,
482 WM8400_LOPLON_SHIFT, 1, 0),
483};
484
485/* LOPMIX */
486static const struct snd_kcontrol_new wm8400_dapm_lopmix_controls[] = {
487SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8400_LINE_MIXER1,
488 WM8400_LR12LOP_SHIFT, 1, 0),
489SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8400_LINE_MIXER1,
490 WM8400_LL12LOP_SHIFT, 1, 0),
491SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8400_LINE_MIXER1,
492 WM8400_LLOPGALOP_SHIFT, 1, 0),
493};
494
495/* RONMIX */
496static const struct snd_kcontrol_new wm8400_dapm_ronmix_controls[] = {
497SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8400_LINE_MIXER2,
498 WM8400_RROPGARON_SHIFT, 1, 0),
499SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8400_LINE_MIXER2,
500 WM8400_RLOPGARON_SHIFT, 1, 0),
501SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8400_LINE_MIXER2,
502 WM8400_ROPRON_SHIFT, 1, 0),
503};
504
505/* ROPMIX */
506static const struct snd_kcontrol_new wm8400_dapm_ropmix_controls[] = {
507SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8400_LINE_MIXER2,
508 WM8400_RL12ROP_SHIFT, 1, 0),
509SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8400_LINE_MIXER2,
510 WM8400_RR12ROP_SHIFT, 1, 0),
511SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8400_LINE_MIXER2,
512 WM8400_RROPGAROP_SHIFT, 1, 0),
513};
514
515/* OUT3MIX */
516static const struct snd_kcontrol_new wm8400_dapm_out3mix_controls[] = {
517SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switch", WM8400_OUT3_4_MIXER,
518 WM8400_LI4O3_SHIFT, 1, 0),
519SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8400_OUT3_4_MIXER,
520 WM8400_LPGAO3_SHIFT, 1, 0),
521};
522
523/* OUT4MIX */
524static const struct snd_kcontrol_new wm8400_dapm_out4mix_controls[] = {
525SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8400_OUT3_4_MIXER,
526 WM8400_RPGAO4_SHIFT, 1, 0),
527SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switch", WM8400_OUT3_4_MIXER,
528 WM8400_RI4O4_SHIFT, 1, 0),
529};
530
531/* SPKMIX */
532static const struct snd_kcontrol_new wm8400_dapm_spkmix_controls[] = {
533SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8400_SPEAKER_MIXER,
534 WM8400_LI2SPK_SHIFT, 1, 0),
535SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8400_SPEAKER_MIXER,
536 WM8400_LB2SPK_SHIFT, 1, 0),
537SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8400_SPEAKER_MIXER,
538 WM8400_LOPGASPK_SHIFT, 1, 0),
539SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8400_SPEAKER_MIXER,
540 WM8400_LDSPK_SHIFT, 1, 0),
541SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8400_SPEAKER_MIXER,
542 WM8400_RDSPK_SHIFT, 1, 0),
543SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8400_SPEAKER_MIXER,
544 WM8400_ROPGASPK_SHIFT, 1, 0),
545SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8400_SPEAKER_MIXER,
546 WM8400_RL12ROP_SHIFT, 1, 0),
547SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8400_SPEAKER_MIXER,
548 WM8400_RI2SPK_SHIFT, 1, 0),
549};
550
551static const struct snd_soc_dapm_widget wm8400_dapm_widgets[] = {
552/* Input Side */
553/* Input Lines */
554SND_SOC_DAPM_INPUT("LIN1"),
555SND_SOC_DAPM_INPUT("LIN2"),
556SND_SOC_DAPM_INPUT("LIN3"),
557SND_SOC_DAPM_INPUT("LIN4/RXN"),
558SND_SOC_DAPM_INPUT("RIN3"),
559SND_SOC_DAPM_INPUT("RIN4/RXP"),
560SND_SOC_DAPM_INPUT("RIN1"),
561SND_SOC_DAPM_INPUT("RIN2"),
562SND_SOC_DAPM_INPUT("Internal ADC Source"),
563
564/* DACs */
565SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8400_POWER_MANAGEMENT_2,
566 WM8400_ADCL_ENA_SHIFT, 0),
567SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8400_POWER_MANAGEMENT_2,
568 WM8400_ADCR_ENA_SHIFT, 0),
569
570/* Input PGAs */
571SND_SOC_DAPM_MIXER("LIN12 PGA", WM8400_POWER_MANAGEMENT_2,
572 WM8400_LIN12_ENA_SHIFT,
573 0, &wm8400_dapm_lin12_pga_controls[0],
574 ARRAY_SIZE(wm8400_dapm_lin12_pga_controls)),
575SND_SOC_DAPM_MIXER("LIN34 PGA", WM8400_POWER_MANAGEMENT_2,
576 WM8400_LIN34_ENA_SHIFT,
577 0, &wm8400_dapm_lin34_pga_controls[0],
578 ARRAY_SIZE(wm8400_dapm_lin34_pga_controls)),
579SND_SOC_DAPM_MIXER("RIN12 PGA", WM8400_POWER_MANAGEMENT_2,
580 WM8400_RIN12_ENA_SHIFT,
581 0, &wm8400_dapm_rin12_pga_controls[0],
582 ARRAY_SIZE(wm8400_dapm_rin12_pga_controls)),
583SND_SOC_DAPM_MIXER("RIN34 PGA", WM8400_POWER_MANAGEMENT_2,
584 WM8400_RIN34_ENA_SHIFT,
585 0, &wm8400_dapm_rin34_pga_controls[0],
586 ARRAY_SIZE(wm8400_dapm_rin34_pga_controls)),
587
588SND_SOC_DAPM_SUPPLY("INL", WM8400_POWER_MANAGEMENT_2, WM8400_AINL_ENA_SHIFT,
589 0, NULL, 0),
590SND_SOC_DAPM_SUPPLY("INR", WM8400_POWER_MANAGEMENT_2, WM8400_AINR_ENA_SHIFT,
591 0, NULL, 0),
592
593/* INMIXL */
594SND_SOC_DAPM_MIXER("INMIXL", SND_SOC_NOPM, 0, 0,
595 &wm8400_dapm_inmixl_controls[0],
596 ARRAY_SIZE(wm8400_dapm_inmixl_controls)),
597
598/* AINLMUX */
599SND_SOC_DAPM_MUX("AILNMUX", SND_SOC_NOPM, 0, 0, &wm8400_dapm_ainlmux_controls),
600
601/* INMIXR */
602SND_SOC_DAPM_MIXER("INMIXR", SND_SOC_NOPM, 0, 0,
603 &wm8400_dapm_inmixr_controls[0],
604 ARRAY_SIZE(wm8400_dapm_inmixr_controls)),
605
606/* AINRMUX */
607SND_SOC_DAPM_MUX("AIRNMUX", SND_SOC_NOPM, 0, 0, &wm8400_dapm_ainrmux_controls),
608
609/* Output Side */
610/* DACs */
611SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8400_POWER_MANAGEMENT_3,
612 WM8400_DACL_ENA_SHIFT, 0),
613SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8400_POWER_MANAGEMENT_3,
614 WM8400_DACR_ENA_SHIFT, 0),
615
616/* LOMIX */
617SND_SOC_DAPM_MIXER_E("LOMIX", WM8400_POWER_MANAGEMENT_3,
618 WM8400_LOMIX_ENA_SHIFT,
619 0, &wm8400_dapm_lomix_controls[0],
620 ARRAY_SIZE(wm8400_dapm_lomix_controls),
621 outmixer_event, SND_SOC_DAPM_PRE_REG),
622
623/* LONMIX */
624SND_SOC_DAPM_MIXER("LONMIX", WM8400_POWER_MANAGEMENT_3, WM8400_LON_ENA_SHIFT,
625 0, &wm8400_dapm_lonmix_controls[0],
626 ARRAY_SIZE(wm8400_dapm_lonmix_controls)),
627
628/* LOPMIX */
629SND_SOC_DAPM_MIXER("LOPMIX", WM8400_POWER_MANAGEMENT_3, WM8400_LOP_ENA_SHIFT,
630 0, &wm8400_dapm_lopmix_controls[0],
631 ARRAY_SIZE(wm8400_dapm_lopmix_controls)),
632
633/* OUT3MIX */
634SND_SOC_DAPM_MIXER("OUT3MIX", WM8400_POWER_MANAGEMENT_1, WM8400_OUT3_ENA_SHIFT,
635 0, &wm8400_dapm_out3mix_controls[0],
636 ARRAY_SIZE(wm8400_dapm_out3mix_controls)),
637
638/* SPKMIX */
639SND_SOC_DAPM_MIXER_E("SPKMIX", WM8400_POWER_MANAGEMENT_1, WM8400_SPK_ENA_SHIFT,
640 0, &wm8400_dapm_spkmix_controls[0],
641 ARRAY_SIZE(wm8400_dapm_spkmix_controls), outmixer_event,
642 SND_SOC_DAPM_PRE_REG),
643
644/* OUT4MIX */
645SND_SOC_DAPM_MIXER("OUT4MIX", WM8400_POWER_MANAGEMENT_1, WM8400_OUT4_ENA_SHIFT,
646 0, &wm8400_dapm_out4mix_controls[0],
647 ARRAY_SIZE(wm8400_dapm_out4mix_controls)),
648
649/* ROPMIX */
650SND_SOC_DAPM_MIXER("ROPMIX", WM8400_POWER_MANAGEMENT_3, WM8400_ROP_ENA_SHIFT,
651 0, &wm8400_dapm_ropmix_controls[0],
652 ARRAY_SIZE(wm8400_dapm_ropmix_controls)),
653
654/* RONMIX */
655SND_SOC_DAPM_MIXER("RONMIX", WM8400_POWER_MANAGEMENT_3, WM8400_RON_ENA_SHIFT,
656 0, &wm8400_dapm_ronmix_controls[0],
657 ARRAY_SIZE(wm8400_dapm_ronmix_controls)),
658
659/* ROMIX */
660SND_SOC_DAPM_MIXER_E("ROMIX", WM8400_POWER_MANAGEMENT_3,
661 WM8400_ROMIX_ENA_SHIFT,
662 0, &wm8400_dapm_romix_controls[0],
663 ARRAY_SIZE(wm8400_dapm_romix_controls),
664 outmixer_event, SND_SOC_DAPM_PRE_REG),
665
666/* LOUT PGA */
667SND_SOC_DAPM_PGA("LOUT PGA", WM8400_POWER_MANAGEMENT_1, WM8400_LOUT_ENA_SHIFT,
668 0, NULL, 0),
669
670/* ROUT PGA */
671SND_SOC_DAPM_PGA("ROUT PGA", WM8400_POWER_MANAGEMENT_1, WM8400_ROUT_ENA_SHIFT,
672 0, NULL, 0),
673
674/* LOPGA */
675SND_SOC_DAPM_PGA("LOPGA", WM8400_POWER_MANAGEMENT_3, WM8400_LOPGA_ENA_SHIFT, 0,
676 NULL, 0),
677
678/* ROPGA */
679SND_SOC_DAPM_PGA("ROPGA", WM8400_POWER_MANAGEMENT_3, WM8400_ROPGA_ENA_SHIFT, 0,
680 NULL, 0),
681
682/* MICBIAS */
683SND_SOC_DAPM_SUPPLY("MICBIAS", WM8400_POWER_MANAGEMENT_1,
684 WM8400_MIC1BIAS_ENA_SHIFT, 0, NULL, 0),
685
686SND_SOC_DAPM_OUTPUT("LON"),
687SND_SOC_DAPM_OUTPUT("LOP"),
688SND_SOC_DAPM_OUTPUT("OUT3"),
689SND_SOC_DAPM_OUTPUT("LOUT"),
690SND_SOC_DAPM_OUTPUT("SPKN"),
691SND_SOC_DAPM_OUTPUT("SPKP"),
692SND_SOC_DAPM_OUTPUT("ROUT"),
693SND_SOC_DAPM_OUTPUT("OUT4"),
694SND_SOC_DAPM_OUTPUT("ROP"),
695SND_SOC_DAPM_OUTPUT("RON"),
696
697SND_SOC_DAPM_OUTPUT("Internal DAC Sink"),
698};
699
700static const struct snd_soc_dapm_route wm8400_dapm_routes[] = {
701 /* Make DACs turn on when playing even if not mixed into any outputs */
702 {"Internal DAC Sink", NULL, "Left DAC"},
703 {"Internal DAC Sink", NULL, "Right DAC"},
704
705 /* Make ADCs turn on when recording
706 * even if not mixed from any inputs */
707 {"Left ADC", NULL, "Internal ADC Source"},
708 {"Right ADC", NULL, "Internal ADC Source"},
709
710 /* Input Side */
711 /* LIN12 PGA */
712 {"LIN12 PGA", "LIN1 Switch", "LIN1"},
713 {"LIN12 PGA", "LIN2 Switch", "LIN2"},
714 /* LIN34 PGA */
715 {"LIN34 PGA", "LIN3 Switch", "LIN3"},
716 {"LIN34 PGA", "LIN4 Switch", "LIN4/RXN"},
717 /* INMIXL */
718 {"INMIXL", NULL, "INL"},
719 {"INMIXL", "Record Left Volume", "LOMIX"},
720 {"INMIXL", "LIN2 Volume", "LIN2"},
721 {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"},
722 {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"},
723 /* AILNMUX */
724 {"AILNMUX", NULL, "INL"},
725 {"AILNMUX", "INMIXL Mix", "INMIXL"},
726 {"AILNMUX", "DIFFINL Mix", "LIN12 PGA"},
727 {"AILNMUX", "DIFFINL Mix", "LIN34 PGA"},
728 {"AILNMUX", "RXVOICE Mix", "LIN4/RXN"},
729 {"AILNMUX", "RXVOICE Mix", "RIN4/RXP"},
730 /* ADC */
731 {"Left ADC", NULL, "AILNMUX"},
732
733 /* RIN12 PGA */
734 {"RIN12 PGA", "RIN1 Switch", "RIN1"},
735 {"RIN12 PGA", "RIN2 Switch", "RIN2"},
736 /* RIN34 PGA */
737 {"RIN34 PGA", "RIN3 Switch", "RIN3"},
738 {"RIN34 PGA", "RIN4 Switch", "RIN4/RXP"},
739 /* INMIXR */
740 {"INMIXR", NULL, "INR"},
741 {"INMIXR", "Record Right Volume", "ROMIX"},
742 {"INMIXR", "RIN2 Volume", "RIN2"},
743 {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"},
744 {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"},
745 /* AIRNMUX */
746 {"AIRNMUX", NULL, "INR"},
747 {"AIRNMUX", "INMIXR Mix", "INMIXR"},
748 {"AIRNMUX", "DIFFINR Mix", "RIN12 PGA"},
749 {"AIRNMUX", "DIFFINR Mix", "RIN34 PGA"},
750 {"AIRNMUX", "RXVOICE Mix", "LIN4/RXN"},
751 {"AIRNMUX", "RXVOICE Mix", "RIN4/RXP"},
752 /* ADC */
753 {"Right ADC", NULL, "AIRNMUX"},
754
755 /* LOMIX */
756 {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"},
757 {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"},
758 {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
759 {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
760 {"LOMIX", "LOMIX Right ADC Bypass Switch", "AIRNMUX"},
761 {"LOMIX", "LOMIX Left ADC Bypass Switch", "AILNMUX"},
762 {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"},
763
764 /* ROMIX */
765 {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"},
766 {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"},
767 {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
768 {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
769 {"ROMIX", "ROMIX Right ADC Bypass Switch", "AIRNMUX"},
770 {"ROMIX", "ROMIX Left ADC Bypass Switch", "AILNMUX"},
771 {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"},
772
773 /* SPKMIX */
774 {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"},
775 {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"},
776 {"SPKMIX", "SPKMIX LADC Bypass Switch", "AILNMUX"},
777 {"SPKMIX", "SPKMIX RADC Bypass Switch", "AIRNMUX"},
778 {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"},
779 {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"},
780 {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"},
781 {"SPKMIX", "SPKMIX Left DAC Switch", "Right DAC"},
782
783 /* LONMIX */
784 {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"},
785 {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"},
786 {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"},
787
788 /* LOPMIX */
789 {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"},
790 {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"},
791 {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"},
792
793 /* OUT3MIX */
794 {"OUT3MIX", "OUT3MIX LIN4/RXP Bypass Switch", "LIN4/RXN"},
795 {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"},
796
797 /* OUT4MIX */
798 {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"},
799 {"OUT4MIX", "OUT4MIX RIN4/RXP Bypass Switch", "RIN4/RXP"},
800
801 /* RONMIX */
802 {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"},
803 {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"},
804 {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"},
805
806 /* ROPMIX */
807 {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"},
808 {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"},
809 {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"},
810
811 /* Out Mixer PGAs */
812 {"LOPGA", NULL, "LOMIX"},
813 {"ROPGA", NULL, "ROMIX"},
814
815 {"LOUT PGA", NULL, "LOMIX"},
816 {"ROUT PGA", NULL, "ROMIX"},
817
818 /* Output Pins */
819 {"LON", NULL, "LONMIX"},
820 {"LOP", NULL, "LOPMIX"},
821 {"OUT3", NULL, "OUT3MIX"},
822 {"LOUT", NULL, "LOUT PGA"},
823 {"SPKN", NULL, "SPKMIX"},
824 {"ROUT", NULL, "ROUT PGA"},
825 {"OUT4", NULL, "OUT4MIX"},
826 {"ROP", NULL, "ROPMIX"},
827 {"RON", NULL, "RONMIX"},
828};
829
830/*
831 * Clock after FLL and dividers
832 */
833static int wm8400_set_dai_sysclk(struct snd_soc_dai *codec_dai,
834 int clk_id, unsigned int freq, int dir)
835{
836 struct snd_soc_component *component = codec_dai->component;
837 struct wm8400_priv *wm8400 = snd_soc_component_get_drvdata(c: component);
838
839 wm8400->sysclk = freq;
840 return 0;
841}
842
843struct fll_factors {
844 u16 n;
845 u16 k;
846 u16 outdiv;
847 u16 fratio;
848 u16 freq_ref;
849};
850
851#define FIXED_FLL_SIZE ((1 << 16) * 10)
852
853static int fll_factors(struct wm8400_priv *wm8400, struct fll_factors *factors,
854 unsigned int Fref, unsigned int Fout)
855{
856 u64 Kpart;
857 unsigned int K, Nmod, target;
858
859 factors->outdiv = 2;
860 while (Fout * factors->outdiv < 90000000 ||
861 Fout * factors->outdiv > 100000000) {
862 factors->outdiv *= 2;
863 if (factors->outdiv > 32) {
864 dev_err(wm8400->wm8400->dev,
865 "Unsupported FLL output frequency %uHz\n",
866 Fout);
867 return -EINVAL;
868 }
869 }
870 target = Fout * factors->outdiv;
871 factors->outdiv = factors->outdiv >> 2;
872
873 if (Fref < 48000)
874 factors->freq_ref = 1;
875 else
876 factors->freq_ref = 0;
877
878 if (Fref < 1000000)
879 factors->fratio = 9;
880 else
881 factors->fratio = 0;
882
883 /* Ensure we have a fractional part */
884 do {
885 if (Fref < 1000000)
886 factors->fratio--;
887 else
888 factors->fratio++;
889
890 if (factors->fratio < 1 || factors->fratio > 8) {
891 dev_err(wm8400->wm8400->dev,
892 "Unable to calculate FRATIO\n");
893 return -EINVAL;
894 }
895
896 factors->n = target / (Fref * factors->fratio);
897 Nmod = target % (Fref * factors->fratio);
898 } while (Nmod == 0);
899
900 /* Calculate fractional part - scale up so we can round. */
901 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
902
903 do_div(Kpart, (Fref * factors->fratio));
904
905 K = Kpart & 0xFFFFFFFF;
906
907 if ((K % 10) >= 5)
908 K += 5;
909
910 /* Move down to proper range now rounding is done */
911 factors->k = K / 10;
912
913 dev_dbg(wm8400->wm8400->dev,
914 "FLL: Fref=%u Fout=%u N=%x K=%x, FRATIO=%x OUTDIV=%x\n",
915 Fref, Fout,
916 factors->n, factors->k, factors->fratio, factors->outdiv);
917
918 return 0;
919}
920
921static int wm8400_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
922 int source, unsigned int freq_in,
923 unsigned int freq_out)
924{
925 struct snd_soc_component *component = codec_dai->component;
926 struct wm8400_priv *wm8400 = snd_soc_component_get_drvdata(c: component);
927 struct fll_factors factors;
928 int ret;
929 u16 reg;
930
931 if (freq_in == wm8400->fll_in && freq_out == wm8400->fll_out)
932 return 0;
933
934 if (freq_out) {
935 ret = fll_factors(wm8400, factors: &factors, Fref: freq_in, Fout: freq_out);
936 if (ret != 0)
937 return ret;
938 } else {
939 /* Bodge GCC 4.4.0 uninitialised variable warning - it
940 * doesn't seem capable of working out that we exit if
941 * freq_out is 0 before any of the uses. */
942 memset(&factors, 0, sizeof(factors));
943 }
944
945 wm8400->fll_out = freq_out;
946 wm8400->fll_in = freq_in;
947
948 /* We *must* disable the FLL before any changes */
949 reg = snd_soc_component_read(component, WM8400_POWER_MANAGEMENT_2);
950 reg &= ~WM8400_FLL_ENA;
951 snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_2, val: reg);
952
953 reg = snd_soc_component_read(component, WM8400_FLL_CONTROL_1);
954 reg &= ~WM8400_FLL_OSC_ENA;
955 snd_soc_component_write(component, WM8400_FLL_CONTROL_1, val: reg);
956
957 if (!freq_out)
958 return 0;
959
960 reg &= ~(WM8400_FLL_REF_FREQ | WM8400_FLL_FRATIO_MASK);
961 reg |= WM8400_FLL_FRAC | factors.fratio;
962 reg |= factors.freq_ref << WM8400_FLL_REF_FREQ_SHIFT;
963 snd_soc_component_write(component, WM8400_FLL_CONTROL_1, val: reg);
964
965 snd_soc_component_write(component, WM8400_FLL_CONTROL_2, val: factors.k);
966 snd_soc_component_write(component, WM8400_FLL_CONTROL_3, val: factors.n);
967
968 reg = snd_soc_component_read(component, WM8400_FLL_CONTROL_4);
969 reg &= ~WM8400_FLL_OUTDIV_MASK;
970 reg |= factors.outdiv;
971 snd_soc_component_write(component, WM8400_FLL_CONTROL_4, val: reg);
972
973 return 0;
974}
975
976/*
977 * Sets ADC and Voice DAC format.
978 */
979static int wm8400_set_dai_fmt(struct snd_soc_dai *codec_dai,
980 unsigned int fmt)
981{
982 struct snd_soc_component *component = codec_dai->component;
983 u16 audio1, audio3;
984
985 audio1 = snd_soc_component_read(component, WM8400_AUDIO_INTERFACE_1);
986 audio3 = snd_soc_component_read(component, WM8400_AUDIO_INTERFACE_3);
987
988 /* set master/slave audio interface */
989 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
990 case SND_SOC_DAIFMT_CBC_CFC:
991 audio3 &= ~WM8400_AIF_MSTR1;
992 break;
993 case SND_SOC_DAIFMT_CBP_CFP:
994 audio3 |= WM8400_AIF_MSTR1;
995 break;
996 default:
997 return -EINVAL;
998 }
999
1000 audio1 &= ~WM8400_AIF_FMT_MASK;
1001
1002 /* interface format */
1003 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1004 case SND_SOC_DAIFMT_I2S:
1005 audio1 |= WM8400_AIF_FMT_I2S;
1006 audio1 &= ~WM8400_AIF_LRCLK_INV;
1007 break;
1008 case SND_SOC_DAIFMT_RIGHT_J:
1009 audio1 |= WM8400_AIF_FMT_RIGHTJ;
1010 audio1 &= ~WM8400_AIF_LRCLK_INV;
1011 break;
1012 case SND_SOC_DAIFMT_LEFT_J:
1013 audio1 |= WM8400_AIF_FMT_LEFTJ;
1014 audio1 &= ~WM8400_AIF_LRCLK_INV;
1015 break;
1016 case SND_SOC_DAIFMT_DSP_A:
1017 audio1 |= WM8400_AIF_FMT_DSP;
1018 audio1 &= ~WM8400_AIF_LRCLK_INV;
1019 break;
1020 case SND_SOC_DAIFMT_DSP_B:
1021 audio1 |= WM8400_AIF_FMT_DSP | WM8400_AIF_LRCLK_INV;
1022 break;
1023 default:
1024 return -EINVAL;
1025 }
1026
1027 snd_soc_component_write(component, WM8400_AUDIO_INTERFACE_1, val: audio1);
1028 snd_soc_component_write(component, WM8400_AUDIO_INTERFACE_3, val: audio3);
1029 return 0;
1030}
1031
1032static int wm8400_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
1033 int div_id, int div)
1034{
1035 struct snd_soc_component *component = codec_dai->component;
1036 u16 reg;
1037
1038 switch (div_id) {
1039 case WM8400_MCLK_DIV:
1040 reg = snd_soc_component_read(component, WM8400_CLOCKING_2) &
1041 ~WM8400_MCLK_DIV_MASK;
1042 snd_soc_component_write(component, WM8400_CLOCKING_2, val: reg | div);
1043 break;
1044 case WM8400_DACCLK_DIV:
1045 reg = snd_soc_component_read(component, WM8400_CLOCKING_2) &
1046 ~WM8400_DAC_CLKDIV_MASK;
1047 snd_soc_component_write(component, WM8400_CLOCKING_2, val: reg | div);
1048 break;
1049 case WM8400_ADCCLK_DIV:
1050 reg = snd_soc_component_read(component, WM8400_CLOCKING_2) &
1051 ~WM8400_ADC_CLKDIV_MASK;
1052 snd_soc_component_write(component, WM8400_CLOCKING_2, val: reg | div);
1053 break;
1054 case WM8400_BCLK_DIV:
1055 reg = snd_soc_component_read(component, WM8400_CLOCKING_1) &
1056 ~WM8400_BCLK_DIV_MASK;
1057 snd_soc_component_write(component, WM8400_CLOCKING_1, val: reg | div);
1058 break;
1059 default:
1060 return -EINVAL;
1061 }
1062
1063 return 0;
1064}
1065
1066/*
1067 * Set PCM DAI bit size and sample rate.
1068 */
1069static int wm8400_hw_params(struct snd_pcm_substream *substream,
1070 struct snd_pcm_hw_params *params,
1071 struct snd_soc_dai *dai)
1072{
1073 struct snd_soc_component *component = dai->component;
1074 u16 audio1 = snd_soc_component_read(component, WM8400_AUDIO_INTERFACE_1);
1075
1076 audio1 &= ~WM8400_AIF_WL_MASK;
1077 /* bit size */
1078 switch (params_width(p: params)) {
1079 case 16:
1080 break;
1081 case 20:
1082 audio1 |= WM8400_AIF_WL_20BITS;
1083 break;
1084 case 24:
1085 audio1 |= WM8400_AIF_WL_24BITS;
1086 break;
1087 case 32:
1088 audio1 |= WM8400_AIF_WL_32BITS;
1089 break;
1090 }
1091
1092 snd_soc_component_write(component, WM8400_AUDIO_INTERFACE_1, val: audio1);
1093 return 0;
1094}
1095
1096static int wm8400_mute(struct snd_soc_dai *dai, int mute, int direction)
1097{
1098 struct snd_soc_component *component = dai->component;
1099 u16 val = snd_soc_component_read(component, WM8400_DAC_CTRL) & ~WM8400_DAC_MUTE;
1100
1101 if (mute)
1102 snd_soc_component_write(component, WM8400_DAC_CTRL, val: val | WM8400_DAC_MUTE);
1103 else
1104 snd_soc_component_write(component, WM8400_DAC_CTRL, val);
1105
1106 return 0;
1107}
1108
1109/* TODO: set bias for best performance at standby */
1110static int wm8400_set_bias_level(struct snd_soc_component *component,
1111 enum snd_soc_bias_level level)
1112{
1113 struct wm8400_priv *wm8400 = snd_soc_component_get_drvdata(c: component);
1114 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
1115 u16 val;
1116 int ret;
1117
1118 switch (level) {
1119 case SND_SOC_BIAS_ON:
1120 break;
1121
1122 case SND_SOC_BIAS_PREPARE:
1123 /* VMID=2*50k */
1124 val = snd_soc_component_read(component, WM8400_POWER_MANAGEMENT_1) &
1125 ~WM8400_VMID_MODE_MASK;
1126 snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1, val: val | 0x2);
1127 break;
1128
1129 case SND_SOC_BIAS_STANDBY:
1130 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF) {
1131 ret = regulator_bulk_enable(ARRAY_SIZE(power),
1132 consumers: &power[0]);
1133 if (ret != 0) {
1134 dev_err(wm8400->wm8400->dev,
1135 "Failed to enable regulators: %d\n",
1136 ret);
1137 return ret;
1138 }
1139
1140 snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1,
1141 WM8400_CODEC_ENA | WM8400_SYSCLK_ENA);
1142
1143 /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */
1144 snd_soc_component_write(component, WM8400_ANTIPOP2, WM8400_SOFTST |
1145 WM8400_BUFDCOPEN | WM8400_POBCTRL);
1146
1147 msleep(msecs: 50);
1148
1149 /* Enable VREF & VMID at 2x50k */
1150 val = snd_soc_component_read(component, WM8400_POWER_MANAGEMENT_1);
1151 val |= 0x2 | WM8400_VREF_ENA;
1152 snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1, val);
1153
1154 /* Enable BUFIOEN */
1155 snd_soc_component_write(component, WM8400_ANTIPOP2, WM8400_SOFTST |
1156 WM8400_BUFDCOPEN | WM8400_POBCTRL |
1157 WM8400_BUFIOEN);
1158
1159 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1160 snd_soc_component_write(component, WM8400_ANTIPOP2, WM8400_BUFIOEN);
1161 }
1162
1163 /* VMID=2*300k */
1164 val = snd_soc_component_read(component, WM8400_POWER_MANAGEMENT_1) &
1165 ~WM8400_VMID_MODE_MASK;
1166 snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1, val: val | 0x4);
1167 break;
1168
1169 case SND_SOC_BIAS_OFF:
1170 /* Enable POBCTRL and SOFT_ST */
1171 snd_soc_component_write(component, WM8400_ANTIPOP2, WM8400_SOFTST |
1172 WM8400_POBCTRL | WM8400_BUFIOEN);
1173
1174 /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */
1175 snd_soc_component_write(component, WM8400_ANTIPOP2, WM8400_SOFTST |
1176 WM8400_BUFDCOPEN | WM8400_POBCTRL |
1177 WM8400_BUFIOEN);
1178
1179 /* mute DAC */
1180 val = snd_soc_component_read(component, WM8400_DAC_CTRL);
1181 snd_soc_component_write(component, WM8400_DAC_CTRL, val: val | WM8400_DAC_MUTE);
1182
1183 /* Enable any disabled outputs */
1184 val = snd_soc_component_read(component, WM8400_POWER_MANAGEMENT_1);
1185 val |= WM8400_SPK_ENA | WM8400_OUT3_ENA |
1186 WM8400_OUT4_ENA | WM8400_LOUT_ENA |
1187 WM8400_ROUT_ENA;
1188 snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1, val);
1189
1190 /* Disable VMID */
1191 val &= ~WM8400_VMID_MODE_MASK;
1192 snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1, val);
1193
1194 msleep(msecs: 300);
1195
1196 /* Enable all output discharge bits */
1197 snd_soc_component_write(component, WM8400_ANTIPOP1, WM8400_DIS_LLINE |
1198 WM8400_DIS_RLINE | WM8400_DIS_OUT3 |
1199 WM8400_DIS_OUT4 | WM8400_DIS_LOUT |
1200 WM8400_DIS_ROUT);
1201
1202 /* Disable VREF */
1203 val &= ~WM8400_VREF_ENA;
1204 snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1, val);
1205
1206 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1207 snd_soc_component_write(component, WM8400_ANTIPOP2, val: 0x0);
1208
1209 ret = regulator_bulk_disable(ARRAY_SIZE(power),
1210 consumers: &power[0]);
1211 if (ret != 0)
1212 return ret;
1213
1214 break;
1215 }
1216
1217 return 0;
1218}
1219
1220#define WM8400_RATES SNDRV_PCM_RATE_8000_96000
1221
1222#define WM8400_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1223 SNDRV_PCM_FMTBIT_S24_LE)
1224
1225static const struct snd_soc_dai_ops wm8400_dai_ops = {
1226 .hw_params = wm8400_hw_params,
1227 .mute_stream = wm8400_mute,
1228 .set_fmt = wm8400_set_dai_fmt,
1229 .set_clkdiv = wm8400_set_dai_clkdiv,
1230 .set_sysclk = wm8400_set_dai_sysclk,
1231 .set_pll = wm8400_set_dai_pll,
1232 .no_capture_mute = 1,
1233};
1234
1235/*
1236 * The WM8400 supports 2 different and mutually exclusive DAI
1237 * configurations.
1238 *
1239 * 1. ADC/DAC on Primary Interface
1240 * 2. ADC on Primary Interface/DAC on secondary
1241 */
1242static struct snd_soc_dai_driver wm8400_dai = {
1243/* ADC/DAC on primary */
1244 .name = "wm8400-hifi",
1245 .playback = {
1246 .stream_name = "Playback",
1247 .channels_min = 1,
1248 .channels_max = 2,
1249 .rates = WM8400_RATES,
1250 .formats = WM8400_FORMATS,
1251 },
1252 .capture = {
1253 .stream_name = "Capture",
1254 .channels_min = 1,
1255 .channels_max = 2,
1256 .rates = WM8400_RATES,
1257 .formats = WM8400_FORMATS,
1258 },
1259 .ops = &wm8400_dai_ops,
1260};
1261
1262static int wm8400_component_probe(struct snd_soc_component *component)
1263{
1264 struct wm8400 *wm8400 = dev_get_platdata(dev: component->dev);
1265 struct wm8400_priv *priv;
1266 int ret;
1267 u16 reg;
1268
1269 priv = devm_kzalloc(dev: component->dev, size: sizeof(struct wm8400_priv),
1270 GFP_KERNEL);
1271 if (priv == NULL)
1272 return -ENOMEM;
1273
1274 snd_soc_component_init_regmap(component, regmap: wm8400->regmap);
1275 snd_soc_component_set_drvdata(c: component, data: priv);
1276 priv->wm8400 = wm8400;
1277
1278 ret = devm_regulator_bulk_get(dev: wm8400->dev,
1279 ARRAY_SIZE(power), consumers: &power[0]);
1280 if (ret != 0) {
1281 dev_err(component->dev, "Failed to get regulators: %d\n", ret);
1282 return ret;
1283 }
1284
1285 wm8400_component_reset(component);
1286
1287 reg = snd_soc_component_read(component, WM8400_POWER_MANAGEMENT_1);
1288 snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1, val: reg | WM8400_CODEC_ENA);
1289
1290 /* Latch volume update bits */
1291 reg = snd_soc_component_read(component, WM8400_LEFT_LINE_INPUT_1_2_VOLUME);
1292 snd_soc_component_write(component, WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
1293 val: reg & WM8400_IPVU);
1294 reg = snd_soc_component_read(component, WM8400_RIGHT_LINE_INPUT_1_2_VOLUME);
1295 snd_soc_component_write(component, WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
1296 val: reg & WM8400_IPVU);
1297
1298 snd_soc_component_write(component, WM8400_LEFT_OUTPUT_VOLUME, val: 0x50 | (1<<8));
1299 snd_soc_component_write(component, WM8400_RIGHT_OUTPUT_VOLUME, val: 0x50 | (1<<8));
1300
1301 return 0;
1302}
1303
1304static void wm8400_component_remove(struct snd_soc_component *component)
1305{
1306 u16 reg;
1307
1308 reg = snd_soc_component_read(component, WM8400_POWER_MANAGEMENT_1);
1309 snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1,
1310 val: reg & (~WM8400_CODEC_ENA));
1311}
1312
1313static const struct snd_soc_component_driver soc_component_dev_wm8400 = {
1314 .probe = wm8400_component_probe,
1315 .remove = wm8400_component_remove,
1316 .set_bias_level = wm8400_set_bias_level,
1317 .controls = wm8400_snd_controls,
1318 .num_controls = ARRAY_SIZE(wm8400_snd_controls),
1319 .dapm_widgets = wm8400_dapm_widgets,
1320 .num_dapm_widgets = ARRAY_SIZE(wm8400_dapm_widgets),
1321 .dapm_routes = wm8400_dapm_routes,
1322 .num_dapm_routes = ARRAY_SIZE(wm8400_dapm_routes),
1323 .suspend_bias_off = 1,
1324 .idle_bias_on = 1,
1325 .use_pmdown_time = 1,
1326 .endianness = 1,
1327};
1328
1329static int wm8400_probe(struct platform_device *pdev)
1330{
1331 return devm_snd_soc_register_component(dev: &pdev->dev,
1332 component_driver: &soc_component_dev_wm8400,
1333 dai_drv: &wm8400_dai, num_dai: 1);
1334}
1335
1336static struct platform_driver wm8400_codec_driver = {
1337 .driver = {
1338 .name = "wm8400-codec",
1339 },
1340 .probe = wm8400_probe,
1341};
1342
1343module_platform_driver(wm8400_codec_driver);
1344
1345MODULE_DESCRIPTION("ASoC WM8400 driver");
1346MODULE_AUTHOR("Mark Brown");
1347MODULE_LICENSE("GPL");
1348MODULE_ALIAS("platform:wm8400-codec");
1349

source code of linux/sound/soc/codecs/wm8400.c