1//===--- Mips.cpp - Implement Mips target feature support -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements Mips TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#include "Mips.h"
14#include "Targets.h"
15#include "clang/Basic/Diagnostic.h"
16#include "clang/Basic/MacroBuilder.h"
17#include "clang/Basic/TargetBuiltins.h"
18#include "llvm/ADT/StringSwitch.h"
19
20using namespace clang;
21using namespace clang::targets;
22
23static constexpr Builtin::Info BuiltinInfo[] = {
24#define BUILTIN(ID, TYPE, ATTRS) \
25 {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
26#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
27 {#ID, TYPE, ATTRS, nullptr, HeaderDesc::HEADER, ALL_LANGUAGES},
28#include "clang/Basic/BuiltinsMips.def"
29};
30
31bool MipsTargetInfo::processorSupportsGPR64() const {
32 return llvm::StringSwitch<bool>(CPU)
33 .Case(S: "mips3", Value: true)
34 .Case(S: "mips4", Value: true)
35 .Case(S: "mips5", Value: true)
36 .Case(S: "mips64", Value: true)
37 .Case(S: "mips64r2", Value: true)
38 .Case(S: "mips64r3", Value: true)
39 .Case(S: "mips64r5", Value: true)
40 .Case(S: "mips64r6", Value: true)
41 .Case(S: "octeon", Value: true)
42 .Case(S: "octeon+", Value: true)
43 .Default(Value: false);
44}
45
46static constexpr llvm::StringLiteral ValidCPUNames[] = {
47 {"mips1"}, {"mips2"}, {"mips3"}, {"mips4"}, {"mips5"},
48 {"mips32"}, {"mips32r2"}, {"mips32r3"}, {"mips32r5"}, {"mips32r6"},
49 {"mips64"}, {"mips64r2"}, {"mips64r3"}, {"mips64r5"}, {"mips64r6"},
50 {"octeon"}, {"octeon+"}, {"p5600"}};
51
52bool MipsTargetInfo::isValidCPUName(StringRef Name) const {
53 return llvm::is_contained(Range: ValidCPUNames, Element: Name);
54}
55
56void MipsTargetInfo::fillValidCPUList(
57 SmallVectorImpl<StringRef> &Values) const {
58 Values.append(in_start: std::begin(arr: ValidCPUNames), in_end: std::end(arr: ValidCPUNames));
59}
60
61unsigned MipsTargetInfo::getISARev() const {
62 return llvm::StringSwitch<unsigned>(getCPU())
63 .Cases(S0: "mips32", S1: "mips64", Value: 1)
64 .Cases(S0: "mips32r2", S1: "mips64r2", S2: "octeon", S3: "octeon+", Value: 2)
65 .Cases(S0: "mips32r3", S1: "mips64r3", Value: 3)
66 .Cases(S0: "mips32r5", S1: "mips64r5", Value: 5)
67 .Cases(S0: "mips32r6", S1: "mips64r6", Value: 6)
68 .Default(Value: 0);
69}
70
71void MipsTargetInfo::getTargetDefines(const LangOptions &Opts,
72 MacroBuilder &Builder) const {
73 if (BigEndian) {
74 DefineStd(Builder, MacroName: "MIPSEB", Opts);
75 Builder.defineMacro(Name: "_MIPSEB");
76 } else {
77 DefineStd(Builder, MacroName: "MIPSEL", Opts);
78 Builder.defineMacro(Name: "_MIPSEL");
79 }
80
81 Builder.defineMacro(Name: "__mips__");
82 Builder.defineMacro(Name: "_mips");
83 if (Opts.GNUMode)
84 Builder.defineMacro(Name: "mips");
85
86 if (ABI == "o32") {
87 Builder.defineMacro(Name: "__mips", Value: "32");
88 Builder.defineMacro(Name: "_MIPS_ISA", Value: "_MIPS_ISA_MIPS32");
89 } else {
90 Builder.defineMacro(Name: "__mips", Value: "64");
91 Builder.defineMacro(Name: "__mips64");
92 Builder.defineMacro(Name: "__mips64__");
93 Builder.defineMacro(Name: "_MIPS_ISA", Value: "_MIPS_ISA_MIPS64");
94 }
95
96 const std::string ISARev = std::to_string(val: getISARev());
97
98 if (!ISARev.empty())
99 Builder.defineMacro(Name: "__mips_isa_rev", Value: ISARev);
100
101 if (ABI == "o32") {
102 Builder.defineMacro(Name: "__mips_o32");
103 Builder.defineMacro(Name: "_ABIO32", Value: "1");
104 Builder.defineMacro(Name: "_MIPS_SIM", Value: "_ABIO32");
105 } else if (ABI == "n32") {
106 Builder.defineMacro(Name: "__mips_n32");
107 Builder.defineMacro(Name: "_ABIN32", Value: "2");
108 Builder.defineMacro(Name: "_MIPS_SIM", Value: "_ABIN32");
109 } else if (ABI == "n64") {
110 Builder.defineMacro(Name: "__mips_n64");
111 Builder.defineMacro(Name: "_ABI64", Value: "3");
112 Builder.defineMacro(Name: "_MIPS_SIM", Value: "_ABI64");
113 } else
114 llvm_unreachable("Invalid ABI.");
115
116 if (!IsNoABICalls) {
117 Builder.defineMacro(Name: "__mips_abicalls");
118 if (CanUseBSDABICalls)
119 Builder.defineMacro(Name: "__ABICALLS__");
120 }
121
122 Builder.defineMacro(Name: "__REGISTER_PREFIX__", Value: "");
123
124 switch (FloatABI) {
125 case HardFloat:
126 Builder.defineMacro(Name: "__mips_hard_float", Value: Twine(1));
127 break;
128 case SoftFloat:
129 Builder.defineMacro(Name: "__mips_soft_float", Value: Twine(1));
130 break;
131 }
132
133 if (IsSingleFloat)
134 Builder.defineMacro(Name: "__mips_single_float", Value: Twine(1));
135
136 switch (FPMode) {
137 case FPXX:
138 Builder.defineMacro(Name: "__mips_fpr", Value: Twine(0));
139 break;
140 case FP32:
141 Builder.defineMacro(Name: "__mips_fpr", Value: Twine(32));
142 break;
143 case FP64:
144 Builder.defineMacro(Name: "__mips_fpr", Value: Twine(64));
145 break;
146}
147
148 if (FPMode == FP64 || IsSingleFloat)
149 Builder.defineMacro(Name: "_MIPS_FPSET", Value: Twine(32));
150 else
151 Builder.defineMacro(Name: "_MIPS_FPSET", Value: Twine(16));
152 if (NoOddSpreg)
153 Builder.defineMacro(Name: "_MIPS_SPFPSET", Value: Twine(16));
154 else
155 Builder.defineMacro(Name: "_MIPS_SPFPSET", Value: Twine(32));
156
157 if (IsMips16)
158 Builder.defineMacro(Name: "__mips16", Value: Twine(1));
159
160 if (IsMicromips)
161 Builder.defineMacro(Name: "__mips_micromips", Value: Twine(1));
162
163 if (IsNan2008)
164 Builder.defineMacro(Name: "__mips_nan2008", Value: Twine(1));
165
166 if (IsAbs2008)
167 Builder.defineMacro(Name: "__mips_abs2008", Value: Twine(1));
168
169 switch (DspRev) {
170 default:
171 break;
172 case DSP1:
173 Builder.defineMacro(Name: "__mips_dsp_rev", Value: Twine(1));
174 Builder.defineMacro(Name: "__mips_dsp", Value: Twine(1));
175 break;
176 case DSP2:
177 Builder.defineMacro(Name: "__mips_dsp_rev", Value: Twine(2));
178 Builder.defineMacro(Name: "__mips_dspr2", Value: Twine(1));
179 Builder.defineMacro(Name: "__mips_dsp", Value: Twine(1));
180 break;
181 }
182
183 if (HasMSA)
184 Builder.defineMacro(Name: "__mips_msa", Value: Twine(1));
185
186 if (DisableMadd4)
187 Builder.defineMacro(Name: "__mips_no_madd4", Value: Twine(1));
188
189 Builder.defineMacro(Name: "_MIPS_SZPTR", Value: Twine(getPointerWidth(AddrSpace: LangAS::Default)));
190 Builder.defineMacro(Name: "_MIPS_SZINT", Value: Twine(getIntWidth()));
191 Builder.defineMacro(Name: "_MIPS_SZLONG", Value: Twine(getLongWidth()));
192
193 Builder.defineMacro(Name: "_MIPS_ARCH", Value: "\"" + CPU + "\"");
194 if (CPU == "octeon+")
195 Builder.defineMacro(Name: "_MIPS_ARCH_OCTEONP");
196 else
197 Builder.defineMacro(Name: "_MIPS_ARCH_" + StringRef(CPU).upper());
198
199 if (StringRef(CPU).starts_with(Prefix: "octeon"))
200 Builder.defineMacro(Name: "__OCTEON__");
201
202 if (CPU != "mips1") {
203 Builder.defineMacro(Name: "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
204 Builder.defineMacro(Name: "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
205 Builder.defineMacro(Name: "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
206 }
207
208 // 32-bit MIPS processors don't have the necessary lld/scd instructions
209 // found in 64-bit processors. In the case of O32 on a 64-bit processor,
210 // the instructions exist but using them violates the ABI since they
211 // require 64-bit GPRs and O32 only supports 32-bit GPRs.
212 if (ABI == "n32" || ABI == "n64")
213 Builder.defineMacro(Name: "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
214}
215
216bool MipsTargetInfo::hasFeature(StringRef Feature) const {
217 return llvm::StringSwitch<bool>(Feature)
218 .Case(S: "mips", Value: true)
219 .Case(S: "dsp", Value: DspRev >= DSP1)
220 .Case(S: "dspr2", Value: DspRev >= DSP2)
221 .Case(S: "fp64", Value: FPMode == FP64)
222 .Case(S: "msa", Value: HasMSA)
223 .Default(Value: false);
224}
225
226ArrayRef<Builtin::Info> MipsTargetInfo::getTargetBuiltins() const {
227 return llvm::ArrayRef(BuiltinInfo,
228 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin);
229}
230
231unsigned MipsTargetInfo::getUnwindWordWidth() const {
232 return llvm::StringSwitch<unsigned>(ABI)
233 .Case(S: "o32", Value: 32)
234 .Case(S: "n32", Value: 64)
235 .Case(S: "n64", Value: 64)
236 .Default(Value: getPointerWidth(AddrSpace: LangAS::Default));
237}
238
239bool MipsTargetInfo::validateTarget(DiagnosticsEngine &Diags) const {
240 // microMIPS64R6 backend was removed.
241 if (getTriple().isMIPS64() && IsMicromips && (ABI == "n32" || ABI == "n64")) {
242 Diags.Report(diag::err_target_unsupported_cpu_for_micromips) << CPU;
243 return false;
244 }
245
246 // 64-bit ABI's require 64-bit CPU's.
247 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) {
248 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU;
249 return false;
250 }
251
252 // -fpxx is valid only for the o32 ABI
253 if (FPMode == FPXX && (ABI == "n32" || ABI == "n64")) {
254 Diags.Report(diag::err_unsupported_abi_for_opt) << "-mfpxx" << "o32";
255 return false;
256 }
257
258 // -mfp32 and n32/n64 ABIs are incompatible
259 if (FPMode != FP64 && FPMode != FPXX && !IsSingleFloat &&
260 (ABI == "n32" || ABI == "n64")) {
261 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfpxx" << CPU;
262 return false;
263 }
264 // Mips revision 6 and -mfp32 are incompatible
265 if (FPMode != FP64 && FPMode != FPXX && (CPU == "mips32r6" ||
266 CPU == "mips64r6")) {
267 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfp32" << CPU;
268 return false;
269 }
270 // Option -mfp64 permitted on Mips32 iff revision 2 or higher is present
271 if (FPMode == FP64 && (CPU == "mips1" || CPU == "mips2" ||
272 getISARev() < 2) && ABI == "o32") {
273 Diags.Report(diag::err_mips_fp64_req) << "-mfp64";
274 return false;
275 }
276
277 return true;
278}
279

source code of clang/lib/Basic/Targets/Mips.cpp