1//===-- ArchSpec.cpp ------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "lldb/Utility/ArchSpec.h"
10#include "lldb/Utility/LLDBLog.h"
11
12#include "lldb/Utility/Log.h"
13#include "lldb/Utility/StringList.h"
14#include "lldb/lldb-defines.h"
15#include "llvm/ADT/STLExtras.h"
16#include "llvm/BinaryFormat/COFF.h"
17#include "llvm/BinaryFormat/ELF.h"
18#include "llvm/BinaryFormat/MachO.h"
19#include "llvm/BinaryFormat/XCOFF.h"
20#include "llvm/Support/Compiler.h"
21#include "llvm/TargetParser/ARMTargetParser.h"
22
23using namespace lldb;
24using namespace lldb_private;
25
26static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2,
27 bool try_inverse, bool enforce_exact_match);
28
29namespace lldb_private {
30
31struct CoreDefinition {
32 ByteOrder default_byte_order;
33 uint32_t addr_byte_size;
34 uint32_t min_opcode_byte_size;
35 uint32_t max_opcode_byte_size;
36 llvm::Triple::ArchType machine;
37 ArchSpec::Core core;
38 const char *const name;
39};
40
41} // namespace lldb_private
42
43// This core information can be looked using the ArchSpec::Core as the index
44static const CoreDefinition g_core_definitions[] = {
45 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::arm, .core: ArchSpec::eCore_arm_generic,
46 .name: "arm"},
47 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::arm, .core: ArchSpec::eCore_arm_armv4,
48 .name: "armv4"},
49 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::arm, .core: ArchSpec::eCore_arm_armv4t,
50 .name: "armv4t"},
51 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::arm, .core: ArchSpec::eCore_arm_armv5,
52 .name: "armv5"},
53 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::arm, .core: ArchSpec::eCore_arm_armv5e,
54 .name: "armv5e"},
55 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::arm, .core: ArchSpec::eCore_arm_armv5t,
56 .name: "armv5t"},
57 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::arm, .core: ArchSpec::eCore_arm_armv6,
58 .name: "armv6"},
59 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::arm, .core: ArchSpec::eCore_arm_armv6m,
60 .name: "armv6m"},
61 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::arm, .core: ArchSpec::eCore_arm_armv7,
62 .name: "armv7"},
63 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::arm, .core: ArchSpec::eCore_arm_armv7a,
64 .name: "armv7a"},
65 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::arm, .core: ArchSpec::eCore_arm_armv7l,
66 .name: "armv7l"},
67 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::arm, .core: ArchSpec::eCore_arm_armv7f,
68 .name: "armv7f"},
69 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::arm, .core: ArchSpec::eCore_arm_armv7s,
70 .name: "armv7s"},
71 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::arm, .core: ArchSpec::eCore_arm_armv7k,
72 .name: "armv7k"},
73 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::arm, .core: ArchSpec::eCore_arm_armv7m,
74 .name: "armv7m"},
75 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::arm, .core: ArchSpec::eCore_arm_armv7em,
76 .name: "armv7em"},
77 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::arm, .core: ArchSpec::eCore_arm_xscale,
78 .name: "xscale"},
79 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::thumb, .core: ArchSpec::eCore_thumb,
80 .name: "thumb"},
81 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::thumb, .core: ArchSpec::eCore_thumbv4t,
82 .name: "thumbv4t"},
83 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::thumb, .core: ArchSpec::eCore_thumbv5,
84 .name: "thumbv5"},
85 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::thumb, .core: ArchSpec::eCore_thumbv5e,
86 .name: "thumbv5e"},
87 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::thumb, .core: ArchSpec::eCore_thumbv6,
88 .name: "thumbv6"},
89 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::thumb, .core: ArchSpec::eCore_thumbv6m,
90 .name: "thumbv6m"},
91 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::thumb, .core: ArchSpec::eCore_thumbv7,
92 .name: "thumbv7"},
93 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::thumb, .core: ArchSpec::eCore_thumbv7f,
94 .name: "thumbv7f"},
95 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::thumb, .core: ArchSpec::eCore_thumbv7s,
96 .name: "thumbv7s"},
97 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::thumb, .core: ArchSpec::eCore_thumbv7k,
98 .name: "thumbv7k"},
99 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::thumb, .core: ArchSpec::eCore_thumbv7m,
100 .name: "thumbv7m"},
101 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::thumb, .core: ArchSpec::eCore_thumbv7em,
102 .name: "thumbv7em"},
103 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 8, .min_opcode_byte_size: 4, .max_opcode_byte_size: 4, .machine: llvm::Triple::aarch64,
104 .core: ArchSpec::eCore_arm_arm64, .name: "arm64"},
105 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 8, .min_opcode_byte_size: 4, .max_opcode_byte_size: 4, .machine: llvm::Triple::aarch64,
106 .core: ArchSpec::eCore_arm_armv8, .name: "armv8"},
107 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 8, .min_opcode_byte_size: 4, .max_opcode_byte_size: 4, .machine: llvm::Triple::aarch64,
108 .core: ArchSpec::eCore_arm_armv8a, .name: "armv8a"},
109 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::arm, .core: ArchSpec::eCore_arm_armv8l,
110 .name: "armv8l"},
111 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 8, .min_opcode_byte_size: 4, .max_opcode_byte_size: 4, .machine: llvm::Triple::aarch64,
112 .core: ArchSpec::eCore_arm_arm64e, .name: "arm64e"},
113 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 4, .max_opcode_byte_size: 4, .machine: llvm::Triple::aarch64_32,
114 .core: ArchSpec::eCore_arm_arm64_32, .name: "arm64_32"},
115 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 8, .min_opcode_byte_size: 4, .max_opcode_byte_size: 4, .machine: llvm::Triple::aarch64,
116 .core: ArchSpec::eCore_arm_aarch64, .name: "aarch64"},
117
118 // mips32, mips32r2, mips32r3, mips32r5, mips32r6
119 {.default_byte_order: eByteOrderBig, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::mips, .core: ArchSpec::eCore_mips32,
120 .name: "mips"},
121 {.default_byte_order: eByteOrderBig, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::mips, .core: ArchSpec::eCore_mips32r2,
122 .name: "mipsr2"},
123 {.default_byte_order: eByteOrderBig, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::mips, .core: ArchSpec::eCore_mips32r3,
124 .name: "mipsr3"},
125 {.default_byte_order: eByteOrderBig, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::mips, .core: ArchSpec::eCore_mips32r5,
126 .name: "mipsr5"},
127 {.default_byte_order: eByteOrderBig, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::mips, .core: ArchSpec::eCore_mips32r6,
128 .name: "mipsr6"},
129 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::mipsel, .core: ArchSpec::eCore_mips32el,
130 .name: "mipsel"},
131 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::mipsel,
132 .core: ArchSpec::eCore_mips32r2el, .name: "mipsr2el"},
133 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::mipsel,
134 .core: ArchSpec::eCore_mips32r3el, .name: "mipsr3el"},
135 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::mipsel,
136 .core: ArchSpec::eCore_mips32r5el, .name: "mipsr5el"},
137 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::mipsel,
138 .core: ArchSpec::eCore_mips32r6el, .name: "mipsr6el"},
139
140 // mips64, mips64r2, mips64r3, mips64r5, mips64r6
141 {.default_byte_order: eByteOrderBig, .addr_byte_size: 8, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::mips64, .core: ArchSpec::eCore_mips64,
142 .name: "mips64"},
143 {.default_byte_order: eByteOrderBig, .addr_byte_size: 8, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::mips64, .core: ArchSpec::eCore_mips64r2,
144 .name: "mips64r2"},
145 {.default_byte_order: eByteOrderBig, .addr_byte_size: 8, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::mips64, .core: ArchSpec::eCore_mips64r3,
146 .name: "mips64r3"},
147 {.default_byte_order: eByteOrderBig, .addr_byte_size: 8, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::mips64, .core: ArchSpec::eCore_mips64r5,
148 .name: "mips64r5"},
149 {.default_byte_order: eByteOrderBig, .addr_byte_size: 8, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::mips64, .core: ArchSpec::eCore_mips64r6,
150 .name: "mips64r6"},
151 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 8, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::mips64el,
152 .core: ArchSpec::eCore_mips64el, .name: "mips64el"},
153 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 8, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::mips64el,
154 .core: ArchSpec::eCore_mips64r2el, .name: "mips64r2el"},
155 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 8, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::mips64el,
156 .core: ArchSpec::eCore_mips64r3el, .name: "mips64r3el"},
157 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 8, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::mips64el,
158 .core: ArchSpec::eCore_mips64r5el, .name: "mips64r5el"},
159 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 8, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::mips64el,
160 .core: ArchSpec::eCore_mips64r6el, .name: "mips64r6el"},
161
162 // MSP430
163 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 2, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::msp430, .core: ArchSpec::eCore_msp430,
164 .name: "msp430"},
165
166 {.default_byte_order: eByteOrderBig, .addr_byte_size: 4, .min_opcode_byte_size: 4, .max_opcode_byte_size: 4, .machine: llvm::Triple::ppc, .core: ArchSpec::eCore_ppc_generic,
167 .name: "powerpc"},
168 {.default_byte_order: eByteOrderBig, .addr_byte_size: 4, .min_opcode_byte_size: 4, .max_opcode_byte_size: 4, .machine: llvm::Triple::ppc, .core: ArchSpec::eCore_ppc_ppc601,
169 .name: "ppc601"},
170 {.default_byte_order: eByteOrderBig, .addr_byte_size: 4, .min_opcode_byte_size: 4, .max_opcode_byte_size: 4, .machine: llvm::Triple::ppc, .core: ArchSpec::eCore_ppc_ppc602,
171 .name: "ppc602"},
172 {.default_byte_order: eByteOrderBig, .addr_byte_size: 4, .min_opcode_byte_size: 4, .max_opcode_byte_size: 4, .machine: llvm::Triple::ppc, .core: ArchSpec::eCore_ppc_ppc603,
173 .name: "ppc603"},
174 {.default_byte_order: eByteOrderBig, .addr_byte_size: 4, .min_opcode_byte_size: 4, .max_opcode_byte_size: 4, .machine: llvm::Triple::ppc, .core: ArchSpec::eCore_ppc_ppc603e,
175 .name: "ppc603e"},
176 {.default_byte_order: eByteOrderBig, .addr_byte_size: 4, .min_opcode_byte_size: 4, .max_opcode_byte_size: 4, .machine: llvm::Triple::ppc, .core: ArchSpec::eCore_ppc_ppc603ev,
177 .name: "ppc603ev"},
178 {.default_byte_order: eByteOrderBig, .addr_byte_size: 4, .min_opcode_byte_size: 4, .max_opcode_byte_size: 4, .machine: llvm::Triple::ppc, .core: ArchSpec::eCore_ppc_ppc604,
179 .name: "ppc604"},
180 {.default_byte_order: eByteOrderBig, .addr_byte_size: 4, .min_opcode_byte_size: 4, .max_opcode_byte_size: 4, .machine: llvm::Triple::ppc, .core: ArchSpec::eCore_ppc_ppc604e,
181 .name: "ppc604e"},
182 {.default_byte_order: eByteOrderBig, .addr_byte_size: 4, .min_opcode_byte_size: 4, .max_opcode_byte_size: 4, .machine: llvm::Triple::ppc, .core: ArchSpec::eCore_ppc_ppc620,
183 .name: "ppc620"},
184 {.default_byte_order: eByteOrderBig, .addr_byte_size: 4, .min_opcode_byte_size: 4, .max_opcode_byte_size: 4, .machine: llvm::Triple::ppc, .core: ArchSpec::eCore_ppc_ppc750,
185 .name: "ppc750"},
186 {.default_byte_order: eByteOrderBig, .addr_byte_size: 4, .min_opcode_byte_size: 4, .max_opcode_byte_size: 4, .machine: llvm::Triple::ppc, .core: ArchSpec::eCore_ppc_ppc7400,
187 .name: "ppc7400"},
188 {.default_byte_order: eByteOrderBig, .addr_byte_size: 4, .min_opcode_byte_size: 4, .max_opcode_byte_size: 4, .machine: llvm::Triple::ppc, .core: ArchSpec::eCore_ppc_ppc7450,
189 .name: "ppc7450"},
190 {.default_byte_order: eByteOrderBig, .addr_byte_size: 4, .min_opcode_byte_size: 4, .max_opcode_byte_size: 4, .machine: llvm::Triple::ppc, .core: ArchSpec::eCore_ppc_ppc970,
191 .name: "ppc970"},
192
193 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 8, .min_opcode_byte_size: 4, .max_opcode_byte_size: 4, .machine: llvm::Triple::ppc64le,
194 .core: ArchSpec::eCore_ppc64le_generic, .name: "powerpc64le"},
195 {.default_byte_order: eByteOrderBig, .addr_byte_size: 8, .min_opcode_byte_size: 4, .max_opcode_byte_size: 4, .machine: llvm::Triple::ppc64, .core: ArchSpec::eCore_ppc64_generic,
196 .name: "powerpc64"},
197 {.default_byte_order: eByteOrderBig, .addr_byte_size: 8, .min_opcode_byte_size: 4, .max_opcode_byte_size: 4, .machine: llvm::Triple::ppc64,
198 .core: ArchSpec::eCore_ppc64_ppc970_64, .name: "ppc970-64"},
199
200 {.default_byte_order: eByteOrderBig, .addr_byte_size: 8, .min_opcode_byte_size: 2, .max_opcode_byte_size: 6, .machine: llvm::Triple::systemz,
201 .core: ArchSpec::eCore_s390x_generic, .name: "s390x"},
202
203 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 4, .max_opcode_byte_size: 4, .machine: llvm::Triple::sparc,
204 .core: ArchSpec::eCore_sparc_generic, .name: "sparc"},
205 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 8, .min_opcode_byte_size: 4, .max_opcode_byte_size: 4, .machine: llvm::Triple::sparcv9,
206 .core: ArchSpec::eCore_sparc9_generic, .name: "sparcv9"},
207
208 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 1, .max_opcode_byte_size: 15, .machine: llvm::Triple::x86, .core: ArchSpec::eCore_x86_32_i386,
209 .name: "i386"},
210 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 1, .max_opcode_byte_size: 15, .machine: llvm::Triple::x86, .core: ArchSpec::eCore_x86_32_i486,
211 .name: "i486"},
212 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 1, .max_opcode_byte_size: 15, .machine: llvm::Triple::x86,
213 .core: ArchSpec::eCore_x86_32_i486sx, .name: "i486sx"},
214 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 1, .max_opcode_byte_size: 15, .machine: llvm::Triple::x86, .core: ArchSpec::eCore_x86_32_i686,
215 .name: "i686"},
216
217 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 8, .min_opcode_byte_size: 1, .max_opcode_byte_size: 15, .machine: llvm::Triple::x86_64,
218 .core: ArchSpec::eCore_x86_64_x86_64, .name: "x86_64"},
219 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 8, .min_opcode_byte_size: 1, .max_opcode_byte_size: 15, .machine: llvm::Triple::x86_64,
220 .core: ArchSpec::eCore_x86_64_x86_64h, .name: "x86_64h"},
221 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 8, .min_opcode_byte_size: 1, .max_opcode_byte_size: 15, .machine: llvm::Triple::x86_64,
222 .core: ArchSpec::eCore_x86_64_amd64, .name: "amd64"},
223
224 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 4, .max_opcode_byte_size: 4, .machine: llvm::Triple::hexagon,
225 .core: ArchSpec::eCore_hexagon_generic, .name: "hexagon"},
226 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 4, .max_opcode_byte_size: 4, .machine: llvm::Triple::hexagon,
227 .core: ArchSpec::eCore_hexagon_hexagonv4, .name: "hexagonv4"},
228 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 4, .max_opcode_byte_size: 4, .machine: llvm::Triple::hexagon,
229 .core: ArchSpec::eCore_hexagon_hexagonv5, .name: "hexagonv5"},
230
231 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::riscv32, .core: ArchSpec::eCore_riscv32,
232 .name: "riscv32"},
233 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 8, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::riscv64, .core: ArchSpec::eCore_riscv64,
234 .name: "riscv64"},
235
236 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 4, .max_opcode_byte_size: 4, .machine: llvm::Triple::loongarch32,
237 .core: ArchSpec::eCore_loongarch32, .name: "loongarch32"},
238 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 8, .min_opcode_byte_size: 4, .max_opcode_byte_size: 4, .machine: llvm::Triple::loongarch64,
239 .core: ArchSpec::eCore_loongarch64, .name: "loongarch64"},
240
241 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 4, .max_opcode_byte_size: 4, .machine: llvm::Triple::UnknownArch,
242 .core: ArchSpec::eCore_uknownMach32, .name: "unknown-mach-32"},
243 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 8, .min_opcode_byte_size: 4, .max_opcode_byte_size: 4, .machine: llvm::Triple::UnknownArch,
244 .core: ArchSpec::eCore_uknownMach64, .name: "unknown-mach-64"},
245 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::arc, .core: ArchSpec::eCore_arc, .name: "arc"},
246
247 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 2, .min_opcode_byte_size: 2, .max_opcode_byte_size: 4, .machine: llvm::Triple::avr, .core: ArchSpec::eCore_avr, .name: "avr"},
248
249 {.default_byte_order: eByteOrderLittle, .addr_byte_size: 4, .min_opcode_byte_size: 1, .max_opcode_byte_size: 4, .machine: llvm::Triple::wasm32, .core: ArchSpec::eCore_wasm32,
250 .name: "wasm32"},
251};
252
253// Ensure that we have an entry in the g_core_definitions for each core. If you
254// comment out an entry above, you will need to comment out the corresponding
255// ArchSpec::Core enumeration.
256static_assert(sizeof(g_core_definitions) / sizeof(CoreDefinition) ==
257 ArchSpec::kNumCores,
258 "make sure we have one core definition for each core");
259
260struct ArchDefinitionEntry {
261 ArchSpec::Core core;
262 uint32_t cpu;
263 uint32_t sub;
264 uint32_t cpu_mask;
265 uint32_t sub_mask;
266};
267
268struct ArchDefinition {
269 ArchitectureType type;
270 size_t num_entries;
271 const ArchDefinitionEntry *entries;
272 const char *name;
273};
274
275void ArchSpec::ListSupportedArchNames(StringList &list) {
276 for (const auto &def : g_core_definitions)
277 list.AppendString(str: def.name);
278}
279
280void ArchSpec::AutoComplete(CompletionRequest &request) {
281 for (const auto &def : g_core_definitions)
282 request.TryCompleteCurrentArg(completion: def.name);
283}
284
285#define CPU_ANY (UINT32_MAX)
286
287//===----------------------------------------------------------------------===//
288// A table that gets searched linearly for matches. This table is used to
289// convert cpu type and subtypes to architecture names, and to convert
290// architecture names to cpu types and subtypes. The ordering is important and
291// allows the precedence to be set when the table is built.
292#define SUBTYPE_MASK 0x00FFFFFFu
293
294// clang-format off
295static const ArchDefinitionEntry g_macho_arch_entries[] = {
296 {.core: ArchSpec::eCore_arm_generic, .cpu: llvm::MachO::CPU_TYPE_ARM, CPU_ANY, UINT32_MAX, UINT32_MAX},
297 {.core: ArchSpec::eCore_arm_generic, .cpu: llvm::MachO::CPU_TYPE_ARM, .sub: llvm::MachO::CPU_SUBTYPE_ARM_ALL, UINT32_MAX, SUBTYPE_MASK},
298 {.core: ArchSpec::eCore_arm_armv4, .cpu: llvm::MachO::CPU_TYPE_ARM, .sub: llvm::MachO::CPU_SUBTYPE_ARM_V4T, UINT32_MAX, SUBTYPE_MASK},
299 {.core: ArchSpec::eCore_arm_armv4t, .cpu: llvm::MachO::CPU_TYPE_ARM, .sub: llvm::MachO::CPU_SUBTYPE_ARM_V4T, UINT32_MAX, SUBTYPE_MASK},
300 {.core: ArchSpec::eCore_arm_armv6, .cpu: llvm::MachO::CPU_TYPE_ARM, .sub: llvm::MachO::CPU_SUBTYPE_ARM_V6, UINT32_MAX, SUBTYPE_MASK},
301 {.core: ArchSpec::eCore_arm_armv6m, .cpu: llvm::MachO::CPU_TYPE_ARM, .sub: llvm::MachO::CPU_SUBTYPE_ARM_V6M, UINT32_MAX, SUBTYPE_MASK},
302 {.core: ArchSpec::eCore_arm_armv5, .cpu: llvm::MachO::CPU_TYPE_ARM, .sub: llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ, UINT32_MAX, SUBTYPE_MASK},
303 {.core: ArchSpec::eCore_arm_armv5e, .cpu: llvm::MachO::CPU_TYPE_ARM, .sub: llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ, UINT32_MAX, SUBTYPE_MASK},
304 {.core: ArchSpec::eCore_arm_armv5t, .cpu: llvm::MachO::CPU_TYPE_ARM, .sub: llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ, UINT32_MAX, SUBTYPE_MASK},
305 {.core: ArchSpec::eCore_arm_xscale, .cpu: llvm::MachO::CPU_TYPE_ARM, .sub: llvm::MachO::CPU_SUBTYPE_ARM_XSCALE, UINT32_MAX, SUBTYPE_MASK},
306 {.core: ArchSpec::eCore_arm_armv7, .cpu: llvm::MachO::CPU_TYPE_ARM, .sub: llvm::MachO::CPU_SUBTYPE_ARM_V7, UINT32_MAX, SUBTYPE_MASK},
307 {.core: ArchSpec::eCore_arm_armv7f, .cpu: llvm::MachO::CPU_TYPE_ARM, .sub: 10, UINT32_MAX, SUBTYPE_MASK},
308 {.core: ArchSpec::eCore_arm_armv7s, .cpu: llvm::MachO::CPU_TYPE_ARM, .sub: llvm::MachO::CPU_SUBTYPE_ARM_V7S, UINT32_MAX, SUBTYPE_MASK},
309 {.core: ArchSpec::eCore_arm_armv7k, .cpu: llvm::MachO::CPU_TYPE_ARM, .sub: llvm::MachO::CPU_SUBTYPE_ARM_V7K, UINT32_MAX, SUBTYPE_MASK},
310 {.core: ArchSpec::eCore_arm_armv7m, .cpu: llvm::MachO::CPU_TYPE_ARM, .sub: llvm::MachO::CPU_SUBTYPE_ARM_V7M, UINT32_MAX, SUBTYPE_MASK},
311 {.core: ArchSpec::eCore_arm_armv7em, .cpu: llvm::MachO::CPU_TYPE_ARM, .sub: llvm::MachO::CPU_SUBTYPE_ARM_V7EM, UINT32_MAX, SUBTYPE_MASK},
312 {.core: ArchSpec::eCore_arm_arm64e, .cpu: llvm::MachO::CPU_TYPE_ARM64, .sub: llvm::MachO::CPU_SUBTYPE_ARM64E, UINT32_MAX, SUBTYPE_MASK},
313 {.core: ArchSpec::eCore_arm_arm64, .cpu: llvm::MachO::CPU_TYPE_ARM64, .sub: llvm::MachO::CPU_SUBTYPE_ARM64_ALL, UINT32_MAX, SUBTYPE_MASK},
314 {.core: ArchSpec::eCore_arm_arm64, .cpu: llvm::MachO::CPU_TYPE_ARM64, .sub: llvm::MachO::CPU_SUBTYPE_ARM64_V8, UINT32_MAX, SUBTYPE_MASK},
315 {.core: ArchSpec::eCore_arm_arm64, .cpu: llvm::MachO::CPU_TYPE_ARM64, .sub: 13, UINT32_MAX, SUBTYPE_MASK},
316 {.core: ArchSpec::eCore_arm_arm64_32, .cpu: llvm::MachO::CPU_TYPE_ARM64_32, .sub: 0, UINT32_MAX, SUBTYPE_MASK},
317 {.core: ArchSpec::eCore_arm_arm64_32, .cpu: llvm::MachO::CPU_TYPE_ARM64_32, .sub: 1, UINT32_MAX, SUBTYPE_MASK},
318 {.core: ArchSpec::eCore_arm_arm64, .cpu: llvm::MachO::CPU_TYPE_ARM64, CPU_ANY, UINT32_MAX, SUBTYPE_MASK},
319 {.core: ArchSpec::eCore_thumb, .cpu: llvm::MachO::CPU_TYPE_ARM, .sub: llvm::MachO::CPU_SUBTYPE_ARM_ALL, UINT32_MAX, SUBTYPE_MASK},
320 {.core: ArchSpec::eCore_thumbv4t, .cpu: llvm::MachO::CPU_TYPE_ARM, .sub: llvm::MachO::CPU_SUBTYPE_ARM_V4T, UINT32_MAX, SUBTYPE_MASK},
321 {.core: ArchSpec::eCore_thumbv5, .cpu: llvm::MachO::CPU_TYPE_ARM, .sub: llvm::MachO::CPU_SUBTYPE_ARM_V5, UINT32_MAX, SUBTYPE_MASK},
322 {.core: ArchSpec::eCore_thumbv5e, .cpu: llvm::MachO::CPU_TYPE_ARM, .sub: llvm::MachO::CPU_SUBTYPE_ARM_V5, UINT32_MAX, SUBTYPE_MASK},
323 {.core: ArchSpec::eCore_thumbv6, .cpu: llvm::MachO::CPU_TYPE_ARM, .sub: llvm::MachO::CPU_SUBTYPE_ARM_V6, UINT32_MAX, SUBTYPE_MASK},
324 {.core: ArchSpec::eCore_thumbv6m, .cpu: llvm::MachO::CPU_TYPE_ARM, .sub: llvm::MachO::CPU_SUBTYPE_ARM_V6M, UINT32_MAX, SUBTYPE_MASK},
325 {.core: ArchSpec::eCore_thumbv7, .cpu: llvm::MachO::CPU_TYPE_ARM, .sub: llvm::MachO::CPU_SUBTYPE_ARM_V7, UINT32_MAX, SUBTYPE_MASK},
326 {.core: ArchSpec::eCore_thumbv7f, .cpu: llvm::MachO::CPU_TYPE_ARM, .sub: 10, UINT32_MAX, SUBTYPE_MASK},
327 {.core: ArchSpec::eCore_thumbv7s, .cpu: llvm::MachO::CPU_TYPE_ARM, .sub: llvm::MachO::CPU_SUBTYPE_ARM_V7S, UINT32_MAX, SUBTYPE_MASK},
328 {.core: ArchSpec::eCore_thumbv7k, .cpu: llvm::MachO::CPU_TYPE_ARM, .sub: llvm::MachO::CPU_SUBTYPE_ARM_V7K, UINT32_MAX, SUBTYPE_MASK},
329 {.core: ArchSpec::eCore_thumbv7m, .cpu: llvm::MachO::CPU_TYPE_ARM, .sub: llvm::MachO::CPU_SUBTYPE_ARM_V7M, UINT32_MAX, SUBTYPE_MASK},
330 {.core: ArchSpec::eCore_thumbv7em, .cpu: llvm::MachO::CPU_TYPE_ARM, .sub: llvm::MachO::CPU_SUBTYPE_ARM_V7EM, UINT32_MAX, SUBTYPE_MASK},
331 {.core: ArchSpec::eCore_ppc_generic, .cpu: llvm::MachO::CPU_TYPE_POWERPC, CPU_ANY, UINT32_MAX, UINT32_MAX},
332 {.core: ArchSpec::eCore_ppc_generic, .cpu: llvm::MachO::CPU_TYPE_POWERPC, .sub: llvm::MachO::CPU_SUBTYPE_POWERPC_ALL, UINT32_MAX, SUBTYPE_MASK},
333 {.core: ArchSpec::eCore_ppc_ppc601, .cpu: llvm::MachO::CPU_TYPE_POWERPC, .sub: llvm::MachO::CPU_SUBTYPE_POWERPC_601, UINT32_MAX, SUBTYPE_MASK},
334 {.core: ArchSpec::eCore_ppc_ppc602, .cpu: llvm::MachO::CPU_TYPE_POWERPC, .sub: llvm::MachO::CPU_SUBTYPE_POWERPC_602, UINT32_MAX, SUBTYPE_MASK},
335 {.core: ArchSpec::eCore_ppc_ppc603, .cpu: llvm::MachO::CPU_TYPE_POWERPC, .sub: llvm::MachO::CPU_SUBTYPE_POWERPC_603, UINT32_MAX, SUBTYPE_MASK},
336 {.core: ArchSpec::eCore_ppc_ppc603e, .cpu: llvm::MachO::CPU_TYPE_POWERPC, .sub: llvm::MachO::CPU_SUBTYPE_POWERPC_603e, UINT32_MAX, SUBTYPE_MASK},
337 {.core: ArchSpec::eCore_ppc_ppc603ev, .cpu: llvm::MachO::CPU_TYPE_POWERPC, .sub: llvm::MachO::CPU_SUBTYPE_POWERPC_603ev, UINT32_MAX, SUBTYPE_MASK},
338 {.core: ArchSpec::eCore_ppc_ppc604, .cpu: llvm::MachO::CPU_TYPE_POWERPC, .sub: llvm::MachO::CPU_SUBTYPE_POWERPC_604, UINT32_MAX, SUBTYPE_MASK},
339 {.core: ArchSpec::eCore_ppc_ppc604e, .cpu: llvm::MachO::CPU_TYPE_POWERPC, .sub: llvm::MachO::CPU_SUBTYPE_POWERPC_604e, UINT32_MAX, SUBTYPE_MASK},
340 {.core: ArchSpec::eCore_ppc_ppc620, .cpu: llvm::MachO::CPU_TYPE_POWERPC, .sub: llvm::MachO::CPU_SUBTYPE_POWERPC_620, UINT32_MAX, SUBTYPE_MASK},
341 {.core: ArchSpec::eCore_ppc_ppc750, .cpu: llvm::MachO::CPU_TYPE_POWERPC, .sub: llvm::MachO::CPU_SUBTYPE_POWERPC_750, UINT32_MAX, SUBTYPE_MASK},
342 {.core: ArchSpec::eCore_ppc_ppc7400, .cpu: llvm::MachO::CPU_TYPE_POWERPC, .sub: llvm::MachO::CPU_SUBTYPE_POWERPC_7400, UINT32_MAX, SUBTYPE_MASK},
343 {.core: ArchSpec::eCore_ppc_ppc7450, .cpu: llvm::MachO::CPU_TYPE_POWERPC, .sub: llvm::MachO::CPU_SUBTYPE_POWERPC_7450, UINT32_MAX, SUBTYPE_MASK},
344 {.core: ArchSpec::eCore_ppc_ppc970, .cpu: llvm::MachO::CPU_TYPE_POWERPC, .sub: llvm::MachO::CPU_SUBTYPE_POWERPC_970, UINT32_MAX, SUBTYPE_MASK},
345 {.core: ArchSpec::eCore_ppc64_generic, .cpu: llvm::MachO::CPU_TYPE_POWERPC64, .sub: llvm::MachO::CPU_SUBTYPE_POWERPC_ALL, UINT32_MAX, SUBTYPE_MASK},
346 {.core: ArchSpec::eCore_ppc64le_generic, .cpu: llvm::MachO::CPU_TYPE_POWERPC64, CPU_ANY, UINT32_MAX, SUBTYPE_MASK},
347 {.core: ArchSpec::eCore_ppc64_ppc970_64, .cpu: llvm::MachO::CPU_TYPE_POWERPC64, .sub: 100, UINT32_MAX, SUBTYPE_MASK},
348 {.core: ArchSpec::eCore_x86_32_i386, .cpu: llvm::MachO::CPU_TYPE_I386, .sub: llvm::MachO::CPU_SUBTYPE_I386_ALL, UINT32_MAX, SUBTYPE_MASK},
349 {.core: ArchSpec::eCore_x86_32_i486, .cpu: llvm::MachO::CPU_TYPE_I386, .sub: llvm::MachO::CPU_SUBTYPE_486, UINT32_MAX, SUBTYPE_MASK},
350 {.core: ArchSpec::eCore_x86_32_i486sx, .cpu: llvm::MachO::CPU_TYPE_I386, .sub: llvm::MachO::CPU_SUBTYPE_486SX, UINT32_MAX, SUBTYPE_MASK},
351 {.core: ArchSpec::eCore_x86_32_i386, .cpu: llvm::MachO::CPU_TYPE_I386, CPU_ANY, UINT32_MAX, UINT32_MAX},
352 {.core: ArchSpec::eCore_x86_64_x86_64, .cpu: llvm::MachO::CPU_TYPE_X86_64, .sub: llvm::MachO::CPU_SUBTYPE_X86_64_ALL, UINT32_MAX, SUBTYPE_MASK},
353 {.core: ArchSpec::eCore_x86_64_x86_64, .cpu: llvm::MachO::CPU_TYPE_X86_64, .sub: llvm::MachO::CPU_SUBTYPE_X86_ARCH1, UINT32_MAX, SUBTYPE_MASK},
354 {.core: ArchSpec::eCore_x86_64_x86_64h, .cpu: llvm::MachO::CPU_TYPE_X86_64, .sub: llvm::MachO::CPU_SUBTYPE_X86_64_H, UINT32_MAX, SUBTYPE_MASK},
355 {.core: ArchSpec::eCore_x86_64_x86_64, .cpu: llvm::MachO::CPU_TYPE_X86_64, CPU_ANY, UINT32_MAX, UINT32_MAX},
356 {.core: ArchSpec::eCore_riscv32, .cpu: llvm::MachO::CPU_TYPE_RISCV, .sub: llvm::MachO::CPU_SUBTYPE_RISCV_ALL, UINT32_MAX, SUBTYPE_MASK},
357 {.core: ArchSpec::eCore_riscv32, .cpu: llvm::MachO::CPU_TYPE_RISCV, CPU_ANY, UINT32_MAX, SUBTYPE_MASK},
358 // Catch any unknown mach architectures so we can always use the object and symbol mach-o files
359 {.core: ArchSpec::eCore_uknownMach32, .cpu: 0, .sub: 0, .cpu_mask: 0xFF000000u, .sub_mask: 0x00000000u},
360 {.core: ArchSpec::eCore_uknownMach64, .cpu: llvm::MachO::CPU_ARCH_ABI64, .sub: 0, .cpu_mask: 0xFF000000u, .sub_mask: 0x00000000u}};
361// clang-format on
362
363static const ArchDefinition g_macho_arch_def = {.type: eArchTypeMachO,
364 .num_entries: std::size(g_macho_arch_entries),
365 .entries: g_macho_arch_entries, .name: "mach-o"};
366
367//===----------------------------------------------------------------------===//
368// A table that gets searched linearly for matches. This table is used to
369// convert cpu type and subtypes to architecture names, and to convert
370// architecture names to cpu types and subtypes. The ordering is important and
371// allows the precedence to be set when the table is built.
372static const ArchDefinitionEntry g_elf_arch_entries[] = {
373 {.core: ArchSpec::eCore_sparc_generic, .cpu: llvm::ELF::EM_SPARC, LLDB_INVALID_CPUTYPE,
374 .cpu_mask: 0xFFFFFFFFu, .sub_mask: 0xFFFFFFFFu}, // Sparc
375 {.core: ArchSpec::eCore_x86_32_i386, .cpu: llvm::ELF::EM_386, LLDB_INVALID_CPUTYPE,
376 .cpu_mask: 0xFFFFFFFFu, .sub_mask: 0xFFFFFFFFu}, // Intel 80386
377 {.core: ArchSpec::eCore_x86_32_i486, .cpu: llvm::ELF::EM_IAMCU, LLDB_INVALID_CPUTYPE,
378 .cpu_mask: 0xFFFFFFFFu, .sub_mask: 0xFFFFFFFFu}, // Intel MCU // FIXME: is this correct?
379 {.core: ArchSpec::eCore_ppc_generic, .cpu: llvm::ELF::EM_PPC, LLDB_INVALID_CPUTYPE,
380 .cpu_mask: 0xFFFFFFFFu, .sub_mask: 0xFFFFFFFFu}, // PowerPC
381 {.core: ArchSpec::eCore_ppc64le_generic, .cpu: llvm::ELF::EM_PPC64,
382 .sub: ArchSpec::eCore_ppc64le_generic, .cpu_mask: 0xFFFFFFFFu, .sub_mask: 0xFFFFFFFFu}, // PowerPC64le
383 {.core: ArchSpec::eCore_ppc64_generic, .cpu: llvm::ELF::EM_PPC64,
384 .sub: ArchSpec::eCore_ppc64_generic, .cpu_mask: 0xFFFFFFFFu, .sub_mask: 0xFFFFFFFFu}, // PowerPC64
385 {.core: ArchSpec::eCore_arm_generic, .cpu: llvm::ELF::EM_ARM, LLDB_INVALID_CPUTYPE,
386 .cpu_mask: 0xFFFFFFFFu, .sub_mask: 0xFFFFFFFFu}, // ARM
387 {.core: ArchSpec::eCore_arm_aarch64, .cpu: llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE,
388 .cpu_mask: 0xFFFFFFFFu, .sub_mask: 0xFFFFFFFFu}, // ARM64
389 {.core: ArchSpec::eCore_s390x_generic, .cpu: llvm::ELF::EM_S390, LLDB_INVALID_CPUTYPE,
390 .cpu_mask: 0xFFFFFFFFu, .sub_mask: 0xFFFFFFFFu}, // SystemZ
391 {.core: ArchSpec::eCore_sparc9_generic, .cpu: llvm::ELF::EM_SPARCV9,
392 LLDB_INVALID_CPUTYPE, .cpu_mask: 0xFFFFFFFFu, .sub_mask: 0xFFFFFFFFu}, // SPARC V9
393 {.core: ArchSpec::eCore_x86_64_x86_64, .cpu: llvm::ELF::EM_X86_64, LLDB_INVALID_CPUTYPE,
394 .cpu_mask: 0xFFFFFFFFu, .sub_mask: 0xFFFFFFFFu}, // AMD64
395 {.core: ArchSpec::eCore_mips32, .cpu: llvm::ELF::EM_MIPS, .sub: ArchSpec::eMIPSSubType_mips32,
396 .cpu_mask: 0xFFFFFFFFu, .sub_mask: 0xFFFFFFFFu}, // mips32
397 {.core: ArchSpec::eCore_mips32r2, .cpu: llvm::ELF::EM_MIPS,
398 .sub: ArchSpec::eMIPSSubType_mips32r2, .cpu_mask: 0xFFFFFFFFu, .sub_mask: 0xFFFFFFFFu}, // mips32r2
399 {.core: ArchSpec::eCore_mips32r6, .cpu: llvm::ELF::EM_MIPS,
400 .sub: ArchSpec::eMIPSSubType_mips32r6, .cpu_mask: 0xFFFFFFFFu, .sub_mask: 0xFFFFFFFFu}, // mips32r6
401 {.core: ArchSpec::eCore_mips32el, .cpu: llvm::ELF::EM_MIPS,
402 .sub: ArchSpec::eMIPSSubType_mips32el, .cpu_mask: 0xFFFFFFFFu, .sub_mask: 0xFFFFFFFFu}, // mips32el
403 {.core: ArchSpec::eCore_mips32r2el, .cpu: llvm::ELF::EM_MIPS,
404 .sub: ArchSpec::eMIPSSubType_mips32r2el, .cpu_mask: 0xFFFFFFFFu, .sub_mask: 0xFFFFFFFFu}, // mips32r2el
405 {.core: ArchSpec::eCore_mips32r6el, .cpu: llvm::ELF::EM_MIPS,
406 .sub: ArchSpec::eMIPSSubType_mips32r6el, .cpu_mask: 0xFFFFFFFFu, .sub_mask: 0xFFFFFFFFu}, // mips32r6el
407 {.core: ArchSpec::eCore_mips64, .cpu: llvm::ELF::EM_MIPS, .sub: ArchSpec::eMIPSSubType_mips64,
408 .cpu_mask: 0xFFFFFFFFu, .sub_mask: 0xFFFFFFFFu}, // mips64
409 {.core: ArchSpec::eCore_mips64r2, .cpu: llvm::ELF::EM_MIPS,
410 .sub: ArchSpec::eMIPSSubType_mips64r2, .cpu_mask: 0xFFFFFFFFu, .sub_mask: 0xFFFFFFFFu}, // mips64r2
411 {.core: ArchSpec::eCore_mips64r6, .cpu: llvm::ELF::EM_MIPS,
412 .sub: ArchSpec::eMIPSSubType_mips64r6, .cpu_mask: 0xFFFFFFFFu, .sub_mask: 0xFFFFFFFFu}, // mips64r6
413 {.core: ArchSpec::eCore_mips64el, .cpu: llvm::ELF::EM_MIPS,
414 .sub: ArchSpec::eMIPSSubType_mips64el, .cpu_mask: 0xFFFFFFFFu, .sub_mask: 0xFFFFFFFFu}, // mips64el
415 {.core: ArchSpec::eCore_mips64r2el, .cpu: llvm::ELF::EM_MIPS,
416 .sub: ArchSpec::eMIPSSubType_mips64r2el, .cpu_mask: 0xFFFFFFFFu, .sub_mask: 0xFFFFFFFFu}, // mips64r2el
417 {.core: ArchSpec::eCore_mips64r6el, .cpu: llvm::ELF::EM_MIPS,
418 .sub: ArchSpec::eMIPSSubType_mips64r6el, .cpu_mask: 0xFFFFFFFFu, .sub_mask: 0xFFFFFFFFu}, // mips64r6el
419 {.core: ArchSpec::eCore_msp430, .cpu: llvm::ELF::EM_MSP430, LLDB_INVALID_CPUTYPE,
420 .cpu_mask: 0xFFFFFFFFu, .sub_mask: 0xFFFFFFFFu}, // MSP430
421 {.core: ArchSpec::eCore_hexagon_generic, .cpu: llvm::ELF::EM_HEXAGON,
422 LLDB_INVALID_CPUTYPE, .cpu_mask: 0xFFFFFFFFu, .sub_mask: 0xFFFFFFFFu}, // HEXAGON
423 {.core: ArchSpec::eCore_arc, .cpu: llvm::ELF::EM_ARC_COMPACT2, LLDB_INVALID_CPUTYPE,
424 .cpu_mask: 0xFFFFFFFFu, .sub_mask: 0xFFFFFFFFu}, // ARC
425 {.core: ArchSpec::eCore_avr, .cpu: llvm::ELF::EM_AVR, LLDB_INVALID_CPUTYPE, .cpu_mask: 0xFFFFFFFFu,
426 .sub_mask: 0xFFFFFFFFu}, // AVR
427 {.core: ArchSpec::eCore_riscv32, .cpu: llvm::ELF::EM_RISCV,
428 .sub: ArchSpec::eRISCVSubType_riscv32, .cpu_mask: 0xFFFFFFFFu, .sub_mask: 0xFFFFFFFFu}, // riscv32
429 {.core: ArchSpec::eCore_riscv64, .cpu: llvm::ELF::EM_RISCV,
430 .sub: ArchSpec::eRISCVSubType_riscv64, .cpu_mask: 0xFFFFFFFFu, .sub_mask: 0xFFFFFFFFu}, // riscv64
431 {.core: ArchSpec::eCore_loongarch32, .cpu: llvm::ELF::EM_LOONGARCH,
432 .sub: ArchSpec::eLoongArchSubType_loongarch32, .cpu_mask: 0xFFFFFFFFu,
433 .sub_mask: 0xFFFFFFFFu}, // loongarch32
434 {.core: ArchSpec::eCore_loongarch64, .cpu: llvm::ELF::EM_LOONGARCH,
435 .sub: ArchSpec::eLoongArchSubType_loongarch64, .cpu_mask: 0xFFFFFFFFu,
436 .sub_mask: 0xFFFFFFFFu}, // loongarch64
437};
438
439static const ArchDefinition g_elf_arch_def = {
440 .type: eArchTypeELF,
441 .num_entries: std::size(g_elf_arch_entries),
442 .entries: g_elf_arch_entries,
443 .name: "elf",
444};
445
446static const ArchDefinitionEntry g_coff_arch_entries[] = {
447 {.core: ArchSpec::eCore_x86_32_i386, .cpu: llvm::COFF::IMAGE_FILE_MACHINE_I386,
448 LLDB_INVALID_CPUTYPE, .cpu_mask: 0xFFFFFFFFu, .sub_mask: 0xFFFFFFFFu}, // Intel 80x86
449 {.core: ArchSpec::eCore_ppc_generic, .cpu: llvm::COFF::IMAGE_FILE_MACHINE_POWERPC,
450 LLDB_INVALID_CPUTYPE, .cpu_mask: 0xFFFFFFFFu, .sub_mask: 0xFFFFFFFFu}, // PowerPC
451 {.core: ArchSpec::eCore_ppc_generic, .cpu: llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP,
452 LLDB_INVALID_CPUTYPE, .cpu_mask: 0xFFFFFFFFu, .sub_mask: 0xFFFFFFFFu}, // PowerPC (with FPU)
453 {.core: ArchSpec::eCore_arm_generic, .cpu: llvm::COFF::IMAGE_FILE_MACHINE_ARM,
454 LLDB_INVALID_CPUTYPE, .cpu_mask: 0xFFFFFFFFu, .sub_mask: 0xFFFFFFFFu}, // ARM
455 {.core: ArchSpec::eCore_arm_armv7, .cpu: llvm::COFF::IMAGE_FILE_MACHINE_ARMNT,
456 LLDB_INVALID_CPUTYPE, .cpu_mask: 0xFFFFFFFFu, .sub_mask: 0xFFFFFFFFu}, // ARMv7
457 {.core: ArchSpec::eCore_thumb, .cpu: llvm::COFF::IMAGE_FILE_MACHINE_THUMB,
458 LLDB_INVALID_CPUTYPE, .cpu_mask: 0xFFFFFFFFu, .sub_mask: 0xFFFFFFFFu}, // ARMv7
459 {.core: ArchSpec::eCore_x86_64_x86_64, .cpu: llvm::COFF::IMAGE_FILE_MACHINE_AMD64,
460 LLDB_INVALID_CPUTYPE, .cpu_mask: 0xFFFFFFFFu, .sub_mask: 0xFFFFFFFFu}, // AMD64
461 {.core: ArchSpec::eCore_arm_arm64, .cpu: llvm::COFF::IMAGE_FILE_MACHINE_ARM64,
462 LLDB_INVALID_CPUTYPE, .cpu_mask: 0xFFFFFFFFu, .sub_mask: 0xFFFFFFFFu} // ARM64
463};
464
465static const ArchDefinition g_coff_arch_def = {
466 .type: eArchTypeCOFF,
467 .num_entries: std::size(g_coff_arch_entries),
468 .entries: g_coff_arch_entries,
469 .name: "pe-coff",
470};
471
472static const ArchDefinitionEntry g_xcoff_arch_entries[] = {
473 {.core: ArchSpec::eCore_ppc_generic, .cpu: llvm::XCOFF::TCPU_COM, LLDB_INVALID_CPUTYPE,
474 .cpu_mask: 0xFFFFFFFFu, .sub_mask: 0xFFFFFFFFu},
475 {.core: ArchSpec::eCore_ppc64_generic, .cpu: llvm::XCOFF::TCPU_PPC64,
476 LLDB_INVALID_CPUTYPE, .cpu_mask: 0xFFFFFFFFu, .sub_mask: 0xFFFFFFFFu}};
477
478static const ArchDefinition g_xcoff_arch_def = {
479 .type: eArchTypeXCOFF,
480 .num_entries: std::size(g_xcoff_arch_entries),
481 .entries: g_xcoff_arch_entries,
482 .name: "xcoff",
483};
484
485//===----------------------------------------------------------------------===//
486// Table of all ArchDefinitions
487static const ArchDefinition *g_arch_definitions[] = {
488 &g_macho_arch_def, &g_elf_arch_def, &g_coff_arch_def, &g_xcoff_arch_def};
489
490//===----------------------------------------------------------------------===//
491// Static helper functions.
492
493// Get the architecture definition for a given object type.
494static const ArchDefinition *FindArchDefinition(ArchitectureType arch_type) {
495 for (const ArchDefinition *def : g_arch_definitions) {
496 if (def->type == arch_type)
497 return def;
498 }
499 return nullptr;
500}
501
502// Get an architecture definition by name.
503static const CoreDefinition *FindCoreDefinition(llvm::StringRef name) {
504 for (const auto &def : g_core_definitions) {
505 if (name.equals_insensitive(RHS: def.name))
506 return &def;
507 }
508 return nullptr;
509}
510
511static inline const CoreDefinition *FindCoreDefinition(ArchSpec::Core core) {
512 if (core < std::size(g_core_definitions))
513 return &g_core_definitions[core];
514 return nullptr;
515}
516
517// Get a definition entry by cpu type and subtype.
518static const ArchDefinitionEntry *
519FindArchDefinitionEntry(const ArchDefinition *def, uint32_t cpu, uint32_t sub) {
520 if (def == nullptr)
521 return nullptr;
522
523 const ArchDefinitionEntry *entries = def->entries;
524 for (size_t i = 0; i < def->num_entries; ++i) {
525 if (entries[i].cpu == (cpu & entries[i].cpu_mask))
526 if (entries[i].sub == (sub & entries[i].sub_mask))
527 return &entries[i];
528 }
529 return nullptr;
530}
531
532static const ArchDefinitionEntry *
533FindArchDefinitionEntry(const ArchDefinition *def, ArchSpec::Core core) {
534 if (def == nullptr)
535 return nullptr;
536
537 const ArchDefinitionEntry *entries = def->entries;
538 for (size_t i = 0; i < def->num_entries; ++i) {
539 if (entries[i].core == core)
540 return &entries[i];
541 }
542 return nullptr;
543}
544
545//===----------------------------------------------------------------------===//
546// Constructors and destructors.
547
548ArchSpec::ArchSpec() = default;
549
550ArchSpec::ArchSpec(const char *triple_cstr) {
551 if (triple_cstr)
552 SetTriple(triple_cstr);
553}
554
555ArchSpec::ArchSpec(llvm::StringRef triple_str) { SetTriple(triple_str); }
556
557ArchSpec::ArchSpec(const llvm::Triple &triple) { SetTriple(triple); }
558
559ArchSpec::ArchSpec(ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) {
560 SetArchitecture(arch_type, cpu, sub: subtype);
561}
562
563ArchSpec::~ArchSpec() = default;
564
565void ArchSpec::Clear() {
566 m_triple = llvm::Triple();
567 m_core = kCore_invalid;
568 m_byte_order = eByteOrderInvalid;
569 m_flags = 0;
570}
571
572//===----------------------------------------------------------------------===//
573// Predicates.
574
575const char *ArchSpec::GetArchitectureName() const {
576 const CoreDefinition *core_def = FindCoreDefinition(core: m_core);
577 if (core_def)
578 return core_def->name;
579 return "unknown";
580}
581
582bool ArchSpec::IsMIPS() const { return GetTriple().isMIPS(); }
583
584std::string ArchSpec::GetTargetABI() const {
585
586 std::string abi;
587
588 if (IsMIPS()) {
589 switch (GetFlags() & ArchSpec::eMIPSABI_mask) {
590 case ArchSpec::eMIPSABI_N64:
591 abi = "n64";
592 return abi;
593 case ArchSpec::eMIPSABI_N32:
594 abi = "n32";
595 return abi;
596 case ArchSpec::eMIPSABI_O32:
597 abi = "o32";
598 return abi;
599 default:
600 return abi;
601 }
602 }
603 return abi;
604}
605
606void ArchSpec::SetFlags(const std::string &elf_abi) {
607
608 uint32_t flag = GetFlags();
609 if (IsMIPS()) {
610 if (elf_abi == "n64")
611 flag |= ArchSpec::eMIPSABI_N64;
612 else if (elf_abi == "n32")
613 flag |= ArchSpec::eMIPSABI_N32;
614 else if (elf_abi == "o32")
615 flag |= ArchSpec::eMIPSABI_O32;
616 }
617 SetFlags(flag);
618}
619
620std::string ArchSpec::GetClangTargetCPU() const {
621 std::string cpu;
622 if (IsMIPS()) {
623 switch (m_core) {
624 case ArchSpec::eCore_mips32:
625 case ArchSpec::eCore_mips32el:
626 cpu = "mips32";
627 break;
628 case ArchSpec::eCore_mips32r2:
629 case ArchSpec::eCore_mips32r2el:
630 cpu = "mips32r2";
631 break;
632 case ArchSpec::eCore_mips32r3:
633 case ArchSpec::eCore_mips32r3el:
634 cpu = "mips32r3";
635 break;
636 case ArchSpec::eCore_mips32r5:
637 case ArchSpec::eCore_mips32r5el:
638 cpu = "mips32r5";
639 break;
640 case ArchSpec::eCore_mips32r6:
641 case ArchSpec::eCore_mips32r6el:
642 cpu = "mips32r6";
643 break;
644 case ArchSpec::eCore_mips64:
645 case ArchSpec::eCore_mips64el:
646 cpu = "mips64";
647 break;
648 case ArchSpec::eCore_mips64r2:
649 case ArchSpec::eCore_mips64r2el:
650 cpu = "mips64r2";
651 break;
652 case ArchSpec::eCore_mips64r3:
653 case ArchSpec::eCore_mips64r3el:
654 cpu = "mips64r3";
655 break;
656 case ArchSpec::eCore_mips64r5:
657 case ArchSpec::eCore_mips64r5el:
658 cpu = "mips64r5";
659 break;
660 case ArchSpec::eCore_mips64r6:
661 case ArchSpec::eCore_mips64r6el:
662 cpu = "mips64r6";
663 break;
664 default:
665 break;
666 }
667 }
668
669 if (GetTriple().isARM())
670 cpu = llvm::ARM::getARMCPUForArch(Triple: GetTriple(), MArch: "").str();
671 return cpu;
672}
673
674uint32_t ArchSpec::GetMachOCPUType() const {
675 const CoreDefinition *core_def = FindCoreDefinition(core: m_core);
676 if (core_def) {
677 const ArchDefinitionEntry *arch_def =
678 FindArchDefinitionEntry(def: &g_macho_arch_def, core: core_def->core);
679 if (arch_def) {
680 return arch_def->cpu;
681 }
682 }
683 return LLDB_INVALID_CPUTYPE;
684}
685
686uint32_t ArchSpec::GetMachOCPUSubType() const {
687 const CoreDefinition *core_def = FindCoreDefinition(core: m_core);
688 if (core_def) {
689 const ArchDefinitionEntry *arch_def =
690 FindArchDefinitionEntry(def: &g_macho_arch_def, core: core_def->core);
691 if (arch_def) {
692 return arch_def->sub;
693 }
694 }
695 return LLDB_INVALID_CPUTYPE;
696}
697
698uint32_t ArchSpec::GetDataByteSize() const {
699 return 1;
700}
701
702uint32_t ArchSpec::GetCodeByteSize() const {
703 return 1;
704}
705
706llvm::Triple::ArchType ArchSpec::GetMachine() const {
707 const CoreDefinition *core_def = FindCoreDefinition(core: m_core);
708 if (core_def)
709 return core_def->machine;
710
711 return llvm::Triple::UnknownArch;
712}
713
714uint32_t ArchSpec::GetAddressByteSize() const {
715 const CoreDefinition *core_def = FindCoreDefinition(core: m_core);
716 if (core_def) {
717 if (core_def->machine == llvm::Triple::mips64 ||
718 core_def->machine == llvm::Triple::mips64el) {
719 // For N32/O32 applications Address size is 4 bytes.
720 if (m_flags & (eMIPSABI_N32 | eMIPSABI_O32))
721 return 4;
722 }
723 return core_def->addr_byte_size;
724 }
725 return 0;
726}
727
728ByteOrder ArchSpec::GetDefaultEndian() const {
729 const CoreDefinition *core_def = FindCoreDefinition(core: m_core);
730 if (core_def)
731 return core_def->default_byte_order;
732 return eByteOrderInvalid;
733}
734
735bool ArchSpec::CharIsSignedByDefault() const {
736 switch (m_triple.getArch()) {
737 default:
738 return true;
739
740 case llvm::Triple::aarch64:
741 case llvm::Triple::aarch64_32:
742 case llvm::Triple::aarch64_be:
743 case llvm::Triple::arm:
744 case llvm::Triple::armeb:
745 case llvm::Triple::thumb:
746 case llvm::Triple::thumbeb:
747 return m_triple.isOSDarwin() || m_triple.isOSWindows();
748
749 case llvm::Triple::ppc:
750 case llvm::Triple::ppc64:
751 return m_triple.isOSDarwin();
752
753 case llvm::Triple::ppc64le:
754 case llvm::Triple::systemz:
755 case llvm::Triple::xcore:
756 case llvm::Triple::arc:
757 return false;
758 }
759}
760
761lldb::ByteOrder ArchSpec::GetByteOrder() const {
762 if (m_byte_order == eByteOrderInvalid)
763 return GetDefaultEndian();
764 return m_byte_order;
765}
766
767//===----------------------------------------------------------------------===//
768// Mutators.
769
770bool ArchSpec::SetTriple(const llvm::Triple &triple) {
771 m_triple = triple;
772 UpdateCore();
773 return IsValid();
774}
775
776bool lldb_private::ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str,
777 ArchSpec &arch) {
778 // Accept "12-10" or "12.10" as cpu type/subtype
779 if (triple_str.empty())
780 return false;
781
782 size_t pos = triple_str.find_first_of(Chars: "-.");
783 if (pos == llvm::StringRef::npos)
784 return false;
785
786 llvm::StringRef cpu_str = triple_str.substr(Start: 0, N: pos);
787 llvm::StringRef remainder = triple_str.substr(Start: pos + 1);
788 if (cpu_str.empty() || remainder.empty())
789 return false;
790
791 llvm::StringRef sub_str;
792 llvm::StringRef vendor;
793 llvm::StringRef os;
794 std::tie(args&: sub_str, args&: remainder) = remainder.split(Separator: '-');
795 std::tie(args&: vendor, args&: os) = remainder.split(Separator: '-');
796
797 uint32_t cpu = 0;
798 uint32_t sub = 0;
799 if (cpu_str.getAsInteger(Radix: 10, Result&: cpu) || sub_str.getAsInteger(Radix: 10, Result&: sub))
800 return false;
801
802 if (!arch.SetArchitecture(arch_type: eArchTypeMachO, cpu, sub))
803 return false;
804 if (!vendor.empty() && !os.empty()) {
805 arch.GetTriple().setVendorName(vendor);
806 arch.GetTriple().setOSName(os);
807 }
808
809 return true;
810}
811
812bool ArchSpec::SetTriple(llvm::StringRef triple) {
813 if (triple.empty()) {
814 Clear();
815 return false;
816 }
817
818 if (ParseMachCPUDashSubtypeTriple(triple_str: triple, arch&: *this))
819 return true;
820
821 SetTriple(llvm::Triple(llvm::Triple::normalize(Str: triple)));
822 return IsValid();
823}
824
825bool ArchSpec::ContainsOnlyArch(const llvm::Triple &normalized_triple) {
826 return !normalized_triple.getArchName().empty() &&
827 normalized_triple.getOSName().empty() &&
828 normalized_triple.getVendorName().empty() &&
829 normalized_triple.getEnvironmentName().empty();
830}
831
832void ArchSpec::MergeFrom(const ArchSpec &other) {
833 // ios-macabi always wins over macosx.
834 if ((GetTriple().getOS() == llvm::Triple::MacOSX ||
835 GetTriple().getOS() == llvm::Triple::UnknownOS) &&
836 other.GetTriple().getOS() == llvm::Triple::IOS &&
837 other.GetTriple().getEnvironment() == llvm::Triple::MacABI) {
838 (*this) = other;
839 return;
840 }
841
842 if (!TripleVendorWasSpecified() && other.TripleVendorWasSpecified())
843 GetTriple().setVendor(other.GetTriple().getVendor());
844 if (!TripleOSWasSpecified() && other.TripleOSWasSpecified())
845 GetTriple().setOS(other.GetTriple().getOS());
846 if (GetTriple().getArch() == llvm::Triple::UnknownArch) {
847 GetTriple().setArch(Kind: other.GetTriple().getArch());
848
849 // MachO unknown64 isn't really invalid as the debugger can still obtain
850 // information from the binary, e.g. line tables. As such, we don't update
851 // the core here.
852 if (other.GetCore() != eCore_uknownMach64)
853 UpdateCore();
854 }
855 if (!TripleEnvironmentWasSpecified() &&
856 other.TripleEnvironmentWasSpecified()) {
857 GetTriple().setEnvironment(other.GetTriple().getEnvironment());
858 }
859 // If this and other are both arm ArchSpecs and this ArchSpec is a generic
860 // "some kind of arm" spec but the other ArchSpec is a specific arm core,
861 // adopt the specific arm core.
862 if (GetTriple().getArch() == llvm::Triple::arm &&
863 other.GetTriple().getArch() == llvm::Triple::arm &&
864 IsCompatibleMatch(rhs: other) && GetCore() == ArchSpec::eCore_arm_generic &&
865 other.GetCore() != ArchSpec::eCore_arm_generic) {
866 m_core = other.GetCore();
867 CoreUpdated(update_triple: false);
868 }
869 if (GetFlags() == 0) {
870 SetFlags(other.GetFlags());
871 }
872}
873
874bool ArchSpec::SetArchitecture(ArchitectureType arch_type, uint32_t cpu,
875 uint32_t sub, uint32_t os) {
876 m_core = kCore_invalid;
877 bool update_triple = true;
878 const ArchDefinition *arch_def = FindArchDefinition(arch_type);
879 if (arch_def) {
880 const ArchDefinitionEntry *arch_def_entry =
881 FindArchDefinitionEntry(def: arch_def, cpu, sub);
882 if (arch_def_entry) {
883 const CoreDefinition *core_def = FindCoreDefinition(core: arch_def_entry->core);
884 if (core_def) {
885 m_core = core_def->core;
886 update_triple = false;
887 // Always use the architecture name because it might be more
888 // descriptive than the architecture enum ("armv7" ->
889 // llvm::Triple::arm).
890 m_triple.setArchName(llvm::StringRef(core_def->name));
891 if (arch_type == eArchTypeMachO) {
892 m_triple.setVendor(llvm::Triple::Apple);
893
894 // Don't set the OS. It could be simulator, macosx, ios, watchos,
895 // tvos, bridgeos. We could get close with the cpu type - but we
896 // can't get it right all of the time. Better to leave this unset
897 // so other sections of code will set it when they have more
898 // information. NB: don't call m_triple.setOS
899 // (llvm::Triple::UnknownOS). That sets the OSName to "unknown" and
900 // the ArchSpec::TripleVendorWasSpecified() method says that any
901 // OSName setting means it was specified.
902 } else if (arch_type == eArchTypeELF) {
903 switch (os) {
904 case llvm::ELF::ELFOSABI_AIX:
905 m_triple.setOS(llvm::Triple::OSType::AIX);
906 break;
907 case llvm::ELF::ELFOSABI_FREEBSD:
908 m_triple.setOS(llvm::Triple::OSType::FreeBSD);
909 break;
910 case llvm::ELF::ELFOSABI_GNU:
911 m_triple.setOS(llvm::Triple::OSType::Linux);
912 break;
913 case llvm::ELF::ELFOSABI_NETBSD:
914 m_triple.setOS(llvm::Triple::OSType::NetBSD);
915 break;
916 case llvm::ELF::ELFOSABI_OPENBSD:
917 m_triple.setOS(llvm::Triple::OSType::OpenBSD);
918 break;
919 case llvm::ELF::ELFOSABI_SOLARIS:
920 m_triple.setOS(llvm::Triple::OSType::Solaris);
921 break;
922 case llvm::ELF::ELFOSABI_STANDALONE:
923 m_triple.setOS(llvm::Triple::OSType::UnknownOS);
924 break;
925 }
926 } else if (arch_type == eArchTypeCOFF && os == llvm::Triple::Win32) {
927 m_triple.setVendor(llvm::Triple::PC);
928 m_triple.setOS(llvm::Triple::Win32);
929 } else if (arch_type == eArchTypeXCOFF && os == llvm::Triple::AIX) {
930 m_triple.setVendor(llvm::Triple::IBM);
931 m_triple.setOS(llvm::Triple::AIX);
932 } else {
933 m_triple.setVendor(llvm::Triple::UnknownVendor);
934 m_triple.setOS(llvm::Triple::UnknownOS);
935 }
936 // Fall back onto setting the machine type if the arch by name
937 // failed...
938 if (m_triple.getArch() == llvm::Triple::UnknownArch)
939 m_triple.setArch(Kind: core_def->machine);
940 }
941 } else {
942 Log *log(GetLog(mask: LLDBLog::Target | LLDBLog::Process | LLDBLog::Platform));
943 LLDB_LOGF(log,
944 "Unable to find a core definition for cpu 0x%" PRIx32
945 " sub %" PRId32,
946 cpu, sub);
947 }
948 }
949 CoreUpdated(update_triple);
950 return IsValid();
951}
952
953uint32_t ArchSpec::GetMinimumOpcodeByteSize() const {
954 const CoreDefinition *core_def = FindCoreDefinition(core: m_core);
955 if (core_def)
956 return core_def->min_opcode_byte_size;
957 return 0;
958}
959
960uint32_t ArchSpec::GetMaximumOpcodeByteSize() const {
961 const CoreDefinition *core_def = FindCoreDefinition(core: m_core);
962 if (core_def)
963 return core_def->max_opcode_byte_size;
964 return 0;
965}
966
967static bool IsCompatibleEnvironment(llvm::Triple::EnvironmentType lhs,
968 llvm::Triple::EnvironmentType rhs) {
969 if (lhs == rhs)
970 return true;
971
972 // Apple simulators are a different platform than what they simulate.
973 // As the environments are different at this point, if one of them is a
974 // simulator, then they are different.
975 if (lhs == llvm::Triple::Simulator || rhs == llvm::Triple::Simulator)
976 return false;
977
978 // If any of the environment is unknown then they are compatible
979 if (lhs == llvm::Triple::UnknownEnvironment ||
980 rhs == llvm::Triple::UnknownEnvironment)
981 return true;
982
983 // If one of the environment is Android and the other one is EABI then they
984 // are considered to be compatible. This is required as a workaround for
985 // shared libraries compiled for Android without the NOTE section indicating
986 // that they are using the Android ABI.
987 if ((lhs == llvm::Triple::Android && rhs == llvm::Triple::EABI) ||
988 (rhs == llvm::Triple::Android && lhs == llvm::Triple::EABI) ||
989 (lhs == llvm::Triple::GNUEABI && rhs == llvm::Triple::EABI) ||
990 (rhs == llvm::Triple::GNUEABI && lhs == llvm::Triple::EABI) ||
991 (lhs == llvm::Triple::GNUEABIHF && rhs == llvm::Triple::EABIHF) ||
992 (rhs == llvm::Triple::GNUEABIHF && lhs == llvm::Triple::EABIHF))
993 return true;
994
995 return false;
996}
997
998bool ArchSpec::IsMatch(const ArchSpec &rhs, MatchType match) const {
999 if (GetByteOrder() != rhs.GetByteOrder() ||
1000 !cores_match(core1: GetCore(), core2: rhs.GetCore(), try_inverse: true, enforce_exact_match: match == ExactMatch))
1001 return false;
1002
1003 const llvm::Triple &lhs_triple = GetTriple();
1004 const llvm::Triple &rhs_triple = rhs.GetTriple();
1005
1006 const llvm::Triple::VendorType lhs_triple_vendor = lhs_triple.getVendor();
1007 const llvm::Triple::VendorType rhs_triple_vendor = rhs_triple.getVendor();
1008
1009 const llvm::Triple::OSType lhs_triple_os = lhs_triple.getOS();
1010 const llvm::Triple::OSType rhs_triple_os = rhs_triple.getOS();
1011
1012 bool both_windows = lhs_triple.isOSWindows() && rhs_triple.isOSWindows();
1013
1014 // On Windows, the vendor field doesn't have any practical effect, but
1015 // it is often set to either "pc" or "w64".
1016 if ((lhs_triple_vendor != rhs_triple_vendor) &&
1017 (match == ExactMatch || !both_windows)) {
1018 const bool rhs_vendor_specified = rhs.TripleVendorWasSpecified();
1019 const bool lhs_vendor_specified = TripleVendorWasSpecified();
1020 // Both architectures had the vendor specified, so if they aren't equal
1021 // then we return false
1022 if (rhs_vendor_specified && lhs_vendor_specified)
1023 return false;
1024
1025 // Only fail if both vendor types are not unknown
1026 if (lhs_triple_vendor != llvm::Triple::UnknownVendor &&
1027 rhs_triple_vendor != llvm::Triple::UnknownVendor)
1028 return false;
1029 }
1030
1031 const llvm::Triple::EnvironmentType lhs_triple_env =
1032 lhs_triple.getEnvironment();
1033 const llvm::Triple::EnvironmentType rhs_triple_env =
1034 rhs_triple.getEnvironment();
1035
1036 if (match == CompatibleMatch) {
1037 // x86_64-apple-ios-macabi, x86_64-apple-macosx are compatible, no match.
1038 if ((lhs_triple_os == llvm::Triple::IOS &&
1039 lhs_triple_env == llvm::Triple::MacABI &&
1040 rhs_triple_os == llvm::Triple::MacOSX) ||
1041 (lhs_triple_os == llvm::Triple::MacOSX &&
1042 rhs_triple_os == llvm::Triple::IOS &&
1043 rhs_triple_env == llvm::Triple::MacABI))
1044 return true;
1045 // x86_64-apple-driverkit, x86_64-apple-macosx are compatible, no match.
1046 if ((lhs_triple_os == llvm::Triple::DriverKit &&
1047 rhs_triple_os == llvm::Triple::MacOSX) ||
1048 (lhs_triple_os == llvm::Triple::MacOSX &&
1049 rhs_triple_os == llvm::Triple::DriverKit))
1050 return true;
1051 }
1052
1053 // x86_64-apple-ios-macabi and x86_64-apple-ios are not compatible.
1054 if (lhs_triple_os == llvm::Triple::IOS &&
1055 rhs_triple_os == llvm::Triple::IOS &&
1056 (lhs_triple_env == llvm::Triple::MacABI ||
1057 rhs_triple_env == llvm::Triple::MacABI) &&
1058 lhs_triple_env != rhs_triple_env)
1059 return false;
1060
1061 if (lhs_triple_os != rhs_triple_os) {
1062 const bool lhs_os_specified = TripleOSWasSpecified();
1063 const bool rhs_os_specified = rhs.TripleOSWasSpecified();
1064 // If both OS types are specified and different, fail.
1065 if (lhs_os_specified && rhs_os_specified)
1066 return false;
1067
1068 // If the pair of os+env is both unspecified, match any other os+env combo.
1069 if (match == CompatibleMatch &&
1070 ((!lhs_os_specified && !lhs_triple.hasEnvironment()) ||
1071 (!rhs_os_specified && !rhs_triple.hasEnvironment())))
1072 return true;
1073 }
1074
1075 if (match == CompatibleMatch && both_windows)
1076 return true; // The Windows environments (MSVC vs GNU) are compatible
1077
1078 return IsCompatibleEnvironment(lhs: lhs_triple_env, rhs: rhs_triple_env);
1079}
1080
1081void ArchSpec::UpdateCore() {
1082 llvm::StringRef arch_name(m_triple.getArchName());
1083 const CoreDefinition *core_def = FindCoreDefinition(name: arch_name);
1084 if (core_def) {
1085 m_core = core_def->core;
1086 // Set the byte order to the default byte order for an architecture. This
1087 // can be modified if needed for cases when cores handle both big and
1088 // little endian
1089 m_byte_order = core_def->default_byte_order;
1090 } else {
1091 Clear();
1092 }
1093}
1094
1095//===----------------------------------------------------------------------===//
1096// Helper methods.
1097
1098void ArchSpec::CoreUpdated(bool update_triple) {
1099 const CoreDefinition *core_def = FindCoreDefinition(core: m_core);
1100 if (core_def) {
1101 if (update_triple)
1102 m_triple = llvm::Triple(core_def->name, "unknown", "unknown");
1103 m_byte_order = core_def->default_byte_order;
1104 } else {
1105 if (update_triple)
1106 m_triple = llvm::Triple();
1107 m_byte_order = eByteOrderInvalid;
1108 }
1109}
1110
1111//===----------------------------------------------------------------------===//
1112// Operators.
1113
1114static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2,
1115 bool try_inverse, bool enforce_exact_match) {
1116 if (core1 == core2)
1117 return true;
1118
1119 switch (core1) {
1120 case ArchSpec::kCore_any:
1121 return true;
1122
1123 case ArchSpec::eCore_arm_generic:
1124 if (enforce_exact_match)
1125 break;
1126 [[fallthrough]];
1127 case ArchSpec::kCore_arm_any:
1128 if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last)
1129 return true;
1130 if (core2 >= ArchSpec::kCore_thumb_first &&
1131 core2 <= ArchSpec::kCore_thumb_last)
1132 return true;
1133 if (core2 == ArchSpec::kCore_arm_any)
1134 return true;
1135 break;
1136
1137 case ArchSpec::kCore_x86_32_any:
1138 if ((core2 >= ArchSpec::kCore_x86_32_first &&
1139 core2 <= ArchSpec::kCore_x86_32_last) ||
1140 (core2 == ArchSpec::kCore_x86_32_any))
1141 return true;
1142 break;
1143
1144 case ArchSpec::kCore_x86_64_any:
1145 if ((core2 >= ArchSpec::kCore_x86_64_first &&
1146 core2 <= ArchSpec::kCore_x86_64_last) ||
1147 (core2 == ArchSpec::kCore_x86_64_any))
1148 return true;
1149 break;
1150
1151 case ArchSpec::kCore_ppc_any:
1152 if ((core2 >= ArchSpec::kCore_ppc_first &&
1153 core2 <= ArchSpec::kCore_ppc_last) ||
1154 (core2 == ArchSpec::kCore_ppc_any))
1155 return true;
1156 break;
1157
1158 case ArchSpec::kCore_ppc64_any:
1159 if ((core2 >= ArchSpec::kCore_ppc64_first &&
1160 core2 <= ArchSpec::kCore_ppc64_last) ||
1161 (core2 == ArchSpec::kCore_ppc64_any))
1162 return true;
1163 break;
1164
1165 case ArchSpec::kCore_hexagon_any:
1166 if ((core2 >= ArchSpec::kCore_hexagon_first &&
1167 core2 <= ArchSpec::kCore_hexagon_last) ||
1168 (core2 == ArchSpec::kCore_hexagon_any))
1169 return true;
1170 break;
1171
1172 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization
1173 // Cortex-M0 - ARMv6-M - armv6m
1174 // Cortex-M3 - ARMv7-M - armv7m
1175 // Cortex-M4 - ARMv7E-M - armv7em
1176 case ArchSpec::eCore_arm_armv7em:
1177 if (!enforce_exact_match) {
1178 if (core2 == ArchSpec::eCore_arm_generic)
1179 return true;
1180 if (core2 == ArchSpec::eCore_arm_armv7m)
1181 return true;
1182 if (core2 == ArchSpec::eCore_arm_armv6m)
1183 return true;
1184 if (core2 == ArchSpec::eCore_arm_armv7)
1185 return true;
1186 try_inverse = true;
1187 }
1188 break;
1189
1190 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization
1191 // Cortex-M0 - ARMv6-M - armv6m
1192 // Cortex-M3 - ARMv7-M - armv7m
1193 // Cortex-M4 - ARMv7E-M - armv7em
1194 case ArchSpec::eCore_arm_armv7m:
1195 if (!enforce_exact_match) {
1196 if (core2 == ArchSpec::eCore_arm_generic)
1197 return true;
1198 if (core2 == ArchSpec::eCore_arm_armv6m)
1199 return true;
1200 if (core2 == ArchSpec::eCore_arm_armv7)
1201 return true;
1202 if (core2 == ArchSpec::eCore_arm_armv7em)
1203 return true;
1204 try_inverse = true;
1205 }
1206 break;
1207
1208 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization
1209 // Cortex-M0 - ARMv6-M - armv6m
1210 // Cortex-M3 - ARMv7-M - armv7m
1211 // Cortex-M4 - ARMv7E-M - armv7em
1212 case ArchSpec::eCore_arm_armv6m:
1213 if (!enforce_exact_match) {
1214 if (core2 == ArchSpec::eCore_arm_generic)
1215 return true;
1216 if (core2 == ArchSpec::eCore_arm_armv7em)
1217 return true;
1218 if (core2 == ArchSpec::eCore_arm_armv7)
1219 return true;
1220 if (core2 == ArchSpec::eCore_arm_armv6m)
1221 return true;
1222 try_inverse = false;
1223 }
1224 break;
1225
1226 case ArchSpec::eCore_arm_armv7f:
1227 case ArchSpec::eCore_arm_armv7k:
1228 case ArchSpec::eCore_arm_armv7s:
1229 case ArchSpec::eCore_arm_armv7l:
1230 case ArchSpec::eCore_arm_armv8l:
1231 if (!enforce_exact_match) {
1232 if (core2 == ArchSpec::eCore_arm_generic)
1233 return true;
1234 if (core2 == ArchSpec::eCore_arm_armv7)
1235 return true;
1236 try_inverse = false;
1237 }
1238 break;
1239
1240 case ArchSpec::eCore_x86_64_x86_64h:
1241 case ArchSpec::eCore_x86_64_amd64:
1242 if (!enforce_exact_match) {
1243 try_inverse = false;
1244 if (core2 == ArchSpec::eCore_x86_64_x86_64)
1245 return true;
1246 }
1247 break;
1248
1249 case ArchSpec::eCore_arm_armv8:
1250 if (!enforce_exact_match) {
1251 if (core2 == ArchSpec::eCore_arm_arm64)
1252 return true;
1253 if (core2 == ArchSpec::eCore_arm_aarch64)
1254 return true;
1255 if (core2 == ArchSpec::eCore_arm_arm64e)
1256 return true;
1257 try_inverse = false;
1258 }
1259 break;
1260
1261 case ArchSpec::eCore_arm_arm64e:
1262 if (!enforce_exact_match) {
1263 if (core2 == ArchSpec::eCore_arm_arm64)
1264 return true;
1265 if (core2 == ArchSpec::eCore_arm_aarch64)
1266 return true;
1267 if (core2 == ArchSpec::eCore_arm_armv8)
1268 return true;
1269 try_inverse = false;
1270 }
1271 break;
1272 case ArchSpec::eCore_arm_aarch64:
1273 if (!enforce_exact_match) {
1274 if (core2 == ArchSpec::eCore_arm_arm64)
1275 return true;
1276 if (core2 == ArchSpec::eCore_arm_armv8)
1277 return true;
1278 if (core2 == ArchSpec::eCore_arm_arm64e)
1279 return true;
1280 try_inverse = false;
1281 }
1282 break;
1283
1284 case ArchSpec::eCore_arm_arm64:
1285 if (!enforce_exact_match) {
1286 if (core2 == ArchSpec::eCore_arm_aarch64)
1287 return true;
1288 if (core2 == ArchSpec::eCore_arm_armv8)
1289 return true;
1290 if (core2 == ArchSpec::eCore_arm_arm64e)
1291 return true;
1292 try_inverse = false;
1293 }
1294 break;
1295
1296 case ArchSpec::eCore_arm_arm64_32:
1297 if (!enforce_exact_match) {
1298 if (core2 == ArchSpec::eCore_arm_generic)
1299 return true;
1300 try_inverse = false;
1301 }
1302 break;
1303
1304 case ArchSpec::eCore_mips32:
1305 if (!enforce_exact_match) {
1306 if (core2 >= ArchSpec::kCore_mips32_first &&
1307 core2 <= ArchSpec::kCore_mips32_last)
1308 return true;
1309 try_inverse = false;
1310 }
1311 break;
1312
1313 case ArchSpec::eCore_mips32el:
1314 if (!enforce_exact_match) {
1315 if (core2 >= ArchSpec::kCore_mips32el_first &&
1316 core2 <= ArchSpec::kCore_mips32el_last)
1317 return true;
1318 try_inverse = true;
1319 }
1320 break;
1321
1322 case ArchSpec::eCore_mips64:
1323 if (!enforce_exact_match) {
1324 if (core2 >= ArchSpec::kCore_mips32_first &&
1325 core2 <= ArchSpec::kCore_mips32_last)
1326 return true;
1327 if (core2 >= ArchSpec::kCore_mips64_first &&
1328 core2 <= ArchSpec::kCore_mips64_last)
1329 return true;
1330 try_inverse = false;
1331 }
1332 break;
1333
1334 case ArchSpec::eCore_mips64el:
1335 if (!enforce_exact_match) {
1336 if (core2 >= ArchSpec::kCore_mips32el_first &&
1337 core2 <= ArchSpec::kCore_mips32el_last)
1338 return true;
1339 if (core2 >= ArchSpec::kCore_mips64el_first &&
1340 core2 <= ArchSpec::kCore_mips64el_last)
1341 return true;
1342 try_inverse = false;
1343 }
1344 break;
1345
1346 case ArchSpec::eCore_mips64r2:
1347 case ArchSpec::eCore_mips64r3:
1348 case ArchSpec::eCore_mips64r5:
1349 if (!enforce_exact_match) {
1350 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= (core1 - 10))
1351 return true;
1352 if (core2 >= ArchSpec::kCore_mips64_first && core2 <= (core1 - 1))
1353 return true;
1354 try_inverse = false;
1355 }
1356 break;
1357
1358 case ArchSpec::eCore_mips64r2el:
1359 case ArchSpec::eCore_mips64r3el:
1360 case ArchSpec::eCore_mips64r5el:
1361 if (!enforce_exact_match) {
1362 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= (core1 - 10))
1363 return true;
1364 if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= (core1 - 1))
1365 return true;
1366 try_inverse = false;
1367 }
1368 break;
1369
1370 case ArchSpec::eCore_mips32r2:
1371 case ArchSpec::eCore_mips32r3:
1372 case ArchSpec::eCore_mips32r5:
1373 if (!enforce_exact_match) {
1374 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= core1)
1375 return true;
1376 }
1377 break;
1378
1379 case ArchSpec::eCore_mips32r2el:
1380 case ArchSpec::eCore_mips32r3el:
1381 case ArchSpec::eCore_mips32r5el:
1382 if (!enforce_exact_match) {
1383 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= core1)
1384 return true;
1385 }
1386 break;
1387
1388 case ArchSpec::eCore_mips32r6:
1389 if (!enforce_exact_match) {
1390 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6)
1391 return true;
1392 }
1393 break;
1394
1395 case ArchSpec::eCore_mips32r6el:
1396 if (!enforce_exact_match) {
1397 if (core2 == ArchSpec::eCore_mips32el ||
1398 core2 == ArchSpec::eCore_mips32r6el)
1399 return true;
1400 }
1401 break;
1402
1403 case ArchSpec::eCore_mips64r6:
1404 if (!enforce_exact_match) {
1405 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6)
1406 return true;
1407 if (core2 == ArchSpec::eCore_mips64 || core2 == ArchSpec::eCore_mips64r6)
1408 return true;
1409 }
1410 break;
1411
1412 case ArchSpec::eCore_mips64r6el:
1413 if (!enforce_exact_match) {
1414 if (core2 == ArchSpec::eCore_mips32el ||
1415 core2 == ArchSpec::eCore_mips32r6el)
1416 return true;
1417 if (core2 == ArchSpec::eCore_mips64el ||
1418 core2 == ArchSpec::eCore_mips64r6el)
1419 return true;
1420 }
1421 break;
1422
1423 default:
1424 break;
1425 }
1426 if (try_inverse)
1427 return cores_match(core1: core2, core2: core1, try_inverse: false, enforce_exact_match);
1428 return false;
1429}
1430
1431bool lldb_private::operator<(const ArchSpec &lhs, const ArchSpec &rhs) {
1432 const ArchSpec::Core lhs_core = lhs.GetCore();
1433 const ArchSpec::Core rhs_core = rhs.GetCore();
1434 return lhs_core < rhs_core;
1435}
1436
1437
1438bool lldb_private::operator==(const ArchSpec &lhs, const ArchSpec &rhs) {
1439 return lhs.GetCore() == rhs.GetCore();
1440}
1441
1442bool ArchSpec::IsFullySpecifiedTriple() const {
1443 if (!TripleOSWasSpecified())
1444 return false;
1445
1446 if (!TripleVendorWasSpecified())
1447 return false;
1448
1449 const unsigned unspecified = 0;
1450 const llvm::Triple &triple = GetTriple();
1451 if (triple.isOSDarwin() && triple.getOSMajorVersion() == unspecified)
1452 return false;
1453
1454 return true;
1455}
1456
1457bool ArchSpec::IsAlwaysThumbInstructions() const {
1458 if (GetTriple().getArch() == llvm::Triple::arm ||
1459 GetTriple().getArch() == llvm::Triple::thumb) {
1460 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M
1461 //
1462 // Cortex-M0 through Cortex-M7 are ARM processor cores which can only
1463 // execute thumb instructions. We map the cores to arch names like this:
1464 //
1465 // Cortex-M0, Cortex-M0+, Cortex-M1: armv6m Cortex-M3: armv7m Cortex-M4,
1466 // Cortex-M7: armv7em
1467
1468 if (GetCore() == ArchSpec::Core::eCore_arm_armv7m ||
1469 GetCore() == ArchSpec::Core::eCore_arm_armv7em ||
1470 GetCore() == ArchSpec::Core::eCore_arm_armv6m ||
1471 GetCore() == ArchSpec::Core::eCore_thumbv7m ||
1472 GetCore() == ArchSpec::Core::eCore_thumbv7em ||
1473 GetCore() == ArchSpec::Core::eCore_thumbv6m) {
1474 return true;
1475 }
1476 // Windows on ARM is always thumb.
1477 if (GetTriple().isOSWindows())
1478 return true;
1479 }
1480 return false;
1481}
1482
1483void ArchSpec::DumpTriple(llvm::raw_ostream &s) const {
1484 const llvm::Triple &triple = GetTriple();
1485 llvm::StringRef arch_str = triple.getArchName();
1486 llvm::StringRef vendor_str = triple.getVendorName();
1487 llvm::StringRef os_str = triple.getOSName();
1488 llvm::StringRef environ_str = triple.getEnvironmentName();
1489
1490 s << llvm::formatv(Fmt: "{0}-{1}-{2}", Vals: arch_str.empty() ? "*" : arch_str,
1491 Vals: vendor_str.empty() ? "*" : vendor_str,
1492 Vals: os_str.empty() ? "*" : os_str);
1493
1494 if (!environ_str.empty())
1495 s << "-" << environ_str;
1496}
1497

source code of lldb/source/Utility/ArchSpec.cpp