1 | //===-- R600RegisterInfo.cpp - R600 Register Information ------------------===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | /// \file |
10 | /// R600 implementation of the TargetRegisterInfo class. |
11 | // |
12 | //===----------------------------------------------------------------------===// |
13 | |
14 | #include "R600RegisterInfo.h" |
15 | #include "MCTargetDesc/R600MCTargetDesc.h" |
16 | #include "R600Defines.h" |
17 | #include "R600Subtarget.h" |
18 | |
19 | using namespace llvm; |
20 | |
21 | #define GET_REGINFO_TARGET_DESC |
22 | #include "R600GenRegisterInfo.inc" |
23 | |
24 | unsigned R600RegisterInfo::getSubRegFromChannel(unsigned Channel) { |
25 | static const uint16_t SubRegFromChannelTable[] = { |
26 | R600::sub0, R600::sub1, R600::sub2, R600::sub3, |
27 | R600::sub4, R600::sub5, R600::sub6, R600::sub7, |
28 | R600::sub8, R600::sub9, R600::sub10, R600::sub11, |
29 | R600::sub12, R600::sub13, R600::sub14, R600::sub15 |
30 | }; |
31 | |
32 | assert(Channel < std::size(SubRegFromChannelTable)); |
33 | return SubRegFromChannelTable[Channel]; |
34 | } |
35 | |
36 | BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const { |
37 | BitVector Reserved(getNumRegs()); |
38 | |
39 | const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>(); |
40 | const R600InstrInfo *TII = ST.getInstrInfo(); |
41 | |
42 | reserveRegisterTuples(Reserved, R600::ZERO); |
43 | reserveRegisterTuples(Reserved, R600::HALF); |
44 | reserveRegisterTuples(Reserved, R600::ONE); |
45 | reserveRegisterTuples(Reserved, R600::ONE_INT); |
46 | reserveRegisterTuples(Reserved, R600::NEG_HALF); |
47 | reserveRegisterTuples(Reserved, R600::NEG_ONE); |
48 | reserveRegisterTuples(Reserved, R600::PV_X); |
49 | reserveRegisterTuples(Reserved, R600::ALU_LITERAL_X); |
50 | reserveRegisterTuples(Reserved, R600::ALU_CONST); |
51 | reserveRegisterTuples(Reserved, R600::PREDICATE_BIT); |
52 | reserveRegisterTuples(Reserved, R600::PRED_SEL_OFF); |
53 | reserveRegisterTuples(Reserved, R600::PRED_SEL_ZERO); |
54 | reserveRegisterTuples(Reserved, R600::PRED_SEL_ONE); |
55 | reserveRegisterTuples(Reserved, R600::INDIRECT_BASE_ADDR); |
56 | |
57 | for (MCPhysReg R : R600::R600_AddrRegClass) |
58 | reserveRegisterTuples(Reserved, R); |
59 | |
60 | TII->reserveIndirectRegisters(Reserved, MF, TRI: *this); |
61 | |
62 | return Reserved; |
63 | } |
64 | |
65 | // Dummy to not crash RegisterClassInfo. |
66 | static const MCPhysReg CalleeSavedReg = R600::NoRegister; |
67 | |
68 | const MCPhysReg *R600RegisterInfo::getCalleeSavedRegs( |
69 | const MachineFunction *) const { |
70 | return &CalleeSavedReg; |
71 | } |
72 | |
73 | Register R600RegisterInfo::getFrameRegister(const MachineFunction &MF) const { |
74 | return R600::NoRegister; |
75 | } |
76 | |
77 | unsigned R600RegisterInfo::getHWRegChan(unsigned reg) const { |
78 | return this->getEncodingValue(reg) >> HW_CHAN_SHIFT; |
79 | } |
80 | |
81 | unsigned R600RegisterInfo::getHWRegIndex(unsigned Reg) const { |
82 | return GET_REG_INDEX(getEncodingValue(Reg)); |
83 | } |
84 | |
85 | const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass( |
86 | MVT VT) const { |
87 | switch(VT.SimpleTy) { |
88 | default: |
89 | case MVT::i32: return &R600::R600_TReg32RegClass; |
90 | } |
91 | } |
92 | |
93 | bool R600RegisterInfo::isPhysRegLiveAcrossClauses(Register Reg) const { |
94 | assert(!Reg.isVirtual()); |
95 | |
96 | switch (Reg) { |
97 | case R600::OQAP: |
98 | case R600::OQBP: |
99 | case R600::AR_X: |
100 | return false; |
101 | default: |
102 | return true; |
103 | } |
104 | } |
105 | |
106 | bool R600RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, |
107 | int SPAdj, |
108 | unsigned FIOperandNum, |
109 | RegScavenger *RS) const { |
110 | llvm_unreachable("Subroutines not supported yet" ); |
111 | } |
112 | |
113 | void R600RegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const { |
114 | MCRegAliasIterator R(Reg, this, true); |
115 | |
116 | for (; R.isValid(); ++R) |
117 | Reserved.set(*R); |
118 | } |
119 | |