| 1 | //===- ARMRegisterBankInfo ---------------------------------------*- C++ -*-==// |
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| 2 | // |
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| 3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
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| 4 | // See https://llvm.org/LICENSE.txt for license information. |
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| 5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
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| 6 | // |
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| 7 | //===----------------------------------------------------------------------===// |
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| 8 | /// \file |
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| 9 | /// This file declares the targeting of the RegisterBankInfo class for ARM. |
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| 10 | /// \todo This should be generated by TableGen. |
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| 11 | //===----------------------------------------------------------------------===// |
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| 12 | |
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| 13 | #ifndef LLVM_LIB_TARGET_ARM_ARMREGISTERBANKINFO_H |
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| 14 | #define LLVM_LIB_TARGET_ARM_ARMREGISTERBANKINFO_H |
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| 15 | |
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| 16 | #include "llvm/CodeGen/RegisterBankInfo.h" |
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| 17 | |
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| 18 | #define GET_REGBANK_DECLARATIONS |
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| 19 | #include "ARMGenRegisterBank.inc" |
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| 20 | |
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| 21 | namespace llvm { |
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| 22 | |
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| 23 | class TargetRegisterInfo; |
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| 24 | |
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| 25 | class ARMGenRegisterBankInfo : public RegisterBankInfo { |
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| 26 | #define GET_TARGET_REGBANK_CLASS |
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| 27 | #include "ARMGenRegisterBank.inc" |
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| 28 | }; |
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| 29 | |
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| 30 | /// This class provides the information for the target register banks. |
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| 31 | class ARMRegisterBankInfo final : public ARMGenRegisterBankInfo { |
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| 32 | public: |
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| 33 | ARMRegisterBankInfo(const TargetRegisterInfo &TRI); |
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| 34 | |
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| 35 | const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC, |
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| 36 | LLT) const override; |
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| 37 | |
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| 38 | const InstructionMapping & |
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| 39 | getInstrMapping(const MachineInstr &MI) const override; |
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| 40 | }; |
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| 41 | } // End llvm namespace. |
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| 42 | #endif |
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| 43 | |
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