1//===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides ARM specific target descriptions.
10//
11//===----------------------------------------------------------------------===//
12
13#include "ARMMCTargetDesc.h"
14#include "ARMAddressingModes.h"
15#include "ARMBaseInfo.h"
16#include "ARMInstPrinter.h"
17#include "ARMMCAsmInfo.h"
18#include "TargetInfo/ARMTargetInfo.h"
19#include "llvm/DebugInfo/CodeView/CodeView.h"
20#include "llvm/MC/MCAsmBackend.h"
21#include "llvm/MC/MCCodeEmitter.h"
22#include "llvm/MC/MCELFStreamer.h"
23#include "llvm/MC/MCInstrAnalysis.h"
24#include "llvm/MC/MCInstrInfo.h"
25#include "llvm/MC/MCObjectWriter.h"
26#include "llvm/MC/MCRegisterInfo.h"
27#include "llvm/MC/MCStreamer.h"
28#include "llvm/MC/MCSubtargetInfo.h"
29#include "llvm/MC/TargetRegistry.h"
30#include "llvm/Support/ErrorHandling.h"
31#include "llvm/TargetParser/Triple.h"
32
33using namespace llvm;
34
35#define GET_REGINFO_MC_DESC
36#include "ARMGenRegisterInfo.inc"
37
38static bool getMCRDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
39 std::string &Info) {
40 if (STI.hasFeature(llvm::ARM::Feature: HasV7Ops) &&
41 (MI.getOperand(i: 0).isImm() && MI.getOperand(i: 0).getImm() == 15) &&
42 (MI.getOperand(i: 1).isImm() && MI.getOperand(i: 1).getImm() == 0) &&
43 // Checks for the deprecated CP15ISB encoding:
44 // mcr p15, #0, rX, c7, c5, #4
45 (MI.getOperand(i: 3).isImm() && MI.getOperand(i: 3).getImm() == 7)) {
46 if ((MI.getOperand(i: 5).isImm() && MI.getOperand(i: 5).getImm() == 4)) {
47 if (MI.getOperand(i: 4).isImm() && MI.getOperand(i: 4).getImm() == 5) {
48 Info = "deprecated since v7, use 'isb'";
49 return true;
50 }
51
52 // Checks for the deprecated CP15DSB encoding:
53 // mcr p15, #0, rX, c7, c10, #4
54 if (MI.getOperand(i: 4).isImm() && MI.getOperand(i: 4).getImm() == 10) {
55 Info = "deprecated since v7, use 'dsb'";
56 return true;
57 }
58 }
59 // Checks for the deprecated CP15DMB encoding:
60 // mcr p15, #0, rX, c7, c10, #5
61 if (MI.getOperand(i: 4).isImm() && MI.getOperand(i: 4).getImm() == 10 &&
62 (MI.getOperand(i: 5).isImm() && MI.getOperand(i: 5).getImm() == 5)) {
63 Info = "deprecated since v7, use 'dmb'";
64 return true;
65 }
66 }
67 if (STI.hasFeature(llvm::ARM::HasV7Ops) &&
68 ((MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 10) ||
69 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 11))) {
70 Info = "since v7, cp10 and cp11 are reserved for advanced SIMD or floating "
71 "point instructions";
72 return true;
73 }
74 return false;
75}
76
77static bool getMRCDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
78 std::string &Info) {
79 if (STI.hasFeature(llvm::ARM::Feature: HasV7Ops) &&
80 ((MI.getOperand(i: 0).isImm() && MI.getOperand(i: 0).getImm() == 10) ||
81 (MI.getOperand(i: 0).isImm() && MI.getOperand(i: 0).getImm() == 11))) {
82 Info = "since v7, cp10 and cp11 are reserved for advanced SIMD or floating "
83 "point instructions";
84 return true;
85 }
86 return false;
87}
88
89static bool getARMStoreDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
90 std::string &Info) {
91 assert(!STI.hasFeature(llvm::ARM::ModeThumb) &&
92 "cannot predicate thumb instructions");
93
94 assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
95 for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
96 assert(MI.getOperand(OI).isReg() && "expected register");
97 if (MI.getOperand(i: OI).getReg() == ARM::PC) {
98 Info = "use of PC in the list is deprecated";
99 return true;
100 }
101 }
102 return false;
103}
104
105static bool getARMLoadDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
106 std::string &Info) {
107 assert(!STI.hasFeature(llvm::ARM::ModeThumb) &&
108 "cannot predicate thumb instructions");
109
110 assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
111 bool ListContainsPC = false, ListContainsLR = false;
112 for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
113 assert(MI.getOperand(OI).isReg() && "expected register");
114 switch (MI.getOperand(i: OI).getReg()) {
115 default:
116 break;
117 case ARM::LR:
118 ListContainsLR = true;
119 break;
120 case ARM::PC:
121 ListContainsPC = true;
122 break;
123 }
124 }
125
126 if (ListContainsPC && ListContainsLR) {
127 Info = "use of LR and PC simultaneously in the list is deprecated";
128 return true;
129 }
130
131 return false;
132}
133
134#define GET_INSTRINFO_MC_DESC
135#define ENABLE_INSTR_PREDICATE_VERIFIER
136#include "ARMGenInstrInfo.inc"
137
138#define GET_SUBTARGETINFO_MC_DESC
139#include "ARMGenSubtargetInfo.inc"
140
141std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
142 std::string ARMArchFeature;
143
144 ARM::ArchKind ArchID = ARM::parseArch(Arch: TT.getArchName());
145 if (ArchID != ARM::ArchKind::INVALID && (CPU.empty() || CPU == "generic"))
146 ARMArchFeature = (ARMArchFeature + "+" + ARM::getArchName(AK: ArchID)).str();
147
148 if (TT.isThumb()) {
149 if (!ARMArchFeature.empty())
150 ARMArchFeature += ",";
151 ARMArchFeature += "+thumb-mode,+v4t";
152 }
153
154 if (TT.isOSNaCl()) {
155 if (!ARMArchFeature.empty())
156 ARMArchFeature += ",";
157 ARMArchFeature += "+nacl-trap";
158 }
159
160 if (TT.isOSWindows()) {
161 if (!ARMArchFeature.empty())
162 ARMArchFeature += ",";
163 ARMArchFeature += "+noarm";
164 }
165
166 return ARMArchFeature;
167}
168
169bool ARM_MC::isPredicated(const MCInst &MI, const MCInstrInfo *MCII) {
170 const MCInstrDesc &Desc = MCII->get(Opcode: MI.getOpcode());
171 int PredOpIdx = Desc.findFirstPredOperandIdx();
172 return PredOpIdx != -1 && MI.getOperand(i: PredOpIdx).getImm() != ARMCC::AL;
173}
174
175bool ARM_MC::isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII) {
176 const MCInstrDesc &Desc = MCII->get(Opcode: MI.getOpcode());
177 for (unsigned I = 0; I < MI.getNumOperands(); ++I) {
178 const MCOperand &MO = MI.getOperand(i: I);
179 if (MO.isReg() && MO.getReg() == ARM::CPSR &&
180 Desc.operands()[I].isOptionalDef())
181 return true;
182 }
183 return false;
184}
185
186uint64_t ARM_MC::evaluateBranchTarget(const MCInstrDesc &InstDesc,
187 uint64_t Addr, int64_t Imm) {
188 // For ARM instructions the PC offset is 8 bytes, for Thumb instructions it
189 // is 4 bytes.
190 uint64_t Offset =
191 ((InstDesc.TSFlags & ARMII::FormMask) == ARMII::ThumbFrm) ? 4 : 8;
192
193 // A Thumb instruction BLX(i) can be 16-bit aligned while targets Arm code
194 // which is 32-bit aligned. The target address for the case is calculated as
195 // targetAddress = Align(PC,4) + imm32;
196 // where
197 // Align(x, y) = y * (x DIV y);
198 if (InstDesc.getOpcode() == ARM::tBLXi)
199 Addr &= ~0x3;
200
201 return Addr + Imm + Offset;
202}
203
204MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(const Triple &TT,
205 StringRef CPU, StringRef FS) {
206 std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
207 if (!FS.empty()) {
208 if (!ArchFS.empty())
209 ArchFS = (Twine(ArchFS) + "," + FS).str();
210 else
211 ArchFS = std::string(FS);
212 }
213
214 return createARMMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, ArchFS);
215}
216
217static MCInstrInfo *createARMMCInstrInfo() {
218 MCInstrInfo *X = new MCInstrInfo();
219 InitARMMCInstrInfo(X);
220 return X;
221}
222
223void ARM_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {
224 // Mapping from CodeView to MC register id.
225 static const struct {
226 codeview::RegisterId CVReg;
227 MCPhysReg Reg;
228 } RegMap[] = {
229 {codeview::RegisterId::ARM_R0, ARM::R0},
230 {codeview::RegisterId::ARM_R1, ARM::R1},
231 {codeview::RegisterId::ARM_R2, ARM::R2},
232 {codeview::RegisterId::ARM_R3, ARM::R3},
233 {codeview::RegisterId::ARM_R4, ARM::R4},
234 {codeview::RegisterId::ARM_R5, ARM::R5},
235 {codeview::RegisterId::ARM_R6, ARM::R6},
236 {codeview::RegisterId::ARM_R7, ARM::R7},
237 {codeview::RegisterId::ARM_R8, ARM::R8},
238 {codeview::RegisterId::ARM_R9, ARM::R9},
239 {codeview::RegisterId::ARM_R10, ARM::R10},
240 {codeview::RegisterId::ARM_R11, ARM::R11},
241 {codeview::RegisterId::ARM_R12, ARM::R12},
242 {codeview::RegisterId::ARM_SP, ARM::SP},
243 {codeview::RegisterId::ARM_LR, ARM::LR},
244 {codeview::RegisterId::ARM_PC, ARM::PC},
245 {codeview::RegisterId::ARM_CPSR, ARM::CPSR},
246 {codeview::RegisterId::ARM_FPSCR, ARM::FPSCR},
247 {codeview::RegisterId::ARM_FPEXC, ARM::FPEXC},
248 {codeview::RegisterId::ARM_FS0, ARM::S0},
249 {codeview::RegisterId::ARM_FS1, ARM::S1},
250 {codeview::RegisterId::ARM_FS2, ARM::S2},
251 {codeview::RegisterId::ARM_FS3, ARM::S3},
252 {codeview::RegisterId::ARM_FS4, ARM::S4},
253 {codeview::RegisterId::ARM_FS5, ARM::S5},
254 {codeview::RegisterId::ARM_FS6, ARM::S6},
255 {codeview::RegisterId::ARM_FS7, ARM::S7},
256 {codeview::RegisterId::ARM_FS8, ARM::S8},
257 {codeview::RegisterId::ARM_FS9, ARM::S9},
258 {codeview::RegisterId::ARM_FS10, ARM::S10},
259 {codeview::RegisterId::ARM_FS11, ARM::S11},
260 {codeview::RegisterId::ARM_FS12, ARM::S12},
261 {codeview::RegisterId::ARM_FS13, ARM::S13},
262 {codeview::RegisterId::ARM_FS14, ARM::S14},
263 {codeview::RegisterId::ARM_FS15, ARM::S15},
264 {codeview::RegisterId::ARM_FS16, ARM::S16},
265 {codeview::RegisterId::ARM_FS17, ARM::S17},
266 {codeview::RegisterId::ARM_FS18, ARM::S18},
267 {codeview::RegisterId::ARM_FS19, ARM::S19},
268 {codeview::RegisterId::ARM_FS20, ARM::S20},
269 {codeview::RegisterId::ARM_FS21, ARM::S21},
270 {codeview::RegisterId::ARM_FS22, ARM::S22},
271 {codeview::RegisterId::ARM_FS23, ARM::S23},
272 {codeview::RegisterId::ARM_FS24, ARM::S24},
273 {codeview::RegisterId::ARM_FS25, ARM::S25},
274 {codeview::RegisterId::ARM_FS26, ARM::S26},
275 {codeview::RegisterId::ARM_FS27, ARM::S27},
276 {codeview::RegisterId::ARM_FS28, ARM::S28},
277 {codeview::RegisterId::ARM_FS29, ARM::S29},
278 {codeview::RegisterId::ARM_FS30, ARM::S30},
279 {codeview::RegisterId::ARM_FS31, ARM::S31},
280 {codeview::RegisterId::ARM_ND0, ARM::D0},
281 {codeview::RegisterId::ARM_ND1, ARM::D1},
282 {codeview::RegisterId::ARM_ND2, ARM::D2},
283 {codeview::RegisterId::ARM_ND3, ARM::D3},
284 {codeview::RegisterId::ARM_ND4, ARM::D4},
285 {codeview::RegisterId::ARM_ND5, ARM::D5},
286 {codeview::RegisterId::ARM_ND6, ARM::D6},
287 {codeview::RegisterId::ARM_ND7, ARM::D7},
288 {codeview::RegisterId::ARM_ND8, ARM::D8},
289 {codeview::RegisterId::ARM_ND9, ARM::D9},
290 {codeview::RegisterId::ARM_ND10, ARM::D10},
291 {codeview::RegisterId::ARM_ND11, ARM::D11},
292 {codeview::RegisterId::ARM_ND12, ARM::D12},
293 {codeview::RegisterId::ARM_ND13, ARM::D13},
294 {codeview::RegisterId::ARM_ND14, ARM::D14},
295 {codeview::RegisterId::ARM_ND15, ARM::D15},
296 {codeview::RegisterId::ARM_ND16, ARM::D16},
297 {codeview::RegisterId::ARM_ND17, ARM::D17},
298 {codeview::RegisterId::ARM_ND18, ARM::D18},
299 {codeview::RegisterId::ARM_ND19, ARM::D19},
300 {codeview::RegisterId::ARM_ND20, ARM::D20},
301 {codeview::RegisterId::ARM_ND21, ARM::D21},
302 {codeview::RegisterId::ARM_ND22, ARM::D22},
303 {codeview::RegisterId::ARM_ND23, ARM::D23},
304 {codeview::RegisterId::ARM_ND24, ARM::D24},
305 {codeview::RegisterId::ARM_ND25, ARM::D25},
306 {codeview::RegisterId::ARM_ND26, ARM::D26},
307 {codeview::RegisterId::ARM_ND27, ARM::D27},
308 {codeview::RegisterId::ARM_ND28, ARM::D28},
309 {codeview::RegisterId::ARM_ND29, ARM::D29},
310 {codeview::RegisterId::ARM_ND30, ARM::D30},
311 {codeview::RegisterId::ARM_ND31, ARM::D31},
312 {codeview::RegisterId::ARM_NQ0, ARM::Q0},
313 {codeview::RegisterId::ARM_NQ1, ARM::Q1},
314 {codeview::RegisterId::ARM_NQ2, ARM::Q2},
315 {codeview::RegisterId::ARM_NQ3, ARM::Q3},
316 {codeview::RegisterId::ARM_NQ4, ARM::Q4},
317 {codeview::RegisterId::ARM_NQ5, ARM::Q5},
318 {codeview::RegisterId::ARM_NQ6, ARM::Q6},
319 {codeview::RegisterId::ARM_NQ7, ARM::Q7},
320 {codeview::RegisterId::ARM_NQ8, ARM::Q8},
321 {codeview::RegisterId::ARM_NQ9, ARM::Q9},
322 {codeview::RegisterId::ARM_NQ10, ARM::Q10},
323 {codeview::RegisterId::ARM_NQ11, ARM::Q11},
324 {codeview::RegisterId::ARM_NQ12, ARM::Q12},
325 {codeview::RegisterId::ARM_NQ13, ARM::Q13},
326 {codeview::RegisterId::ARM_NQ14, ARM::Q14},
327 {codeview::RegisterId::ARM_NQ15, ARM::Q15},
328 };
329 for (const auto &I : RegMap)
330 MRI->mapLLVMRegToCVReg(I.Reg, static_cast<int>(I.CVReg));
331}
332
333static MCRegisterInfo *createARMMCRegisterInfo(const Triple &Triple) {
334 MCRegisterInfo *X = new MCRegisterInfo();
335 InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
336 ARM_MC::initLLVMToCVRegMapping(MRI: X);
337 return X;
338}
339
340static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI,
341 const Triple &TheTriple,
342 const MCTargetOptions &Options) {
343 MCAsmInfo *MAI;
344 if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO())
345 MAI = new ARMMCAsmInfoDarwin(TheTriple);
346 else if (TheTriple.isWindowsMSVCEnvironment())
347 MAI = new ARMCOFFMCAsmInfoMicrosoft();
348 else if (TheTriple.isOSWindows())
349 MAI = new ARMCOFFMCAsmInfoGNU();
350 else
351 MAI = new ARMELFMCAsmInfo(TheTriple);
352
353 unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
354 MAI->addInitialFrameState(Inst: MCCFIInstruction::cfiDefCfa(L: nullptr, Register: Reg, Offset: 0));
355
356 return MAI;
357}
358
359static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx,
360 std::unique_ptr<MCAsmBackend> &&MAB,
361 std::unique_ptr<MCObjectWriter> &&OW,
362 std::unique_ptr<MCCodeEmitter> &&Emitter,
363 bool RelaxAll) {
364 return createARMELFStreamer(
365 Context&: Ctx, TAB: std::move(MAB), OW: std::move(OW), Emitter: std::move(Emitter), RelaxAll: false,
366 IsThumb: (T.getArch() == Triple::thumb || T.getArch() == Triple::thumbeb),
367 IsAndroid: T.isAndroid());
368}
369
370static MCStreamer *
371createARMMachOStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&MAB,
372 std::unique_ptr<MCObjectWriter> &&OW,
373 std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll,
374 bool DWARFMustBeAtTheEnd) {
375 return createMachOStreamer(Ctx, TAB: std::move(MAB), OW: std::move(OW),
376 CE: std::move(Emitter), RelaxAll: false, DWARFMustBeAtTheEnd);
377}
378
379static MCInstPrinter *createARMMCInstPrinter(const Triple &T,
380 unsigned SyntaxVariant,
381 const MCAsmInfo &MAI,
382 const MCInstrInfo &MII,
383 const MCRegisterInfo &MRI) {
384 if (SyntaxVariant == 0)
385 return new ARMInstPrinter(MAI, MII, MRI);
386 return nullptr;
387}
388
389static MCRelocationInfo *createARMMCRelocationInfo(const Triple &TT,
390 MCContext &Ctx) {
391 if (TT.isOSBinFormatMachO())
392 return createARMMachORelocationInfo(Ctx);
393 // Default to the stock relocation info.
394 return llvm::createMCRelocationInfo(TT, Ctx);
395}
396
397namespace {
398
399class ARMMCInstrAnalysis : public MCInstrAnalysis {
400public:
401 ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
402
403 bool isUnconditionalBranch(const MCInst &Inst) const override {
404 // BCCs with the "always" predicate are unconditional branches.
405 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
406 return true;
407 return MCInstrAnalysis::isUnconditionalBranch(Inst);
408 }
409
410 bool isConditionalBranch(const MCInst &Inst) const override {
411 // BCCs with the "always" predicate are unconditional branches.
412 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
413 return false;
414 return MCInstrAnalysis::isConditionalBranch(Inst);
415 }
416
417 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
418 uint64_t &Target) const override {
419 const MCInstrDesc &Desc = Info->get(Opcode: Inst.getOpcode());
420
421 // Find the PC-relative immediate operand in the instruction.
422 for (unsigned OpNum = 0; OpNum < Desc.getNumOperands(); ++OpNum) {
423 if (Inst.getOperand(i: OpNum).isImm() &&
424 Desc.operands()[OpNum].OperandType == MCOI::OPERAND_PCREL) {
425 int64_t Imm = Inst.getOperand(i: OpNum).getImm();
426 Target = ARM_MC::evaluateBranchTarget(InstDesc: Desc, Addr, Imm);
427 return true;
428 }
429 }
430 return false;
431 }
432
433 std::optional<uint64_t>
434 evaluateMemoryOperandAddress(const MCInst &Inst, const MCSubtargetInfo *STI,
435 uint64_t Addr, uint64_t Size) const override;
436};
437
438} // namespace
439
440static std::optional<uint64_t>
441// NOLINTNEXTLINE(readability-identifier-naming)
442evaluateMemOpAddrForAddrMode_i12(const MCInst &Inst, const MCInstrDesc &Desc,
443 unsigned MemOpIndex, uint64_t Addr) {
444 if (MemOpIndex + 1 >= Desc.getNumOperands())
445 return std::nullopt;
446
447 const MCOperand &MO1 = Inst.getOperand(i: MemOpIndex);
448 const MCOperand &MO2 = Inst.getOperand(i: MemOpIndex + 1);
449 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm())
450 return std::nullopt;
451
452 int32_t OffImm = (int32_t)MO2.getImm();
453 // Special value for #-0. All others are normal.
454 if (OffImm == INT32_MIN)
455 OffImm = 0;
456 return Addr + OffImm;
457}
458
459static std::optional<uint64_t>
460evaluateMemOpAddrForAddrMode3(const MCInst &Inst, const MCInstrDesc &Desc,
461 unsigned MemOpIndex, uint64_t Addr) {
462 if (MemOpIndex + 2 >= Desc.getNumOperands())
463 return std::nullopt;
464
465 const MCOperand &MO1 = Inst.getOperand(i: MemOpIndex);
466 const MCOperand &MO2 = Inst.getOperand(i: MemOpIndex + 1);
467 const MCOperand &MO3 = Inst.getOperand(i: MemOpIndex + 2);
468 if (!MO1.isReg() || MO1.getReg() != ARM::PC || MO2.getReg() || !MO3.isImm())
469 return std::nullopt;
470
471 unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc: MO3.getImm());
472 ARM_AM::AddrOpc Op = ARM_AM::getAM3Op(AM3Opc: MO3.getImm());
473
474 if (Op == ARM_AM::sub)
475 return Addr - ImmOffs;
476 return Addr + ImmOffs;
477}
478
479static std::optional<uint64_t>
480evaluateMemOpAddrForAddrMode5(const MCInst &Inst, const MCInstrDesc &Desc,
481 unsigned MemOpIndex, uint64_t Addr) {
482 if (MemOpIndex + 1 >= Desc.getNumOperands())
483 return std::nullopt;
484
485 const MCOperand &MO1 = Inst.getOperand(i: MemOpIndex);
486 const MCOperand &MO2 = Inst.getOperand(i: MemOpIndex + 1);
487 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm())
488 return std::nullopt;
489
490 unsigned ImmOffs = ARM_AM::getAM5Offset(AM5Opc: MO2.getImm());
491 ARM_AM::AddrOpc Op = ARM_AM::getAM5Op(AM5Opc: MO2.getImm());
492
493 if (Op == ARM_AM::sub)
494 return Addr - ImmOffs * 4;
495 return Addr + ImmOffs * 4;
496}
497
498static std::optional<uint64_t>
499evaluateMemOpAddrForAddrMode5FP16(const MCInst &Inst, const MCInstrDesc &Desc,
500 unsigned MemOpIndex, uint64_t Addr) {
501 if (MemOpIndex + 1 >= Desc.getNumOperands())
502 return std::nullopt;
503
504 const MCOperand &MO1 = Inst.getOperand(i: MemOpIndex);
505 const MCOperand &MO2 = Inst.getOperand(i: MemOpIndex + 1);
506 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm())
507 return std::nullopt;
508
509 unsigned ImmOffs = ARM_AM::getAM5FP16Offset(AM5Opc: MO2.getImm());
510 ARM_AM::AddrOpc Op = ARM_AM::getAM5FP16Op(AM5Opc: MO2.getImm());
511
512 if (Op == ARM_AM::sub)
513 return Addr - ImmOffs * 2;
514 return Addr + ImmOffs * 2;
515}
516
517static std::optional<uint64_t>
518// NOLINTNEXTLINE(readability-identifier-naming)
519evaluateMemOpAddrForAddrModeT2_i8s4(const MCInst &Inst, const MCInstrDesc &Desc,
520 unsigned MemOpIndex, uint64_t Addr) {
521 if (MemOpIndex + 1 >= Desc.getNumOperands())
522 return std::nullopt;
523
524 const MCOperand &MO1 = Inst.getOperand(i: MemOpIndex);
525 const MCOperand &MO2 = Inst.getOperand(i: MemOpIndex + 1);
526 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm())
527 return std::nullopt;
528
529 int32_t OffImm = (int32_t)MO2.getImm();
530 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
531
532 // Special value for #-0. All others are normal.
533 if (OffImm == INT32_MIN)
534 OffImm = 0;
535 return Addr + OffImm;
536}
537
538static std::optional<uint64_t>
539// NOLINTNEXTLINE(readability-identifier-naming)
540evaluateMemOpAddrForAddrModeT2_pc(const MCInst &Inst, const MCInstrDesc &Desc,
541 unsigned MemOpIndex, uint64_t Addr) {
542 const MCOperand &MO1 = Inst.getOperand(i: MemOpIndex);
543 if (!MO1.isImm())
544 return std::nullopt;
545
546 int32_t OffImm = (int32_t)MO1.getImm();
547
548 // Special value for #-0. All others are normal.
549 if (OffImm == INT32_MIN)
550 OffImm = 0;
551 return Addr + OffImm;
552}
553
554static std::optional<uint64_t>
555// NOLINTNEXTLINE(readability-identifier-naming)
556evaluateMemOpAddrForAddrModeT1_s(const MCInst &Inst, const MCInstrDesc &Desc,
557 unsigned MemOpIndex, uint64_t Addr) {
558 return evaluateMemOpAddrForAddrModeT2_pc(Inst, Desc, MemOpIndex, Addr);
559}
560
561std::optional<uint64_t> ARMMCInstrAnalysis::evaluateMemoryOperandAddress(
562 const MCInst &Inst, const MCSubtargetInfo *STI, uint64_t Addr,
563 uint64_t Size) const {
564 const MCInstrDesc &Desc = Info->get(Opcode: Inst.getOpcode());
565
566 // Only load instructions can have PC-relative memory addressing.
567 if (!Desc.mayLoad())
568 return std::nullopt;
569
570 // PC-relative addressing does not update the base register.
571 uint64_t TSFlags = Desc.TSFlags;
572 unsigned IndexMode =
573 (TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift;
574 if (IndexMode != ARMII::IndexModeNone)
575 return std::nullopt;
576
577 // Find the memory addressing operand in the instruction.
578 unsigned OpIndex = Desc.NumDefs;
579 while (OpIndex < Desc.getNumOperands() &&
580 Desc.operands()[OpIndex].OperandType != MCOI::OPERAND_MEMORY)
581 ++OpIndex;
582 if (OpIndex == Desc.getNumOperands())
583 return std::nullopt;
584
585 // Base address for PC-relative addressing is always 32-bit aligned.
586 Addr &= ~0x3;
587
588 // For ARM instructions the PC offset is 8 bytes, for Thumb instructions it
589 // is 4 bytes.
590 switch (Desc.TSFlags & ARMII::FormMask) {
591 default:
592 Addr += 8;
593 break;
594 case ARMII::ThumbFrm:
595 Addr += 4;
596 break;
597 // VLDR* instructions share the same opcode (and thus the same form) for Arm
598 // and Thumb. Use a bit longer route through STI in that case.
599 case ARMII::VFPLdStFrm:
600 Addr += STI->hasFeature(ARM::ModeThumb) ? 4 : 8;
601 break;
602 }
603
604 // Eveluate the address depending on the addressing mode
605 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
606 switch (AddrMode) {
607 default:
608 return std::nullopt;
609 case ARMII::AddrMode_i12:
610 return evaluateMemOpAddrForAddrMode_i12(Inst, Desc, MemOpIndex: OpIndex, Addr);
611 case ARMII::AddrMode3:
612 return evaluateMemOpAddrForAddrMode3(Inst, Desc, MemOpIndex: OpIndex, Addr);
613 case ARMII::AddrMode5:
614 return evaluateMemOpAddrForAddrMode5(Inst, Desc, MemOpIndex: OpIndex, Addr);
615 case ARMII::AddrMode5FP16:
616 return evaluateMemOpAddrForAddrMode5FP16(Inst, Desc, MemOpIndex: OpIndex, Addr);
617 case ARMII::AddrModeT2_i8s4:
618 return evaluateMemOpAddrForAddrModeT2_i8s4(Inst, Desc, MemOpIndex: OpIndex, Addr);
619 case ARMII::AddrModeT2_pc:
620 return evaluateMemOpAddrForAddrModeT2_pc(Inst, Desc, MemOpIndex: OpIndex, Addr);
621 case ARMII::AddrModeT1_s:
622 return evaluateMemOpAddrForAddrModeT1_s(Inst, Desc, MemOpIndex: OpIndex, Addr);
623 }
624}
625
626static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
627 return new ARMMCInstrAnalysis(Info);
628}
629
630bool ARM::isCDECoproc(size_t Coproc, const MCSubtargetInfo &STI) {
631 // Unfortunately we don't have ARMTargetInfo in the disassembler, so we have
632 // to rely on feature bits.
633 if (Coproc >= 8)
634 return false;
635 return STI.getFeatureBits()[ARM::FeatureCoprocCDE0 + Coproc];
636}
637
638// Force static initialization.
639extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTargetMC() {
640 for (Target *T : {&getTheARMLETarget(), &getTheARMBETarget(),
641 &getTheThumbLETarget(), &getTheThumbBETarget()}) {
642 // Register the MC asm info.
643 RegisterMCAsmInfoFn X(*T, createARMMCAsmInfo);
644
645 // Register the MC instruction info.
646 TargetRegistry::RegisterMCInstrInfo(T&: *T, Fn: createARMMCInstrInfo);
647
648 // Register the MC register info.
649 TargetRegistry::RegisterMCRegInfo(T&: *T, Fn: createARMMCRegisterInfo);
650
651 // Register the MC subtarget info.
652 TargetRegistry::RegisterMCSubtargetInfo(T&: *T,
653 Fn: ARM_MC::createARMMCSubtargetInfo);
654
655 TargetRegistry::RegisterELFStreamer(T&: *T, Fn: createELFStreamer);
656 TargetRegistry::RegisterCOFFStreamer(T&: *T, Fn: createARMWinCOFFStreamer);
657 TargetRegistry::RegisterMachOStreamer(T&: *T, Fn: createARMMachOStreamer);
658
659 // Register the obj target streamer.
660 TargetRegistry::RegisterObjectTargetStreamer(T&: *T,
661 Fn: createARMObjectTargetStreamer);
662
663 // Register the asm streamer.
664 TargetRegistry::RegisterAsmTargetStreamer(T&: *T, Fn: createARMTargetAsmStreamer);
665
666 // Register the null TargetStreamer.
667 TargetRegistry::RegisterNullTargetStreamer(T&: *T, Fn: createARMNullTargetStreamer);
668
669 // Register the MCInstPrinter.
670 TargetRegistry::RegisterMCInstPrinter(T&: *T, Fn: createARMMCInstPrinter);
671
672 // Register the MC relocation info.
673 TargetRegistry::RegisterMCRelocationInfo(T&: *T, Fn: createARMMCRelocationInfo);
674 }
675
676 // Register the MC instruction analyzer.
677 for (Target *T : {&getTheARMLETarget(), &getTheARMBETarget(),
678 &getTheThumbLETarget(), &getTheThumbBETarget()})
679 TargetRegistry::RegisterMCInstrAnalysis(T&: *T, Fn: createARMMCInstrAnalysis);
680
681 for (Target *T : {&getTheARMLETarget(), &getTheThumbLETarget()}) {
682 TargetRegistry::RegisterMCCodeEmitter(T&: *T, Fn: createARMLEMCCodeEmitter);
683 TargetRegistry::RegisterMCAsmBackend(T&: *T, Fn: createARMLEAsmBackend);
684 }
685 for (Target *T : {&getTheARMBETarget(), &getTheThumbBETarget()}) {
686 TargetRegistry::RegisterMCCodeEmitter(T&: *T, Fn: createARMBEMCCodeEmitter);
687 TargetRegistry::RegisterMCAsmBackend(T&: *T, Fn: createARMBEAsmBackend);
688 }
689}
690

source code of llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp