| 1 | //===- ThumbRegisterInfo.h - Thumb Register Information Impl -*- C++ -*-===// |
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| 2 | // |
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| 3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
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| 4 | // See https://llvm.org/LICENSE.txt for license information. |
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| 5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
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| 6 | // |
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| 7 | //===----------------------------------------------------------------------===// |
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| 8 | // |
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| 9 | // This file contains the Thumb implementation of the TargetRegisterInfo |
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| 10 | // class. With the exception of emitLoadConstPool Thumb2 tracks |
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| 11 | // ARMBaseRegisterInfo, Thumb1 overloads the functions below. |
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| 12 | // |
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| 13 | //===----------------------------------------------------------------------===// |
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| 14 | |
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| 15 | #ifndef LLVM_LIB_TARGET_ARM_THUMB1REGISTERINFO_H |
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| 16 | #define LLVM_LIB_TARGET_ARM_THUMB1REGISTERINFO_H |
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| 17 | |
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| 18 | #include "ARMBaseRegisterInfo.h" |
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| 19 | #include "llvm/CodeGen/TargetRegisterInfo.h" |
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| 20 | |
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| 21 | namespace llvm { |
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| 22 | class ARMSubtarget; |
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| 23 | class ARMBaseInstrInfo; |
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| 24 | |
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| 25 | struct ThumbRegisterInfo : public ARMBaseRegisterInfo { |
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| 26 | public: |
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| 27 | ThumbRegisterInfo(); |
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| 28 | |
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| 29 | const TargetRegisterClass * |
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| 30 | getLargestLegalSuperClass(const TargetRegisterClass *RC, |
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| 31 | const MachineFunction &MF) const override; |
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| 32 | |
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| 33 | const TargetRegisterClass * |
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| 34 | getPointerRegClass(const MachineFunction &MF, |
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| 35 | unsigned Kind = 0) const override; |
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| 36 | |
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| 37 | /// emitLoadConstPool - Emits a load from constpool to materialize the |
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| 38 | /// specified immediate. |
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| 39 | void |
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| 40 | emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, |
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| 41 | const DebugLoc &dl, Register DestReg, unsigned SubIdx, |
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| 42 | int Val, ARMCC::CondCodes Pred = ARMCC::AL, |
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| 43 | Register PredReg = Register(), |
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| 44 | unsigned MIFlags = MachineInstr::NoFlags) const override; |
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| 45 | |
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| 46 | // rewrite MI to access 'Offset' bytes from the FP. Update Offset to be |
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| 47 | // however much remains to be handled. Return 'true' if no further |
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| 48 | // work is required. |
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| 49 | bool rewriteFrameIndex(MachineBasicBlock::iterator II, unsigned FrameRegIdx, |
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| 50 | Register FrameReg, int &Offset, |
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| 51 | const ARMBaseInstrInfo &TII) const; |
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| 52 | void resolveFrameIndex(MachineInstr &MI, Register BaseReg, |
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| 53 | int64_t Offset) const override; |
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| 54 | bool eliminateFrameIndex(MachineBasicBlock::iterator II, |
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| 55 | int SPAdj, unsigned FIOperandNum, |
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| 56 | RegScavenger *RS = nullptr) const override; |
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| 57 | bool useFPForScavengingIndex(const MachineFunction &MF) const override; |
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| 58 | }; |
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| 59 | } |
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| 60 | |
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| 61 | #endif |
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| 62 | |
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