1//===-- XtensaInstrInfo.h - Xtensa Instruction Information ------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
6// See https://llvm.org/LICENSE.txt for license information.
7// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
8//
9//===----------------------------------------------------------------------===//
10//
11// This file contains the Xtensa implementation of the TargetInstrInfo class.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_LIB_TARGET_XTENSA_XTENSAINSTRINFO_H
16#define LLVM_LIB_TARGET_XTENSA_XTENSAINSTRINFO_H
17
18#include "Xtensa.h"
19#include "XtensaRegisterInfo.h"
20#include "llvm/CodeGen/TargetInstrInfo.h"
21#include "llvm/CodeGen/TargetRegisterInfo.h"
22
23#define GET_INSTRINFO_HEADER
24
25#include "XtensaGenInstrInfo.inc"
26
27namespace llvm {
28
29class XtensaTargetMachine;
30class XtensaSubtarget;
31class XtensaInstrInfo : public XtensaGenInstrInfo {
32 const XtensaRegisterInfo RI;
33 const XtensaSubtarget &STI;
34
35public:
36 XtensaInstrInfo(const XtensaSubtarget &STI);
37
38 void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
39 MachineBasicBlock::iterator I) const;
40
41 // Return the XtensaRegisterInfo, which this class owns.
42 const XtensaRegisterInfo &getRegisterInfo() const { return RI; }
43
44 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
45 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
46 bool KillSrc) const override;
47
48 void storeRegToStackSlot(MachineBasicBlock &MBB,
49 MachineBasicBlock::iterator MBBI, Register SrcReg,
50 bool isKill, int FrameIndex,
51 const TargetRegisterClass *RC,
52 const TargetRegisterInfo *TRI,
53 Register VReg) const override;
54
55 void loadRegFromStackSlot(MachineBasicBlock &MBB,
56 MachineBasicBlock::iterator MBBI, Register DestReg,
57 int FrameIdx, const TargetRegisterClass *RC,
58 const TargetRegisterInfo *TRI,
59 Register VReg) const override;
60
61 // Get the load and store opcodes for a given register class and offset.
62 void getLoadStoreOpcodes(const TargetRegisterClass *RC, unsigned &LoadOpcode,
63 unsigned &StoreOpcode, int64_t offset) const;
64
65 // Emit code before MBBI in MI to move immediate value Value into
66 // physical register Reg.
67 void loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
68 unsigned *Reg, int64_t Value) const;
69
70 const XtensaSubtarget &getSubtarget() const { return STI; }
71};
72} // end namespace llvm
73
74#endif /* LLVM_LIB_TARGET_XTENSA_XTENSAINSTRINFO_H */
75

source code of llvm/lib/Target/Xtensa/XtensaInstrInfo.h