1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * linux/arch/alpha/kernel/core_lca.c |
4 | * |
5 | * Written by David Mosberger (davidm@cs.arizona.edu) with some code |
6 | * taken from Dave Rusling's (david.rusling@reo.mts.dec.com) 32-bit |
7 | * bios code. |
8 | * |
9 | * Code common to all LCA core logic chips. |
10 | */ |
11 | |
12 | #define __EXTERN_INLINE inline |
13 | #include <asm/io.h> |
14 | #include <asm/core_lca.h> |
15 | #undef __EXTERN_INLINE |
16 | |
17 | #include <linux/types.h> |
18 | #include <linux/pci.h> |
19 | #include <linux/init.h> |
20 | #include <linux/tty.h> |
21 | |
22 | #include <asm/ptrace.h> |
23 | #include <asm/irq_regs.h> |
24 | #include <asm/smp.h> |
25 | |
26 | #include "proto.h" |
27 | #include "pci_impl.h" |
28 | |
29 | |
30 | /* |
31 | * BIOS32-style PCI interface: |
32 | */ |
33 | |
34 | /* |
35 | * Machine check reasons. Defined according to PALcode sources |
36 | * (osf.h and platform.h). |
37 | */ |
38 | #define MCHK_K_TPERR 0x0080 |
39 | #define MCHK_K_TCPERR 0x0082 |
40 | #define MCHK_K_HERR 0x0084 |
41 | #define MCHK_K_ECC_C 0x0086 |
42 | #define MCHK_K_ECC_NC 0x0088 |
43 | #define MCHK_K_UNKNOWN 0x008A |
44 | #define MCHK_K_CACKSOFT 0x008C |
45 | #define MCHK_K_BUGCHECK 0x008E |
46 | #define MCHK_K_OS_BUGCHECK 0x0090 |
47 | #define MCHK_K_DCPERR 0x0092 |
48 | #define MCHK_K_ICPERR 0x0094 |
49 | |
50 | |
51 | /* |
52 | * Platform-specific machine-check reasons: |
53 | */ |
54 | #define MCHK_K_SIO_SERR 0x204 /* all platforms so far */ |
55 | #define MCHK_K_SIO_IOCHK 0x206 /* all platforms so far */ |
56 | #define MCHK_K_DCSR 0x208 /* all but Noname */ |
57 | |
58 | |
59 | /* |
60 | * Given a bus, device, and function number, compute resulting |
61 | * configuration space address and setup the LCA_IOC_CONF register |
62 | * accordingly. It is therefore not safe to have concurrent |
63 | * invocations to configuration space access routines, but there |
64 | * really shouldn't be any need for this. |
65 | * |
66 | * Type 0: |
67 | * |
68 | * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 |
69 | * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 |
70 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ |
71 | * | | | | | | | | | | | | | | | | | | | | | | | |F|F|F|R|R|R|R|R|R|0|0| |
72 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ |
73 | * |
74 | * 31:11 Device select bit. |
75 | * 10:8 Function number |
76 | * 7:2 Register number |
77 | * |
78 | * Type 1: |
79 | * |
80 | * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 |
81 | * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 |
82 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ |
83 | * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1| |
84 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ |
85 | * |
86 | * 31:24 reserved |
87 | * 23:16 bus number (8 bits = 128 possible buses) |
88 | * 15:11 Device number (5 bits) |
89 | * 10:8 function number |
90 | * 7:2 register number |
91 | * |
92 | * Notes: |
93 | * The function number selects which function of a multi-function device |
94 | * (e.g., SCSI and Ethernet). |
95 | * |
96 | * The register selects a DWORD (32 bit) register offset. Hence it |
97 | * doesn't get shifted by 2 bits as we want to "drop" the bottom two |
98 | * bits. |
99 | */ |
100 | |
101 | static int |
102 | mk_conf_addr(struct pci_bus *pbus, unsigned int device_fn, int where, |
103 | unsigned long *pci_addr) |
104 | { |
105 | unsigned long addr; |
106 | u8 bus = pbus->number; |
107 | |
108 | if (bus == 0) { |
109 | int device = device_fn >> 3; |
110 | int func = device_fn & 0x7; |
111 | |
112 | /* Type 0 configuration cycle. */ |
113 | |
114 | if (device > 12) { |
115 | return -1; |
116 | } |
117 | |
118 | *(vulp)LCA_IOC_CONF = 0; |
119 | addr = (1 << (11 + device)) | (func << 8) | where; |
120 | } else { |
121 | /* Type 1 configuration cycle. */ |
122 | *(vulp)LCA_IOC_CONF = 1; |
123 | addr = (bus << 16) | (device_fn << 8) | where; |
124 | } |
125 | *pci_addr = addr; |
126 | return 0; |
127 | } |
128 | |
129 | static unsigned int |
130 | conf_read(unsigned long addr) |
131 | { |
132 | unsigned long flags, code, stat0; |
133 | unsigned int value; |
134 | |
135 | local_irq_save(flags); |
136 | |
137 | /* Reset status register to avoid losing errors. */ |
138 | stat0 = *(vulp)LCA_IOC_STAT0; |
139 | *(vulp)LCA_IOC_STAT0 = stat0; |
140 | mb(); |
141 | |
142 | /* Access configuration space. */ |
143 | value = *(vuip)addr; |
144 | draina(); |
145 | |
146 | stat0 = *(vulp)LCA_IOC_STAT0; |
147 | if (stat0 & LCA_IOC_STAT0_ERR) { |
148 | code = ((stat0 >> LCA_IOC_STAT0_CODE_SHIFT) |
149 | & LCA_IOC_STAT0_CODE_MASK); |
150 | if (code != 1) { |
151 | printk("lca.c:conf_read: got stat0=%lx\n" , stat0); |
152 | } |
153 | |
154 | /* Reset error status. */ |
155 | *(vulp)LCA_IOC_STAT0 = stat0; |
156 | mb(); |
157 | |
158 | /* Reset machine check. */ |
159 | wrmces(mces: 0x7); |
160 | |
161 | value = 0xffffffff; |
162 | } |
163 | local_irq_restore(flags); |
164 | return value; |
165 | } |
166 | |
167 | static void |
168 | conf_write(unsigned long addr, unsigned int value) |
169 | { |
170 | unsigned long flags, code, stat0; |
171 | |
172 | local_irq_save(flags); /* avoid getting hit by machine check */ |
173 | |
174 | /* Reset status register to avoid losing errors. */ |
175 | stat0 = *(vulp)LCA_IOC_STAT0; |
176 | *(vulp)LCA_IOC_STAT0 = stat0; |
177 | mb(); |
178 | |
179 | /* Access configuration space. */ |
180 | *(vuip)addr = value; |
181 | draina(); |
182 | |
183 | stat0 = *(vulp)LCA_IOC_STAT0; |
184 | if (stat0 & LCA_IOC_STAT0_ERR) { |
185 | code = ((stat0 >> LCA_IOC_STAT0_CODE_SHIFT) |
186 | & LCA_IOC_STAT0_CODE_MASK); |
187 | if (code != 1) { |
188 | printk("lca.c:conf_write: got stat0=%lx\n" , stat0); |
189 | } |
190 | |
191 | /* Reset error status. */ |
192 | *(vulp)LCA_IOC_STAT0 = stat0; |
193 | mb(); |
194 | |
195 | /* Reset machine check. */ |
196 | wrmces(mces: 0x7); |
197 | } |
198 | local_irq_restore(flags); |
199 | } |
200 | |
201 | static int |
202 | lca_read_config(struct pci_bus *bus, unsigned int devfn, int where, |
203 | int size, u32 *value) |
204 | { |
205 | unsigned long addr, pci_addr; |
206 | long mask; |
207 | int shift; |
208 | |
209 | if (mk_conf_addr(pbus: bus, device_fn: devfn, where, pci_addr: &pci_addr)) |
210 | return PCIBIOS_DEVICE_NOT_FOUND; |
211 | |
212 | shift = (where & 3) * 8; |
213 | mask = (size - 1) * 8; |
214 | addr = (pci_addr << 5) + mask + LCA_CONF; |
215 | *value = conf_read(addr) >> (shift); |
216 | return PCIBIOS_SUCCESSFUL; |
217 | } |
218 | |
219 | static int |
220 | lca_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size, |
221 | u32 value) |
222 | { |
223 | unsigned long addr, pci_addr; |
224 | long mask; |
225 | |
226 | if (mk_conf_addr(pbus: bus, device_fn: devfn, where, pci_addr: &pci_addr)) |
227 | return PCIBIOS_DEVICE_NOT_FOUND; |
228 | |
229 | mask = (size - 1) * 8; |
230 | addr = (pci_addr << 5) + mask + LCA_CONF; |
231 | conf_write(addr, value: value << ((where & 3) * 8)); |
232 | return PCIBIOS_SUCCESSFUL; |
233 | } |
234 | |
235 | struct pci_ops lca_pci_ops = |
236 | { |
237 | .read = lca_read_config, |
238 | .write = lca_write_config, |
239 | }; |
240 | |
241 | void |
242 | lca_pci_tbi(struct pci_controller *hose, dma_addr_t start, dma_addr_t end) |
243 | { |
244 | wmb(); |
245 | *(vulp)LCA_IOC_TBIA = 0; |
246 | mb(); |
247 | } |
248 | |
249 | void __init |
250 | lca_init_arch(void) |
251 | { |
252 | struct pci_controller *hose; |
253 | |
254 | /* |
255 | * Create our single hose. |
256 | */ |
257 | |
258 | pci_isa_hose = hose = alloc_pci_controller(); |
259 | hose->io_space = &ioport_resource; |
260 | hose->mem_space = &iomem_resource; |
261 | hose->index = 0; |
262 | |
263 | hose->sparse_mem_base = LCA_SPARSE_MEM - IDENT_ADDR; |
264 | hose->dense_mem_base = LCA_DENSE_MEM - IDENT_ADDR; |
265 | hose->sparse_io_base = LCA_IO - IDENT_ADDR; |
266 | hose->dense_io_base = 0; |
267 | |
268 | /* |
269 | * Set up the PCI to main memory translation windows. |
270 | * |
271 | * Mimic the SRM settings for the direct-map window. |
272 | * Window 0 is scatter-gather 8MB at 8MB (for isa). |
273 | * Window 1 is direct access 1GB at 1GB. |
274 | * |
275 | * Note that we do not try to save any of the DMA window CSRs |
276 | * before setting them, since we cannot read those CSRs on LCA. |
277 | */ |
278 | hose->sg_isa = iommu_arena_new(hose, 0x00800000, 0x00800000, |
279 | SMP_CACHE_BYTES); |
280 | hose->sg_pci = NULL; |
281 | __direct_map_base = 0x40000000; |
282 | __direct_map_size = 0x40000000; |
283 | |
284 | *(vulp)LCA_IOC_W_BASE0 = hose->sg_isa->dma_base | (3UL << 32); |
285 | *(vulp)LCA_IOC_W_MASK0 = (hose->sg_isa->size - 1) & 0xfff00000; |
286 | *(vulp)LCA_IOC_T_BASE0 = virt_to_phys(hose->sg_isa->ptes); |
287 | |
288 | *(vulp)LCA_IOC_W_BASE1 = __direct_map_base | (2UL << 32); |
289 | *(vulp)LCA_IOC_W_MASK1 = (__direct_map_size - 1) & 0xfff00000; |
290 | *(vulp)LCA_IOC_T_BASE1 = 0; |
291 | |
292 | *(vulp)LCA_IOC_TB_ENA = 0x80; |
293 | |
294 | lca_pci_tbi(hose, start: 0, end: -1); |
295 | |
296 | /* |
297 | * Disable PCI parity for now. The NCR53c810 chip has |
298 | * troubles meeting the PCI spec which results in |
299 | * data parity errors. |
300 | */ |
301 | *(vulp)LCA_IOC_PAR_DIS = 1UL<<5; |
302 | |
303 | /* |
304 | * Finally, set up for restoring the correct HAE if using SRM. |
305 | * Again, since we cannot read many of the CSRs on the LCA, |
306 | * one of which happens to be the HAE, we save the value that |
307 | * the SRM will expect... |
308 | */ |
309 | if (alpha_using_srm) |
310 | srm_hae = 0x80000000UL; |
311 | } |
312 | |
313 | /* |
314 | * Constants used during machine-check handling. I suppose these |
315 | * could be moved into lca.h but I don't see much reason why anybody |
316 | * else would want to use them. |
317 | */ |
318 | |
319 | #define ESR_EAV (1UL<< 0) /* error address valid */ |
320 | #define ESR_CEE (1UL<< 1) /* correctable error */ |
321 | #define ESR_UEE (1UL<< 2) /* uncorrectable error */ |
322 | #define ESR_WRE (1UL<< 3) /* write-error */ |
323 | #define ESR_SOR (1UL<< 4) /* error source */ |
324 | #define ESR_CTE (1UL<< 7) /* cache-tag error */ |
325 | #define ESR_MSE (1UL<< 9) /* multiple soft errors */ |
326 | #define ESR_MHE (1UL<<10) /* multiple hard errors */ |
327 | #define ESR_NXM (1UL<<12) /* non-existent memory */ |
328 | |
329 | #define IOC_ERR ( 1<<4) /* ioc logs an error */ |
330 | #define IOC_CMD_SHIFT 0 |
331 | #define IOC_CMD (0xf<<IOC_CMD_SHIFT) |
332 | #define IOC_CODE_SHIFT 8 |
333 | #define IOC_CODE (0xf<<IOC_CODE_SHIFT) |
334 | #define IOC_LOST ( 1<<5) |
335 | #define IOC_P_NBR ((__u32) ~((1<<13) - 1)) |
336 | |
337 | static void |
338 | mem_error(unsigned long esr, unsigned long ear) |
339 | { |
340 | printk(" %s %s error to %s occurred at address %x\n" , |
341 | ((esr & ESR_CEE) ? "Correctable" : |
342 | (esr & ESR_UEE) ? "Uncorrectable" : "A" ), |
343 | (esr & ESR_WRE) ? "write" : "read" , |
344 | (esr & ESR_SOR) ? "memory" : "b-cache" , |
345 | (unsigned) (ear & 0x1ffffff8)); |
346 | if (esr & ESR_CTE) { |
347 | printk(" A b-cache tag parity error was detected.\n" ); |
348 | } |
349 | if (esr & ESR_MSE) { |
350 | printk(" Several other correctable errors occurred.\n" ); |
351 | } |
352 | if (esr & ESR_MHE) { |
353 | printk(" Several other uncorrectable errors occurred.\n" ); |
354 | } |
355 | if (esr & ESR_NXM) { |
356 | printk(" Attempted to access non-existent memory.\n" ); |
357 | } |
358 | } |
359 | |
360 | static void |
361 | ioc_error(__u32 stat0, __u32 stat1) |
362 | { |
363 | static const char * const pci_cmd[] = { |
364 | "Interrupt Acknowledge" , "Special" , "I/O Read" , "I/O Write" , |
365 | "Rsvd 1" , "Rsvd 2" , "Memory Read" , "Memory Write" , "Rsvd3" , |
366 | "Rsvd4" , "Configuration Read" , "Configuration Write" , |
367 | "Memory Read Multiple" , "Dual Address" , "Memory Read Line" , |
368 | "Memory Write and Invalidate" |
369 | }; |
370 | static const char * const err_name[] = { |
371 | "exceeded retry limit" , "no device" , "bad data parity" , |
372 | "target abort" , "bad address parity" , "page table read error" , |
373 | "invalid page" , "data error" |
374 | }; |
375 | unsigned code = (stat0 & IOC_CODE) >> IOC_CODE_SHIFT; |
376 | unsigned cmd = (stat0 & IOC_CMD) >> IOC_CMD_SHIFT; |
377 | |
378 | printk(" %s initiated PCI %s cycle to address %x" |
379 | " failed due to %s.\n" , |
380 | code > 3 ? "PCI" : "CPU" , pci_cmd[cmd], stat1, err_name[code]); |
381 | |
382 | if (code == 5 || code == 6) { |
383 | printk(" (Error occurred at PCI memory address %x.)\n" , |
384 | (stat0 & ~IOC_P_NBR)); |
385 | } |
386 | if (stat0 & IOC_LOST) { |
387 | printk(" Other PCI errors occurred simultaneously.\n" ); |
388 | } |
389 | } |
390 | |
391 | void |
392 | lca_machine_check(unsigned long vector, unsigned long la_ptr) |
393 | { |
394 | const char * reason; |
395 | union el_lca el; |
396 | |
397 | el.c = (struct el_common *) la_ptr; |
398 | |
399 | wrmces(mces: rdmces()); /* reset machine check pending flag */ |
400 | |
401 | printk(KERN_CRIT "LCA machine check: vector=%#lx pc=%#lx code=%#x\n" , |
402 | vector, get_irq_regs()->pc, (unsigned int) el.c->code); |
403 | |
404 | /* |
405 | * The first quadword after the common header always seems to |
406 | * be the machine check reason---don't know why this isn't |
407 | * part of the common header instead. In the case of a long |
408 | * logout frame, the upper 32 bits is the machine check |
409 | * revision level, which we ignore for now. |
410 | */ |
411 | switch ((unsigned int) el.c->code) { |
412 | case MCHK_K_TPERR: reason = "tag parity error" ; break; |
413 | case MCHK_K_TCPERR: reason = "tag control parity error" ; break; |
414 | case MCHK_K_HERR: reason = "access to non-existent memory" ; break; |
415 | case MCHK_K_ECC_C: reason = "correctable ECC error" ; break; |
416 | case MCHK_K_ECC_NC: reason = "non-correctable ECC error" ; break; |
417 | case MCHK_K_CACKSOFT: reason = "MCHK_K_CACKSOFT" ; break; |
418 | case MCHK_K_BUGCHECK: reason = "illegal exception in PAL mode" ; break; |
419 | case MCHK_K_OS_BUGCHECK: reason = "callsys in kernel mode" ; break; |
420 | case MCHK_K_DCPERR: reason = "d-cache parity error" ; break; |
421 | case MCHK_K_ICPERR: reason = "i-cache parity error" ; break; |
422 | case MCHK_K_SIO_SERR: reason = "SIO SERR occurred on PCI bus" ; break; |
423 | case MCHK_K_SIO_IOCHK: reason = "SIO IOCHK occurred on ISA bus" ; break; |
424 | case MCHK_K_DCSR: reason = "MCHK_K_DCSR" ; break; |
425 | case MCHK_K_UNKNOWN: |
426 | default: reason = "unknown" ; break; |
427 | } |
428 | |
429 | switch (el.c->size) { |
430 | case sizeof(struct el_lca_mcheck_short): |
431 | printk(KERN_CRIT |
432 | " Reason: %s (short frame%s, dc_stat=%#lx):\n" , |
433 | reason, el.c->retry ? ", retryable" : "" , |
434 | el.s->dc_stat); |
435 | if (el.s->esr & ESR_EAV) { |
436 | mem_error(esr: el.s->esr, ear: el.s->ear); |
437 | } |
438 | if (el.s->ioc_stat0 & IOC_ERR) { |
439 | ioc_error(stat0: el.s->ioc_stat0, stat1: el.s->ioc_stat1); |
440 | } |
441 | break; |
442 | |
443 | case sizeof(struct el_lca_mcheck_long): |
444 | printk(KERN_CRIT " Reason: %s (long frame%s):\n" , |
445 | reason, el.c->retry ? ", retryable" : "" ); |
446 | printk(KERN_CRIT |
447 | " reason: %#lx exc_addr: %#lx dc_stat: %#lx\n" , |
448 | el.l->pt[0], el.l->exc_addr, el.l->dc_stat); |
449 | printk(KERN_CRIT " car: %#lx\n" , el.l->car); |
450 | if (el.l->esr & ESR_EAV) { |
451 | mem_error(esr: el.l->esr, ear: el.l->ear); |
452 | } |
453 | if (el.l->ioc_stat0 & IOC_ERR) { |
454 | ioc_error(stat0: el.l->ioc_stat0, stat1: el.l->ioc_stat1); |
455 | } |
456 | break; |
457 | |
458 | default: |
459 | printk(KERN_CRIT " Unknown errorlog size %d\n" , el.c->size); |
460 | } |
461 | |
462 | /* Dump the logout area to give all info. */ |
463 | #ifdef CONFIG_VERBOSE_MCHECK |
464 | if (alpha_verbose_mcheck > 1) { |
465 | unsigned long * ptr = (unsigned long *) la_ptr; |
466 | long i; |
467 | for (i = 0; i < el.c->size / sizeof(long); i += 2) { |
468 | printk(KERN_CRIT " +%8lx %016lx %016lx\n" , |
469 | i*sizeof(long), ptr[i], ptr[i+1]); |
470 | } |
471 | } |
472 | #endif /* CONFIG_VERBOSE_MCHECK */ |
473 | } |
474 | |
475 | /* |
476 | * The following routines are needed to support the SPEED changing |
477 | * necessary to successfully manage the thermal problem on the AlphaBook1. |
478 | */ |
479 | |
480 | void |
481 | lca_clock_print(void) |
482 | { |
483 | long pmr_reg; |
484 | |
485 | pmr_reg = LCA_READ_PMR; |
486 | |
487 | printk("Status of clock control:\n" ); |
488 | printk("\tPrimary clock divisor\t0x%lx\n" , LCA_GET_PRIMARY(pmr_reg)); |
489 | printk("\tOverride clock divisor\t0x%lx\n" , LCA_GET_OVERRIDE(pmr_reg)); |
490 | printk("\tInterrupt override is %s\n" , |
491 | (pmr_reg & LCA_PMR_INTO) ? "on" : "off" ); |
492 | printk("\tDMA override is %s\n" , |
493 | (pmr_reg & LCA_PMR_DMAO) ? "on" : "off" ); |
494 | |
495 | } |
496 | |
497 | int |
498 | lca_get_clock(void) |
499 | { |
500 | long pmr_reg; |
501 | |
502 | pmr_reg = LCA_READ_PMR; |
503 | return(LCA_GET_PRIMARY(pmr_reg)); |
504 | |
505 | } |
506 | |
507 | void |
508 | lca_clock_fiddle(int divisor) |
509 | { |
510 | long pmr_reg; |
511 | |
512 | pmr_reg = LCA_READ_PMR; |
513 | LCA_SET_PRIMARY_CLOCK(pmr_reg, divisor); |
514 | /* lca_norm_clock = divisor; */ |
515 | LCA_WRITE_PMR(pmr_reg); |
516 | mb(); |
517 | } |
518 | |